Index: src/southbridge/nvidia/ck804/Kconfig
===================================================================
--- src/southbridge/nvidia/ck804/Kconfig	(revision 5849)
+++ src/southbridge/nvidia/ck804/Kconfig	(working copy)
@@ -1,6 +1,7 @@
 config SOUTHBRIDGE_NVIDIA_CK804
 	bool
 	select HAVE_HARD_RESET
+	select HAVE_USBDEBUG
 	select IOAPIC
 
 config ID_SECTION_OFFSET
Index: src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c
===================================================================
--- src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c	(revision 5849)
+++ src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c	(working copy)
@@ -26,9 +26,9 @@
 #include <device/pci_def.h>
 
 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
-#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
+#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
 #else
-#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
+#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
 #endif
 
 #define EHCI_BAR		0xFEF00000	/* EHCI BAR address */
@@ -38,7 +38,7 @@
 void set_debug_port(unsigned int port)
 {
 	u32 dword;
-	device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */
+	device_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */
 
 	/* Write the port number to 0x74[15:12]. */
 	dword = pci_read_config32(dev, 0x74);
@@ -47,9 +47,9 @@
 	pci_write_config32(dev, 0x74, dword);
 }
 
-static void mcp55_enable_usbdebug(unsigned int port)
+static void ck804_enable_usbdebug(unsigned int port)
 {
-	device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */
+	device_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */
 
 	/* Mark the requested physical USB port (1-15) as the Debug Port. */
 	set_debug_port(port);