1.
intel Ethernet PHY I211 connected on I3-U6100 PCIE lane 1, I211 is not shown in lspci.
and serial port log:
PCI: 00:1c.0 scanning...
do_pci_scan_bridge for PCI: 00:1c.0
PCI: pci_scan_bus for bus 01
POST: 0x24
POST: 0x25
POST: 0x55
scan_bus: scanning of bus PCI: 00:1c.0 took 12591 usecs
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In our previous version board, I211 is on PCIE lane 5, which is shown in lspci and works fine. and serial port log:
PCI: 00:1c.0 scanning...
do_pci_scan_bridge for PCI: 00:1c.0
PCI: pci_scan_bus for bus 01
POST: 0x24
PCI: 01:00.0 [8086/1539] enabled
POST: 0x25
POST: 0x55
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x50
Capability: type 0x11 @ 0x70
Capability: type 0x10 @ 0xa0
Capability: type 0x10 @ 0x40
Enabling Common Clock Configuration
PCIE CLK PM is not supported by endpoint
ASPM: Enabled L1
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x50
Capability: type 0x11 @ 0x70
Capability: type 0x10 @ 0xa0
Failed to enable LTR for dev = PCI: 01:00.0
scan_bus: scanning of bus PCI: 00:1c.0 took 56231 usecs
2.
A m.2 sata on pcie lane 11(sata 1B) doesn't work(not shown on lsblk). On the previous version board, sata is on PCIE lane 8 (1A) and works fine.
The following 3 files are changed for this new board from the previous version board .
1.IFWI configuration file settings,
2. devicetree.cb
3. gpio.h (SATAXPCIE1 detect)