The
two major issues with bringing up the memory subsystem on a new board are SPD
parameters and DQ/DQS layout
Specifically,
if you look at the apollolake rvp subtree, you can see a whole bunch of
parameters being set in romstage.c. Some of it is fairly straightforward.
Swizzling tables are not and require you to be able to read schematic (and
have access to it in the first place)
Obviously,
the problem could be elsewhere. I would start with enabling MRC debug and
perhaps posting the MRC output
I
port the Coreboot to a board with an SOC Intel Atom E3845 and use FSP for the
Baytrail family. The result - postcode is 0x2A. From the descriptions on the
Internet, I understand that the problem is in the incorrect memory
parameters.
Question: are there any utilities or methods that will help to get the
correct memory parameters when working a regular BIOS from Linux or Windows
systems?
Many thanks!
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