coreboot-4.8.1-6794ce02d45273427c1c6675950c8468380c040a Wed Aug 15 07:13:10 UTC 2018 bootblock starting... FSP TempRamInit successful... CBFS: 'Master Header Locator' located CBFS at [20000:1fffc0) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 80 size 703c coreboot-4.8.1-6794ce02d45273427c1c6675950c8468380c040a Wed Aug 15 07:13:10 UTC 2018 romstage starting... FSP TempRamInit was successful... GPIO table: 0xffe26540, entry num: 0x98! Changing GpioPad PID: c2 Offset: 0x418 PadModeP1: 1 P2: 2 R: 0x05000602 Fx05000a02 ! Changing GpioPad PID: c2 Offset: 0x470 PadModeP1: 0 P2: 2 R: 0x45000300 Fx05000b00 ! Changing GpioPad PID: c2 Offset: 0x478 PadModeP1: 0 P2: 2 R: 0x45000300 Fx05000b00 ! Changing GpioPad PID: c2 Offset: 0x480 PadModeP1: 0 P2: 2 R: 0x45000300 Fx05000b00 ! Changing GpioPad PID: c2 Offset: 0x488 PadModeP1: 0 P2: 2 R: 0x45000300 Fx05000b00 ! Changing GpioPad PID: c2 Offset: 0x490 PadModeP1: 0 P2: 2 R: 0x45000300 Fx05000b00 ! Changing GpioPad PID: c2 Offset: 0x498 PadModeP1: 0 P2: 2 R: 0x45000300 Fx05000b00 ! Changing GpioPad PID: c2 Offset: 0x4a0 PadModeP1: 0 P2: 2 R: 0x45000300 Fx05000b00 ! Changing GpioPad PID: c2 Offset: 0x4a8 PadModeP1: 0 P2: 2 R: 0x45000300 Fx05000b00 ! Changing GpioPad PID: c2 Offset: 0x4b0 PadModeP1: 0 P2: 2 R: 0x45000300 Fx05000b00 ! Changing GpioPad PID: c2 Offset: 0x4d8 PadModeP1: 0 P2: 3 R: 0x45000200 Fx45000e00 ! Changing GpioPad PID: c2 Offset: 0x500 PadModeP1: 1 P2: 0 R: 0x45000602 Fx45000202 ! Changing GpioPad PID: c5 Offset: 0x498 PadModeP1: 2 P2: 3 R: 0x45000a02 Fx05000e02 ! Changing GpioPad PID: c5 Offset: 0x4a0 PadModeP1: 3 P2: 0 R: 0x45000e00 Fx45040100 ! Changing GpioPad PID: c5 Offset: 0x4a8 PadModeP1: 1 P2: 0 R: 0x45000602 Fx45020102 ! Changing GpioPad PID: c5 Offset: 0x4b0 PadModeP1: 1 P2: 3 R: 0x45000602 Fx45000e02 ! Changing GpioPad PID: c5 Offset: 0x4c8 PadModeP1: 0 P2: 3 R: 0x45000300 Fx05000f00 ! Changing GpioPad PID: c5 Offset: 0x4d0 PadModeP1: 0 P2: 3 R: 0x45000300 Fx05000f00 ! GPIO WARNING: Accessing pad not owned by host (Group=2, Pad=21)!The owner is CSME ** Please make sure the GPIO usage in sync between CSME/ISH and Host IA FW configuration. ** All the GPIO occupied by CSME/ISH should not do any configuration by Host IA FW. GPIO WARNING: Accessing pad not owned by host (Group=2, Pad=22)!The owner is CSME ** Please make sure the GPIO usage in sync between CSME/ISH and Host IA FW configuration. ** All the GPIO occupied by CSME/ISH should not do any configuration by Host IA FW. Changing GpioPad PID: c5 Offset: 0x560 PadModeP1: 0 P2: 1 R: 0x45000200 Fx45000600 ! Changing GpioPad PID: c5 Offset: 0x568 PadModeP1: 0 P2: 3 R: 0x45000200 Fx45000e00 ! Changing GpioPad PID: c5 Offset: 0x570 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! Changing GpioPad PID: c5 Offset: 0x578 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! Changing GpioPad PID: c5 Offset: 0x580 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! GPIO WARNING: Accessing pad not owned by host (Group=2, Pad=39)!The owner is CSME ** Please make sure the GPIO usage in sync between CSME/ISH and Host IA FW configuration. ** All the GPIO occupied by CSME/ISH should not do any configuration by Host IA FW. GPIO WARNING: Accessing pad not owned by host (Group=2, Pad=40)!The owner is CSME ** Please make sure the GPIO usage in sync between CSME/ISH and Host IA FW configuration. ** All the GPIO occupied by CSME/ISH should not do any configuration by Host IA FW. GPIO WARNING: Accessing pad not owned by host (Group=2, Pad=48)!The owner is CSME ** Please make sure the GPIO usage in sync between CSME/ISH and Host IA FW configuration. ** All the GPIO occupied by CSME/ISH should not do any configuration by Host IA FW. Changing GpioPad PID: c5 Offset: 0x618 PadModeP1: 1 P2: 0 R: 0x45000600 Fx45000100 ! Changing GpioPad PID: c5 Offset: 0x620 PadModeP1: 0 P2: 0 R: 0x44000300 Fx44000000 ! Changing GpioPad PID: c5 Offset: 0x628 PadModeP1: 0 P2: 0 R: 0x44000300 Fx44000100 ! Changing GpioPad PID: c5 Offset: 0x630 PadModeP1: 0 P2: 0 R: 0x44000300 Fx44000100 ! Changing GpioPad PID: c5 Offset: 0x648 PadModeP1: 0 P2: 1 R: 0x45000200 Fx45000600 ! Changing GpioPad PID: c5 Offset: 0x688 PadModeP1: 1 P2: 0 R: 0x44000600 Fx44000100 ! Changing GpioPad PID: c5 Offset: 0x710 PadModeP1: 1 P2: 0 R: 0x45000700 Fx45000100 ! Changing GpioPad PID: c5 Offset: 0x718 PadModeP1: 1 P2: 2 R: 0x45000702 Fx45000b02 ! Changing GpioPad PID: c5 Offset: 0x728 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! Changing GpioPad PID: c5 Offset: 0x730 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! Changing GpioPad PID: c5 Offset: 0x738 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! Changing GpioPad PID: c5 Offset: 0x740 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! Changing GpioPad PID: c5 Offset: 0x748 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! Changing GpioPad PID: c5 Offset: 0x750 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! Changing GpioPad PID: c5 Offset: 0x758 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! Changing GpioPad PID: c5 Offset: 0x760 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! Changing GpioPad PID: c5 Offset: 0x768 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! Changing GpioPad PID: c5 Offset: 0x770 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! Changing GpioPad PID: c5 Offset: 0x778 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! Changing GpioPad PID: c5 Offset: 0x780 PadModeP1: 0 P2: 0 R: 0x45000200 Fx45000200 ! TCO base address set to 0x400! CBFS: 'Master Header Locator' located CBFS at [20000:1fffc0) CBFS: Locating 'fspm.bin' CBFS: Found @ offset 111fc0 size 90000 FMAP: Found "FLASH" version 1.1 at 0. FMAP: base = ffe00000 size = 200000 #areas = 4 FMAP: area RW_MRC_CACHE found @ 10000 (65536 bytes) MRC: no data in 'RW_MRC_CACHE' ============= FSP Spec v2.0 Header Revision v3 (DNV-FSP0 v0.0.1.10) ============= Fsp BootFirmwareVolumeBase - 0xFFF32000 Fsp BootFirmwareVolumeSize - 0x90000 Fsp TemporaryRamBase - 0xFEF60100 Fsp TemporaryRamSize - 0x4FF00 Fsp PeiTemporaryRamBase - 0xFEF60100 Fsp PeiTemporaryRamSize - 0x27F80 Fsp StackBase - 0xFEF88080 Fsp StackSize - 0x27F80 Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A The 0th FV start address is 0x000FFF32000, size is 0x00090000, handle is 0x0 Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38 Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Install PPI: DBE23AA9-A345-4B97-85B6-B226F1617389 Loading PEIM at 0x000FFF3E968 EntryPoint=0x000FFF3EA48 Install PPI: 06E81C58-4AD7-44BC-8390-F10265F72480 Install PPI: 01F34D25-4DE2-23AD-3FF3-36353FF323F1 Install PPI: 4D8B155B-C059-4C8F-8926-06FD4331DB8A Install PPI: A60C6B59-E459-425D-9C69-0BCC9CB27D81 Loading PEIM at 0x000FFF42BB4 EntryPoint=0x000FFF42C94 FSP BUILD ID : 0015.D85 Initialise SYSTEM_CONFIGURATION Initialise PCH_SETUP CustomerRevision: version xxx Updating Policies with Memory Init UPD PCDs... 0x03 : PcdInterleaveMode 0x00 : PcdHalfWidthEnable 0x01 : PcdTclIdle 0x00 : PcdMemoryPreservation 0x00 : PcdMemoryThermalThrottling Install PPI: 70CEA1D9-0FEE-4E68-8F26-5FCD6D092FCC Build PCH_SETUP HOB at 0xFEF61450(0x16C bytes) Build SYSTEM_CONFIGURATION HOB at 0xFEF615D8(0x650 bytes) Build PLATFORM_INFO_HOB HOB at 0xFEF61C40(0xC6 bytes) Install PPI: 2AB86EF5-ECB5-4134-B556-3854CA1FE1B4 Loading PEIM at 0x000FFF46454 EntryPoint=0x000FFF46534 Install PPI: D14319E2-407A-9580-8DE5-51A8FFC6D7D7 Install PPI: EE0EA811-FBD9-4777-B95A-BA4F71101F74 Loading PEIM at 0x000FFF49C44 EntryPoint=0x000FFF49D14 FspInitPreMemEntryPoint() - Start Install PPI: 1F4C6F90-B06B-48D8-A201-BAE5F1CD7D56 Install PPI: EF398D58-9DFD-4103-BF94-78C6F4FE712F Setting BootMode to BOOT_WITH_FULL_CONFIGURATION [SPS] (ICC) MeFiaMuxConfigGet [HECI] Resetting HECI interface (CSR: 80000002/80000008, MEFS1:000F0345) [HECI] Send msg: 80140008 00040000 ... [HECI] Got msg: 80240008 00040000 ... [SPS] (ICC) MeFiaMuxConfigGet: FIA Mux configuration retrieved, number of lanes allowed: (12) [SPS] (ICC) MeFiaMuxConfigGet: Received number of Lanes allowed = 0xC [SPS] (ICC) MeFiaMuxConfigGet: Received FIA Mux Lanes Configuration = 0xF800550000 [SPS] (ICC) MeFiaMuxConfigGet: Received SATA Lanes Configuration = 0x51555555 [SPS] (ICC) MeFiaMuxConfigGet: Received PCIE Root Ports Configuration = 0x10 [SPS] (ICC) MeFiaMuxConfigGet: End - Success FiaMuxCreatePolicyDefaults() MeFiaMuxConfigGet status = Success, MuxConfiguration 0xF800550000, NumLanesAllowed 0xC SataLaneConfiguration 0x51555555, PcieRootPortsConfiguration 0x10 UpdatePeiFiaMuxPolicy SkuNumLanesAllowed: 0xC FiaMuxConfig.MuxConfiguration: 0xF800550000 FiaMuxConfig.SataLaneConfiguration: 0x51555555 FiaMuxConfig.PcieRootPortsConfiguration: 0x10 FiaMuxConfigRequest.MuxConfiguration: 0xF800550000 FiaMuxConfigRequest.SataLaneConfiguration: 0x51555555 FiaMuxConfigRequest.PcieRootPortsConfiguration: 0x10 FIA Mux Policy ready!! Install PPI: 43CC4396-68AF-42DA-A905-4AF2EDEC2847 FIA MUX PEI Policy Initialization Done Install PPI: AEBFFA01-7EDC-49FF-8D88-CB848C5E8670 Silicon PEI Policy Initialization Done policy 80400042 ------------------ PCH SATA Config 0 Policy Override ------------------ Sata controller 0 is not on FIA config ------------------ PCH SATA Config 1 Policy Override ------------------ FIA: SATA controller 1 is enabled FIA Mux Lane 0xC config is 0x0 Disabling port: 0x0 FIA Mux Lane 0xD config is 0x0 Disabling port: 0x1 FIA Mux Lane 0xE config is 0x0 Disabling port: 0x2 FIA Mux Lane 0xF config is 0x0 Disabling port: 0x3 FIA Mux Lane 0x10 config is 0x0 Disabling port: 0x4 FIA Mux Lane 0x11 config is 0x2 FIA Mux Lane 0x12 config is 0x3 Disabling port: 0x6 FIA Mux Lane 0x13 config is 0x3 Disabling port: 0x7 ------------------ PCH USB Config Policy Override ------------------ FIA: XHCI controller is enabled FIA Mux Lane 0x10 config is 0x0 XCHI Port 0x0 is being disabled FIA Mux Lane 0x11 config is 0x2 XCHI Port 0x1 is being disabled FIA Mux Lane 0x12 config is 0x3 XCHI Port 0x2 is enabled FIA Mux Lane 0x13 config is 0x3 XCHI Port 0x3 is enabled PCH_PWRON: NvmSafeRegister = 1 PCH_PWRON: GpioSafeRegister = 0 PCH_PWRON: DmiSafeRegister = 1 PCH_PWRON: SmbusSafeRegister = 0 PCH_PWRON: RtcSafeRegister = 0 PCH_PWRON: ItssSafeRegister = 0 PCH_PWRON: P2sbSafeRegister = 1 PCH_PWRON: PsthSafeRegister = 1 PCH_PWRON: HostPmSafeRegister = 1 PCH_PWRON: ScsSafeRegister = 1 PCH_PWRON: ThermalSafeRegister = 1 PCH_PWRON: PcieSafeRegister = 1 PCH_PWRON: PsfSafeRegister = 1 PCH_PWRON: XhciSafeSettings = 0 PCH_PWRON: XdciSafeSettings = 1 PCH_PWRON: SataPmSafeRegister = 0 PCH_PWRON: FiaSafeRegister = 0 PCH_PWRON: LpcSafeRegister = 0 PCH_PWRON: IshSafeRegister = 1 PCH_PWRON: HdaSafeRegister = 1 PCH_PWRON: DciSafeRegister = 0 PCH_PWRON: CSI2SafeRegister = 1 ------------------------ PCH Print Platform Protocol Start ------------------------ Revision= C AcpiBase= 1800 MctpBroadcastCycle= 0 ------------------ PCH General Config ------------------ SubSystemVendorId= 8086 SubSystemId= 7270 Crid= 0 ------------------ PCH SATA Config 0 ----------------- Enable= 0 SataMode= 0 PortSettings[0] Enabled= 1 PortSettings[0] HotPlug= 1 PortSettings[0] InterlockSw= 0 PortSettings[0] External= 0 PortSettings[0] SpinUp= 0 PortSettings[0] SolidStateDrive= 0 PortSettings[0] DevSlp= 0 PortSettings[0] EnableDitoConfig= 0 PortSettings[0] DmVal= F PortSettings[0] DitoVal= 271 PortSettings[0] ZpOdd= 0 PortSettings[0] HsioRxGen1EqBoostMagEnable= 0 PortSettings[0] HsioRxGen1EqBoostMag= 0 PortSettings[0] HsioRxGen2EqBoostMagEnable= 0 PortSettings[0] HsioRxGen2EqBoostMag= 0 PortSettings[0] HsioRxGen3EqBoostMagEnable= 0 PortSettings[0] HsioRxGen3EqBoostMag= 0 PortSettings[0] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[0] HsioTxGen1DownscaleAmp= 0 PortSettings[0] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[0] HsioTxGen2DownscaleAmp= 0 PortSettings[0] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[0] HsioTxGen3DownscaleAmp= 0 PortSettings[0] HsioTxGen1DeEmphEnable= 0 PortSettings[0] HsioTxGen1DeEmph= 0 PortSettings[0] HsioTxGen2DeEmphEnable= 0 PortSettings[0] HsioTxGen2DeEmph= 0 PortSettings[0] HsioTxGen3DeEmphEnable= 0 PortSettings[0] HsioTxGen3DeEmph= 0 PortSettings[1] Enabled= 1 PortSettings[1] HotPlug= 1 PortSettings[1] InterlockSw= 0 PortSettings[1] External= 0 PortSettings[1] SpinUp= 0 PortSettings[1] SolidStateDrive= 0 PortSettings[1] DevSlp= 0 PortSettings[1] EnableDitoConfig= 0 PortSettings[1] DmVal= F PortSettings[1] DitoVal= 271 PortSettings[1] ZpOdd= 0 PortSettings[1] HsioRxGen1EqBoostMagEnable= 0 PortSettings[1] HsioRxGen1EqBoostMag= 0 PortSettings[1] HsioRxGen2EqBoostMagEnable= 0 PortSettings[1] HsioRxGen2EqBoostMag= 0 PortSettings[1] HsioRxGen3EqBoostMagEnable= 0 PortSettings[1] HsioRxGen3EqBoostMag= 0 PortSettings[1] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[1] HsioTxGen1DownscaleAmp= 0 PortSettings[1] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[1] HsioTxGen2DownscaleAmp= 0 PortSettings[1] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[1] HsioTxGen3DownscaleAmp= 0 PortSettings[1] HsioTxGen1DeEmphEnable= 0 PortSettings[1] HsioTxGen1DeEmph= 0 PortSettings[1] HsioTxGen2DeEmphEnable= 0 PortSettings[1] HsioTxGen2DeEmph= 0 PortSettings[1] HsioTxGen3DeEmphEnable= 0 PortSettings[1] HsioTxGen3DeEmph= 0 PortSettings[2] Enabled= 1 PortSettings[2] HotPlug= 1 PortSettings[2] InterlockSw= 0 PortSettings[2] External= 0 PortSettings[2] SpinUp= 0 PortSettings[2] SolidStateDrive= 0 PortSettings[2] DevSlp= 0 PortSettings[2] EnableDitoConfig= 0 PortSettings[2] DmVal= F PortSettings[2] DitoVal= 271 PortSettings[2] ZpOdd= 0 PortSettings[2] HsioRxGen1EqBoostMagEnable= 0 PortSettings[2] HsioRxGen1EqBoostMag= 0 PortSettings[2] HsioRxGen2EqBoostMagEnable= 0 PortSettings[2] HsioRxGen2EqBoostMag= 0 PortSettings[2] HsioRxGen3EqBoostMagEnable= 0 PortSettings[2] HsioRxGen3EqBoostMag= 0 PortSettings[2] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[2] HsioTxGen1DownscaleAmp= 0 PortSettings[2] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[2] HsioTxGen2DownscaleAmp= 0 PortSettings[2] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[2] HsioTxGen3DownscaleAmp= 0 PortSettings[2] HsioTxGen1DeEmphEnable= 0 PortSettings[2] HsioTxGen1DeEmph= 0 PortSettings[2] HsioTxGen2DeEmphEnable= 0 PortSettings[2] HsioTxGen2DeEmph= 0 PortSettings[2] HsioTxGen3DeEmphEnable= 0 PortSettings[2] HsioTxGen3DeEmph= 0 PortSettings[3] Enabled= 1 PortSettings[3] HotPlug= 1 PortSettings[3] InterlockSw= 0 PortSettings[3] External= 0 PortSettings[3] SpinUp= 0 PortSettings[3] SolidStateDrive= 0 PortSettings[3] DevSlp= 0 PortSettings[3] EnableDitoConfig= 0 PortSettings[3] DmVal= F PortSettings[3] DitoVal= 271 PortSettings[3] ZpOdd= 0 PortSettings[3] HsioRxGen1EqBoostMagEnable= 0 PortSettings[3] HsioRxGen1EqBoostMag= 0 PortSettings[3] HsioRxGen2EqBoostMagEnable= 0 PortSettings[3] HsioRxGen2EqBoostMag= 0 PortSettings[3] HsioRxGen3EqBoostMagEnable= 0 PortSettings[3] HsioRxGen3EqBoostMag= 0 PortSettings[3] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[3] HsioTxGen1DownscaleAmp= 0 PortSettings[3] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[3] HsioTxGen2DownscaleAmp= 0 PortSettings[3] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[3] HsioTxGen3DownscaleAmp= 0 PortSettings[3] HsioTxGen1DeEmphEnable= 0 PortSettings[3] HsioTxGen1DeEmph= 0 PortSettings[3] HsioTxGen2DeEmphEnable= 0 PortSettings[3] HsioTxGen2DeEmph= 0 PortSettings[3] HsioTxGen3DeEmphEnable= 0 PortSettings[3] HsioTxGen3DeEmph= 0 PortSettings[4] Enabled= 1 PortSettings[4] HotPlug= 1 PortSettings[4] InterlockSw= 0 PortSettings[4] External= 0 PortSettings[4] SpinUp= 0 PortSettings[4] SolidStateDrive= 0 PortSettings[4] DevSlp= 0 PortSettings[4] EnableDitoConfig= 0 PortSettings[4] DmVal= F PortSettings[4] DitoVal= 271 PortSettings[4] ZpOdd= 0 PortSettings[4] HsioRxGen1EqBoostMagEnable= 0 PortSettings[4] HsioRxGen1EqBoostMag= 0 PortSettings[4] HsioRxGen2EqBoostMagEnable= 0 PortSettings[4] HsioRxGen2EqBoostMag= 0 PortSettings[4] HsioRxGen3EqBoostMagEnable= 0 PortSettings[4] HsioRxGen3EqBoostMag= 0 PortSettings[4] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[4] HsioTxGen1DownscaleAmp= 0 PortSettings[4] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[4] HsioTxGen2DownscaleAmp= 0 PortSettings[4] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[4] HsioTxGen3DownscaleAmp= 0 PortSettings[4] HsioTxGen1DeEmphEnable= 0 PortSettings[4] HsioTxGen1DeEmph= 0 PortSettings[4] HsioTxGen2DeEmphEnable= 0 PortSettings[4] HsioTxGen2DeEmph= 0 PortSettings[4] HsioTxGen3DeEmphEnable= 0 PortSettings[4] HsioTxGen3DeEmph= 0 PortSettings[5] Enabled= 1 PortSettings[5] HotPlug= 1 PortSettings[5] InterlockSw= 0 PortSettings[5] External= 0 PortSettings[5] SpinUp= 0 PortSettings[5] SolidStateDrive= 0 PortSettings[5] DevSlp= 0 PortSettings[5] EnableDitoConfig= 0 PortSettings[5] DmVal= F PortSettings[5] DitoVal= 271 PortSettings[5] ZpOdd= 0 PortSettings[5] HsioRxGen1EqBoostMagEnable= 0 PortSettings[5] HsioRxGen1EqBoostMag= 0 PortSettings[5] HsioRxGen2EqBoostMagEnable= 0 PortSettings[5] HsioRxGen2EqBoostMag= 0 PortSettings[5] HsioRxGen3EqBoostMagEnable= 0 PortSettings[5] HsioRxGen3EqBoostMag= 0 PortSettings[5] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[5] HsioTxGen1DownscaleAmp= 0 PortSettings[5] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[5] HsioTxGen2DownscaleAmp= 0 PortSettings[5] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[5] HsioTxGen3DownscaleAmp= 0 PortSettings[5] HsioTxGen1DeEmphEnable= 0 PortSettings[5] HsioTxGen1DeEmph= 0 PortSettings[5] HsioTxGen2DeEmphEnable= 0 PortSettings[5] HsioTxGen2DeEmph= 0 PortSettings[5] HsioTxGen3DeEmphEnable= 0 PortSettings[5] HsioTxGen3DeEmph= 0 PortSettings[6] Enabled= 1 PortSettings[6] HotPlug= 1 PortSettings[6] InterlockSw= 0 PortSettings[6] External= 0 PortSettings[6] SpinUp= 0 PortSettings[6] SolidStateDrive= 0 PortSettings[6] DevSlp= 0 PortSettings[6] EnableDitoConfig= 0 PortSettings[6] DmVal= F PortSettings[6] DitoVal= 271 PortSettings[6] ZpOdd= 0 PortSettings[6] HsioRxGen1EqBoostMagEnable= 0 PortSettings[6] HsioRxGen1EqBoostMag= 0 PortSettings[6] HsioRxGen2EqBoostMagEnable= 0 PortSettings[6] HsioRxGen2EqBoostMag= 0 PortSettings[6] HsioRxGen3EqBoostMagEnable= 0 PortSettings[6] HsioRxGen3EqBoostMag= 0 PortSettings[6] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[6] HsioTxGen1DownscaleAmp= 0 PortSettings[6] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[6] HsioTxGen2DownscaleAmp= 0 PortSettings[6] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[6] HsioTxGen3DownscaleAmp= 0 PortSettings[6] HsioTxGen1DeEmphEnable= 0 PortSettings[6] HsioTxGen1DeEmph= 0 PortSettings[6] HsioTxGen2DeEmphEnable= 0 PortSettings[6] HsioTxGen2DeEmph= 0 PortSettings[6] HsioTxGen3DeEmphEnable= 0 PortSettings[6] HsioTxGen3DeEmph= 0 PortSettings[7] Enabled= 1 PortSettings[7] HotPlug= 1 PortSettings[7] InterlockSw= 0 PortSettings[7] External= 0 PortSettings[7] SpinUp= 0 PortSettings[7] SolidStateDrive= 0 PortSettings[7] DevSlp= 0 PortSettings[7] EnableDitoConfig= 0 PortSettings[7] DmVal= F PortSettings[7] DitoVal= 271 PortSettings[7] ZpOdd= 0 PortSettings[7] HsioRxGen1EqBoostMagEnable= 0 PortSettings[7] HsioRxGen1EqBoostMag= 0 PortSettings[7] HsioRxGen2EqBoostMagEnable= 0 PortSettings[7] HsioRxGen2EqBoostMag= 0 PortSettings[7] HsioRxGen3EqBoostMagEnable= 0 PortSettings[7] HsioRxGen3EqBoostMag= 0 PortSettings[7] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[7] HsioTxGen1DownscaleAmp= 0 PortSettings[7] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[7] HsioTxGen2DownscaleAmp= 0 PortSettings[7] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[7] HsioTxGen3DownscaleAmp= 0 PortSettings[7] HsioTxGen1DeEmphEnable= 0 PortSettings[7] HsioTxGen1DeEmph= 0 PortSettings[7] HsioTxGen2DeEmphEnable= 0 PortSettings[7] HsioTxGen2DeEmph= 0 PortSettings[7] HsioTxGen3DeEmphEnable= 0 PortSettings[7] HsioTxGen3DeEmph= 0 RaidAlternateId= 0 Raid0= 1 Raid1= 1 Raid10= 1 Raid5= 1 Irrt= 1 OromUiBanner= 1 OromUiDelay= 0 HddUnlock= 0 LedLocate= 0 IrrtOnly= 1 SmartStorage= 1 SpeedSupport= 3 eSATASpeedLimit= 0 TestMode= 0 SalpSupport= 0 RstPcieStorageRemap[0].Enable = 0 RstPcieStorageRemap[0].RstPcieStoragePort = 0 RstPcieStorageRemap[0].DeviceResetDelay = 64 RstPcieStorageRemap[0].RstPcieStorageTestMode = 0 RstPcieStorageRemap[0].RstPcieStoragePortConfigCheck = 0 RstPcieStorageRemap[0].RstPcieStorageDeviceInterface = 0 RstPcieStorageRemap[0].RstPcieStorageDeviceBarSizeCheck = 0 RstPcieStorageRemap[0].RstPcieStorageDeviceBarSelect = 0 RstPcieStorageRemap[0].RstPcieStorageDeviceInterrupt = 0 RstPcieStorageRemap[0].RstPcieStorageAspmProgramming = 0 RstPcieStorageRemap[0].RstPcieStorageSaveRestore = 0 RstPcieStorageRemap[1].Enable = 0 RstPcieStorageRemap[1].RstPcieStoragePort = 0 RstPcieStorageRemap[1].DeviceResetDelay = 64 RstPcieStorageRemap[1].RstPcieStorageTestMode = 0 RstPcieStorageRemap[1].RstPcieStoragePortConfigCheck = 0 RstPcieStorageRemap[1].RstPcieStorageDeviceInterface = 0 RstPcieStorageRemap[1].RstPcieStorageDeviceBarSizeCheck = 0 RstPcieStorageRemap[1].RstPcieStorageDeviceBarSelect = 0 RstPcieStorageRemap[1].RstPcieStorageDeviceInterrupt = 0 RstPcieStorageRemap[1].RstPcieStorageAspmProgramming = 0 RstPcieStorageRemap[1].RstPcieStorageSaveRestore = 0 RstPcieStorageRemap[2].Enable = 0 RstPcieStorageRemap[2].RstPcieStoragePort = 0 RstPcieStorageRemap[2].DeviceResetDelay = 64 RstPcieStorageRemap[2].RstPcieStorageTestMode = 0 RstPcieStorageRemap[2].RstPcieStoragePortConfigCheck = 0 RstPcieStorageRemap[2].RstPcieStorageDeviceInterface = 0 RstPcieStorageRemap[2].RstPcieStorageDeviceBarSizeCheck = 0 RstPcieStorageRemap[2].RstPcieStorageDeviceBarSelect = 0 RstPcieStorageRemap[2].RstPcieStorageDeviceInterrupt = 0 RstPcieStorageRemap[2].RstPcieStorageAspmProgramming = 0 RstPcieStorageRemap[2].RstPcieStorageSaveRestore = 0 LtrEnable= 0 LtrConfigLock= 0 LtrOverride= 0 SnoopLatencyOverrideMultiplier= 2 SataAssel= 0 RstPcieStorageRemapSataMsix= 0 SnoopLatencyOverrideValue= A ------------------ PCH SATA Config 1 ----------------- Enable= 1 SataMode= 0 PortSettings[0] Enabled= 0 PortSettings[0] HotPlug= 1 PortSettings[0] InterlockSw= 0 PortSettings[0] External= 0 PortSettings[0] SpinUp= 0 PortSettings[0] SolidStateDrive= 0 PortSettings[0] DevSlp= 0 PortSettings[0] EnableDitoConfig= 0 PortSettings[0] DmVal= F PortSettings[0] DitoVal= 271 PortSettings[0] ZpOdd= 0 PortSettings[0] HsioRxGen1EqBoostMagEnable= 0 PortSettings[0] HsioRxGen1EqBoostMag= 0 PortSettings[0] HsioRxGen2EqBoostMagEnable= 0 PortSettings[0] HsioRxGen2EqBoostMag= 0 PortSettings[0] HsioRxGen3EqBoostMagEnable= 0 PortSettings[0] HsioRxGen3EqBoostMag= 0 PortSettings[0] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[0] HsioTxGen1DownscaleAmp= 0 PortSettings[0] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[0] HsioTxGen2DownscaleAmp= 0 PortSettings[0] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[0] HsioTxGen3DownscaleAmp= 0 PortSettings[0] HsioTxGen1DeEmphEnable= 0 PortSettings[0] HsioTxGen1DeEmph= 0 PortSettings[0] HsioTxGen2DeEmphEnable= 0 PortSettings[0] HsioTxGen2DeEmph= 0 PortSettings[0] HsioTxGen3DeEmphEnable= 0 PortSettings[0] HsioTxGen3DeEmph= 0 PortSettings[1] Enabled= 0 PortSettings[1] HotPlug= 1 PortSettings[1] InterlockSw= 0 PortSettings[1] External= 0 PortSettings[1] SpinUp= 0 PortSettings[1] SolidStateDrive= 0 PortSettings[1] DevSlp= 0 PortSettings[1] EnableDitoConfig= 0 PortSettings[1] DmVal= F PortSettings[1] DitoVal= 271 PortSettings[1] ZpOdd= 0 PortSettings[1] HsioRxGen1EqBoostMagEnable= 0 PortSettings[1] HsioRxGen1EqBoostMag= 0 PortSettings[1] HsioRxGen2EqBoostMagEnable= 0 PortSettings[1] HsioRxGen2EqBoostMag= 0 PortSettings[1] HsioRxGen3EqBoostMagEnable= 0 PortSettings[1] HsioRxGen3EqBoostMag= 0 PortSettings[1] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[1] HsioTxGen1DownscaleAmp= 0 PortSettings[1] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[1] HsioTxGen2DownscaleAmp= 0 PortSettings[1] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[1] HsioTxGen3DownscaleAmp= 0 PortSettings[1] HsioTxGen1DeEmphEnable= 0 PortSettings[1] HsioTxGen1DeEmph= 0 PortSettings[1] HsioTxGen2DeEmphEnable= 0 PortSettings[1] HsioTxGen2DeEmph= 0 PortSettings[1] HsioTxGen3DeEmphEnable= 0 PortSettings[1] HsioTxGen3DeEmph= 0 PortSettings[2] Enabled= 0 PortSettings[2] HotPlug= 1 PortSettings[2] InterlockSw= 0 PortSettings[2] External= 0 PortSettings[2] SpinUp= 0 PortSettings[2] SolidStateDrive= 0 PortSettings[2] DevSlp= 0 PortSettings[2] EnableDitoConfig= 0 PortSettings[2] DmVal= F PortSettings[2] DitoVal= 271 PortSettings[2] ZpOdd= 0 PortSettings[2] HsioRxGen1EqBoostMagEnable= 0 PortSettings[2] HsioRxGen1EqBoostMag= 0 PortSettings[2] HsioRxGen2EqBoostMagEnable= 0 PortSettings[2] HsioRxGen2EqBoostMag= 0 PortSettings[2] HsioRxGen3EqBoostMagEnable= 0 PortSettings[2] HsioRxGen3EqBoostMag= 0 PortSettings[2] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[2] HsioTxGen1DownscaleAmp= 0 PortSettings[2] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[2] HsioTxGen2DownscaleAmp= 0 PortSettings[2] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[2] HsioTxGen3DownscaleAmp= 0 PortSettings[2] HsioTxGen1DeEmphEnable= 0 PortSettings[2] HsioTxGen1DeEmph= 0 PortSettings[2] HsioTxGen2DeEmphEnable= 0 PortSettings[2] HsioTxGen2DeEmph= 0 PortSettings[2] HsioTxGen3DeEmphEnable= 0 PortSettings[2] HsioTxGen3DeEmph= 0 PortSettings[3] Enabled= 0 PortSettings[3] HotPlug= 1 PortSettings[3] InterlockSw= 0 PortSettings[3] External= 0 PortSettings[3] SpinUp= 0 PortSettings[3] SolidStateDrive= 0 PortSettings[3] DevSlp= 0 PortSettings[3] EnableDitoConfig= 0 PortSettings[3] DmVal= F PortSettings[3] DitoVal= 271 PortSettings[3] ZpOdd= 0 PortSettings[3] HsioRxGen1EqBoostMagEnable= 0 PortSettings[3] HsioRxGen1EqBoostMag= 0 PortSettings[3] HsioRxGen2EqBoostMagEnable= 0 PortSettings[3] HsioRxGen2EqBoostMag= 0 PortSettings[3] HsioRxGen3EqBoostMagEnable= 0 PortSettings[3] HsioRxGen3EqBoostMag= 0 PortSettings[3] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[3] HsioTxGen1DownscaleAmp= 0 PortSettings[3] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[3] HsioTxGen2DownscaleAmp= 0 PortSettings[3] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[3] HsioTxGen3DownscaleAmp= 0 PortSettings[3] HsioTxGen1DeEmphEnable= 0 PortSettings[3] HsioTxGen1DeEmph= 0 PortSettings[3] HsioTxGen2DeEmphEnable= 0 PortSettings[3] HsioTxGen2DeEmph= 0 PortSettings[3] HsioTxGen3DeEmphEnable= 0 PortSettings[3] HsioTxGen3DeEmph= 0 PortSettings[4] Enabled= 0 PortSettings[4] HotPlug= 1 PortSettings[4] InterlockSw= 0 PortSettings[4] External= 0 PortSettings[4] SpinUp= 0 PortSettings[4] SolidStateDrive= 0 PortSettings[4] DevSlp= 0 PortSettings[4] EnableDitoConfig= 0 PortSettings[4] DmVal= F PortSettings[4] DitoVal= 271 PortSettings[4] ZpOdd= 0 PortSettings[4] HsioRxGen1EqBoostMagEnable= 0 PortSettings[4] HsioRxGen1EqBoostMag= 0 PortSettings[4] HsioRxGen2EqBoostMagEnable= 0 PortSettings[4] HsioRxGen2EqBoostMag= 0 PortSettings[4] HsioRxGen3EqBoostMagEnable= 0 PortSettings[4] HsioRxGen3EqBoostMag= 0 PortSettings[4] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[4] HsioTxGen1DownscaleAmp= 0 PortSettings[4] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[4] HsioTxGen2DownscaleAmp= 0 PortSettings[4] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[4] HsioTxGen3DownscaleAmp= 0 PortSettings[4] HsioTxGen1DeEmphEnable= 0 PortSettings[4] HsioTxGen1DeEmph= 0 PortSettings[4] HsioTxGen2DeEmphEnable= 0 PortSettings[4] HsioTxGen2DeEmph= 0 PortSettings[4] HsioTxGen3DeEmphEnable= 0 PortSettings[4] HsioTxGen3DeEmph= 0 PortSettings[5] Enabled= 1 PortSettings[5] HotPlug= 1 PortSettings[5] InterlockSw= 0 PortSettings[5] External= 0 PortSettings[5] SpinUp= 0 PortSettings[5] SolidStateDrive= 0 PortSettings[5] DevSlp= 0 PortSettings[5] EnableDitoConfig= 0 PortSettings[5] DmVal= F PortSettings[5] DitoVal= 271 PortSettings[5] ZpOdd= 0 PortSettings[5] HsioRxGen1EqBoostMagEnable= 0 PortSettings[5] HsioRxGen1EqBoostMag= 0 PortSettings[5] HsioRxGen2EqBoostMagEnable= 0 PortSettings[5] HsioRxGen2EqBoostMag= 0 PortSettings[5] HsioRxGen3EqBoostMagEnable= 0 PortSettings[5] HsioRxGen3EqBoostMag= 0 PortSettings[5] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[5] HsioTxGen1DownscaleAmp= 0 PortSettings[5] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[5] HsioTxGen2DownscaleAmp= 0 PortSettings[5] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[5] HsioTxGen3DownscaleAmp= 0 PortSettings[5] HsioTxGen1DeEmphEnable= 0 PortSettings[5] HsioTxGen1DeEmph= 0 PortSettings[5] HsioTxGen2DeEmphEnable= 0 PortSettings[5] HsioTxGen2DeEmph= 0 PortSettings[5] HsioTxGen3DeEmphEnable= 0 PortSettings[5] HsioTxGen3DeEmph= 0 PortSettings[6] Enabled= 0 PortSettings[6] HotPlug= 1 PortSettings[6] InterlockSw= 0 PortSettings[6] External= 0 PortSettings[6] SpinUp= 0 PortSettings[6] SolidStateDrive= 0 PortSettings[6] DevSlp= 0 PortSettings[6] EnableDitoConfig= 0 PortSettings[6] DmVal= F PortSettings[6] DitoVal= 271 PortSettings[6] ZpOdd= 0 PortSettings[6] HsioRxGen1EqBoostMagEnable= 0 PortSettings[6] HsioRxGen1EqBoostMag= 0 PortSettings[6] HsioRxGen2EqBoostMagEnable= 0 PortSettings[6] HsioRxGen2EqBoostMag= 0 PortSettings[6] HsioRxGen3EqBoostMagEnable= 0 PortSettings[6] HsioRxGen3EqBoostMag= 0 PortSettings[6] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[6] HsioTxGen1DownscaleAmp= 0 PortSettings[6] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[6] HsioTxGen2DownscaleAmp= 0 PortSettings[6] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[6] HsioTxGen3DownscaleAmp= 0 PortSettings[6] HsioTxGen1DeEmphEnable= 0 PortSettings[6] HsioTxGen1DeEmph= 0 PortSettings[6] HsioTxGen2DeEmphEnable= 0 PortSettings[6] HsioTxGen2DeEmph= 0 PortSettings[6] HsioTxGen3DeEmphEnable= 0 PortSettings[6] HsioTxGen3DeEmph= 0 PortSettings[7] Enabled= 0 PortSettings[7] HotPlug= 1 PortSettings[7] InterlockSw= 0 PortSettings[7] External= 0 PortSettings[7] SpinUp= 0 PortSettings[7] SolidStateDrive= 0 PortSettings[7] DevSlp= 0 PortSettings[7] EnableDitoConfig= 0 PortSettings[7] DmVal= F PortSettings[7] DitoVal= 271 PortSettings[7] ZpOdd= 0 PortSettings[7] HsioRxGen1EqBoostMagEnable= 0 PortSettings[7] HsioRxGen1EqBoostMag= 0 PortSettings[7] HsioRxGen2EqBoostMagEnable= 0 PortSettings[7] HsioRxGen2EqBoostMag= 0 PortSettings[7] HsioRxGen3EqBoostMagEnable= 0 PortSettings[7] HsioRxGen3EqBoostMag= 0 PortSettings[7] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[7] HsioTxGen1DownscaleAmp= 0 PortSettings[7] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[7] HsioTxGen2DownscaleAmp= 0 PortSettings[7] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[7] HsioTxGen3DownscaleAmp= 0 PortSettings[7] HsioTxGen1DeEmphEnable= 0 PortSettings[7] HsioTxGen1DeEmph= 0 PortSettings[7] HsioTxGen2DeEmphEnable= 0 PortSettings[7] HsioTxGen2DeEmph= 0 PortSettings[7] HsioTxGen3DeEmphEnable= 0 PortSettings[7] HsioTxGen3DeEmph= 0 RaidAlternateId= 0 Raid0= 1 Raid1= 1 Raid10= 1 Raid5= 1 Irrt= 1 OromUiBanner= 1 OromUiDelay= 0 HddUnlock= 0 LedLocate= 0 IrrtOnly= 1 SmartStorage= 1 SpeedSupport= 3 eSATASpeedLimit= 0 TestMode= 0 SalpSupport= 0 RstPcieStorageRemap[0].Enable = 0 RstPcieStorageRemap[0].RstPcieStoragePort = 0 RstPcieStorageRemap[0].DeviceResetDelay = 64 RstPcieStorageRemap[0].RstPcieStorageTestMode = 0 RstPcieStorageRemap[0].RstPcieStoragePortConfigCheck = 0 RstPcieStorageRemap[0].RstPcieStorageDeviceInterface = 0 RstPcieStorageRemap[0].RstPcieStorageDeviceBarSizeCheck = 0 RstPcieStorageRemap[0].RstPcieStorageDeviceBarSelect = 0 RstPcieStorageRemap[0].RstPcieStorageDeviceInterrupt = 0 RstPcieStorageRemap[0].RstPcieStorageAspmProgramming = 0 RstPcieStorageRemap[0].RstPcieStorageSaveRestore = 0 RstPcieStorageRemap[1].Enable = 0 RstPcieStorageRemap[1].RstPcieStoragePort = 0 RstPcieStorageRemap[1].DeviceResetDelay = 64 RstPcieStorageRemap[1].RstPcieStorageTestMode = 0 RstPcieStorageRemap[1].RstPcieStoragePortConfigCheck = 0 RstPcieStorageRemap[1].RstPcieStorageDeviceInterface = 0 RstPcieStorageRemap[1].RstPcieStorageDeviceBarSizeCheck = 0 RstPcieStorageRemap[1].RstPcieStorageDeviceBarSelect = 0 RstPcieStorageRemap[1].RstPcieStorageDeviceInterrupt = 0 RstPcieStorageRemap[1].RstPcieStorageAspmProgramming = 0 RstPcieStorageRemap[1].RstPcieStorageSaveRestore = 0 RstPcieStorageRemap[2].Enable = 0 RstPcieStorageRemap[2].RstPcieStoragePort = 0 RstPcieStorageRemap[2].DeviceResetDelay = 64 RstPcieStorageRemap[2].RstPcieStorageTestMode = 0 RstPcieStorageRemap[2].RstPcieStoragePortConfigCheck = 0 RstPcieStorageRemap[2].RstPcieStorageDeviceInterface = 0 RstPcieStorageRemap[2].RstPcieStorageDeviceBarSizeCheck = 0 RstPcieStorageRemap[2].RstPcieStorageDeviceBarSelect = 0 RstPcieStorageRemap[2].RstPcieStorageDeviceInterrupt = 0 RstPcieStorageRemap[2].RstPcieStorageAspmProgramming = 0 RstPcieStorageRemap[2].RstPcieStorageSaveRestore = 0 LtrEnable= 0 LtrConfigLock= 0 LtrOverride= 0 SnoopLatencyOverrideMultiplier= 2 SataAssel= 0 RstPcieStorageRemapSataMsix= 0 SnoopLatencyOverrideValue= A ------------------ PCH USB Config ------------------ UsbPrecondition= 0 DisableComplianceMode= 0 PortUsb20[0].Enabled= 1 PortUsb20[0].OverCurrentPin= OC8 PortUsb20[0].Afe.Petxiset= 4 PortUsb20[0].Afe.Txiset= 0 PortUsb20[0].Afe.Predeemp= 3 PortUsb20[0].Afe.Pehalfbit= 0 PortUsb20[1].Enabled= 1 PortUsb20[1].OverCurrentPin= OC8 PortUsb20[1].Afe.Petxiset= 4 PortUsb20[1].Afe.Txiset= 0 PortUsb20[1].Afe.Predeemp= 3 PortUsb20[1].Afe.Pehalfbit= 0 PortUsb20[2].Enabled= 1 PortUsb20[2].OverCurrentPin= OC8 PortUsb20[2].Afe.Petxiset= 4 PortUsb20[2].Afe.Txiset= 0 PortUsb20[2].Afe.Predeemp= 3 PortUsb20[2].Afe.Pehalfbit= 0 PortUsb20[3].Enabled= 1 PortUsb20[3].OverCurrentPin= OC8 PortUsb20[3].Afe.Petxiset= 4 PortUsb20[3].Afe.Txiset= 0 PortUsb20[3].Afe.Predeemp= 3 PortUsb20[3].Afe.Pehalfbit= 0 PortUsb30[0] Enabled= 0 PortUsb30[0].OverCurrentPin= OC8 PortUsb30[0].HsioTxDeEmph = 0 PortUsb30[0].HsioTxDeEmphEnable = 0 PortUsb30[0].HsioTxDownscaleAmp = 0 PortUsb30[0].HsioTxDownscaleAmpEnable = 0 PortUsb30[1] Enabled= 0 PortUsb30[1].OverCurrentPin= OC8 PortUsb30[1].HsioTxDeEmph = 0 PortUsb30[1].HsioTxDeEmphEnable = 0 PortUsb30[1].HsioTxDownscaleAmp = 0 PortUsb30[1].HsioTxDownscaleAmpEnable = 0 PortUsb30[2] Enabled= 1 PortUsb30[2].OverCurrentPin= OC8 PortUsb30[2].HsioTxDeEmph = 0 PortUsb30[2].HsioTxDeEmphEnable = 0 PortUsb30[2].HsioTxDownscaleAmp = 0 PortUsb30[2].HsioTxDownscaleAmpEnable = 0 PortUsb30[3] Enabled= 1 PortUsb30[3].OverCurrentPin= OC8 PortUsb30[3].HsioTxDeEmph = 0 PortUsb30[3].HsioTxDeEmphEnable = 0 PortUsb30[3].HsioTxDownscaleAmp = 0 PortUsb30[3].HsioTxDownscaleAmpEnable = 0 XhciEnabled = 0 XhciSsicHalt = 0 EPTypeLockPolicy = 0x00000000 EPTypeLockPolicyPortControl1 = 0x00000000 EPTypeLockPolicyPortControl2 = 0x00000000 TstMnuUnlockUsbForNoa= 0 ------------------ PCH IOAPIC Config ------------------ BdfValid= 1 BusNumber= F0 DeviceNumber= 1F FunctionNumber= 0 IoApicId= 2 ApicRangeSelect= 0 IoApicEntry24_119= 0 ------------------ PCH HPET Config ------------------ Enable 1 BdfValid 0 BusNumber 0 DeviceNumber 0 FunctionNumber 0 Base FED00000 ------------------ PCH SMBUS Config ------------------ Enable= 1 ArpEnable= 0 DynamicPowerGating= 0 SmbusIoBase= EFA0 NumRsvdSmbusAddresses= 4 RsvdSmbusAddressTable= { A2h A0h A2h A0h } ------------------ PCH Lock Down Config ------------------ GlobalSmi= 1 BiosInterface= 1 RtcLock= 1 BiosLock= 1 SpiEiss= 1 ------------------ PCH PM Config ------------------ PowerResetStatusClear MeWakeSts = 0 PowerResetStatusClear MeHrstColdSts = 0 PowerResetStatusClear MeHrstWarmSts = 0 PowerResetStatusClear MeHostPowerDn = 0 PowerResetStatusClear WolOvrWkSts = 0 WakeConfig PmeB0S5Dis = 0 WakeConfig WolEnableOverride = 0 WakeConfig LanWakeFromDeepSx = 0 WakeConfig PcieWakeFromDeepSx = 0 WakeConfig WoWlanEnable = 0 WakeConfig WoWlanDeepSxEnable = 0 PchDeepSxPol = 0 PchSlpS3MinAssert = 0 PchSlpS4MinAssert = 0 PchSlpSusMinAssert = 0 PchSlpAMinAssert = 0 PciClockRun = 0 SlpStrchSusUp = 0 SlpLanLowDc = 0 PwrBtnOverridePeriod = 0 DisableEnergyReport = 0 DisableDsxAcPresentPulldown = 0 PmcReadDisable = 1 PchPwrCycDur = 0 PciePllSsc = 0 CapsuleResetType = 0 PchPmRegisterLock = 0 SlpS0CsMePgQDis = 0 SlpS0GbeDiscQDis = 0 SlpS0ADspD3QDis = 0 SlpS0XhciD3QDis = 0 SlpS0LpioD3QDis = 0 SlpS0IccPllWBEn = 0 SlpS0PUGBEn = 0 ------------------ PCH LPC SIRQ Config ------------------ SirqEnable= 1 SirqMode= 0 StartFramePulse= 0 ------------------ PCH Interrupt Config ------------------ Interrupt assignment: Dxx:Fx INTx IRQ D31:F4 1 023 D31:F7 1 023 D28:F0 1 016 D27:F0 1 016 D27:F1 2 017 D27:F3 3 018 D27:F4 4 019 D26:F2 3 018 D26:F1 2 017 D26:F0 1 016 D24:F0 1 016 D24:F1 2 017 D24:F3 3 018 D24:F4 4 019 D23:F0 1 017 D22:F0 1 016 D21:F0 1 019 D20:F0 1 021 D19:F0 1 020 D18:F0 1 016 D17:F0 4 023 D16:F0 3 022 D15:F0 2 021 D14:F0 1 020 D12:F0 4 019 D11:F0 3 018 D10:F0 2 017 D09:F0 1 016 D06:F0 1 018 D05:F0 1 023 Legacy PIC interrupt routing: PIRQx IRQx PIRQA -> IRQ11 PIRQB -> IRQ10 PIRQC -> IRQ6 PIRQD -> IRQ7 PIRQE -> IRQ12 PIRQF -> IRQ14 PIRQG -> IRQ15 PIRQH -> IRQ15 Other interrupt configuration: GpioIrqRoute= 14 SciIrqSelect= 9 TcoIrqEnable= 0 TcoIrqSelect= 9 ------------------ PCH HSUART Config ---------------- HsUartMode[0]= 0 HsUartMode[1]= 0 HsUartMode[2]= 0 ------------------ PCH TraceHub Config ------------------ TraceHubEnable = 1 TraceHubFwEnable = 1 TraceHubFwDestination = 1 TraceHubPtiMode = 2 TraceHubPtiTraining = 0 TraceHubPtiSpeed = 0 TraceHubMemBaseRegion0 = 0 TraceHubMemBaseRegion1 = 0 EnableMode= 0 MemReg0Size= 100000 MemReg1Size= 100000 ------------------ PCH Flash Protection Config ------------------ WriteProtectionEnable[0]= 1 ReadProtectionEnable[0]= 0 ProtectedRangeLimit[0]= 0 ProtectedRangeBase[0]= 0 WriteProtectionEnable[1]= 1 ReadProtectionEnable[1]= 0 ProtectedRangeLimit[1]= 0 ProtectedRangeBase[1]= 0 WriteProtectionEnable[2]= 1 ReadProtectionEnable[2]= 0 ProtectedRangeLimit[2]= 0 ProtectedRangeBase[2]= 0 WriteProtectionEnable[3]= 1 ReadProtectionEnable[3]= 0 ProtectedRangeLimit[3]= 0 ProtectedRangeBase[3]= 0 WriteProtectionEnable[4]= 1 ReadProtectionEnable[4]= 0 ProtectedRangeLimit[4]= 0 ProtectedRangeBase[4]= 0 ------------------ PCH WDT Config ------------------ DisableAndLock= 1 ------------------ PCH P2SB Config ------------------ SbiUnlock= 0 PsfUnlock= 0 ------------------ PCH DCI Config ------------------ DciEn= 0 DciAutoDetect= 1 ------------------ PCH LPC Config ------------------ EnhancePort8xhDecoding= 1 ------------------ PCH SPI Config ------------------ ShowSpiController= 0 ------------------------ PCH Print Platform Protocol End -------------------------- Install PPI: DFE2B897-0E8E-4926-BC69-E5EDD3F938E1 PCH PEI Policy Initialization Done in Pre-Memory TotalBlockCount = 0x5 TotalPolicySize after adding Block[0x0]= 0x68 TotalPolicySize after adding Block[0x1]= 0x84 TotalPolicySize after adding Block[0x2]= 0xA34 TotalPolicySize after adding Block[0x3]= 0xA48 TotalPolicySize after adding Block[0x4]= 0xA60 TotalPolicySize Final = 0xA60 SaInitPolicy= 0xFEF62CB8 Inside case EnumPlatformConfigId Exiting case EnumPlatformConfigId Addnew config block for SaIpBlocks[BlockCount].BlockId = 0x0 Inside case EnumVtdConfigId Vtd->BlockId = 0x3 Vtd->BlockSize = 0x1C Vtd 0x1C and remapping 0x0 Exiting case EnumVtdConfigId Addnew config block for SaIpBlocks[BlockCount].BlockId = 0x3 Exiting case EnumMemConfigId Addnew config block for SaIpBlocks[BlockCount].BlockId = 0x1 Exiting case EnumNvMemConfigId Addnew config block for SaIpBlocks[BlockCount].BlockId = 0x2 Exiting case EnumSaRestrictedConfigId Addnew config block for SaIpBlocks[BlockCount].BlockId = 0x4 SiSaPolicyPpi->Header.BlockCount = 0x5 UpdatePeiSaPolicy() vtd 1 and remapping 1 Install PPI: F5621AF5-F70B-4360-84F3-C2CF5143CDB8 SA Data HOB installed SystemAgent PEI Platform Policy Initialization Done Pcie IP Policy ready!! Install PPI: BB159A68-8300-43EF-A2A7-F2ADE6C964A6 PCIE IP PEI Policy Initialization Done IQAT IP Policy ready!! Install PPI: AC6BD8E9-0B89-45B1-AE09-A2C017334B6A IQAT IP PEI Policy Initialization Done FspInitPreMemEntryPoint() - End Loading PEIM at 0x000FFF577AC EntryPoint=0x000FFF5787C SiInitPrePolicy : Entry Install PPI: 75AFD0B3-1F2F-4871-AFF2-7AA48AF259D8 PchInitPrePolicy : Entry PCH Series : SKL PCH-H PCH Revision ID: 0x11 PCH Stepping : B1 PCH SKU : (WDT) Readback = 0x00002000 (WDT) Status OK. Install PPI: F38D1338-AF7A-4FB6-91DB-1A9C2183570D Install PPI: 17865DC0-0B8B-4DA8-8B42-7C46B85CCA4D InstallPchReset() Start Install PPI: 433E0F9F-05AE-410A-A0C3-BF298ECB25AC InstallPchReset() End InstallPchSpi() Start Flash Region read Permission : CB Flash Region write Permission : 4A Component 0 SFDP VSCC value : B1D82084 Component 1 SFDP VSCC value : 2000 Component Number : 1 Total Flash Size : 1000000 PchStrapBaseAddr : 100 PchStrapSize : FC CpuStrapBaseAddr : 300 CpuStrapSize : 4 Install PPI: FBF26154-4E55-4BDC-AF7B-D918AC443F61 SPI PPI Installed InstallPchSpi() End PchInitPreMem : Entry PCH PWRM Base needs to be programmed before here PCH Revision ID: 0x11 PCH Revision ID: 0x11 PchEarlyInit : Entry PRSTS = 0xFED03010 Value = 0x10100900 ETR3 = 0xE00FA0AC Value = 0x00000000 ConfigureLpcOnEarlyPei() PchEarlyInit : Exit PchInitPreMem : Exit PchInitPrePolicy : Exit Register PPI Notify: AEBFFA01-7EDC-49FF-8D88-CB848C5E8670 Notify: PPI Guid: AEBFFA01-7EDC-49FF-8D88-CB848C5E8670, Peim notify entry point: FFF578AC SiInitPreMemOnPolicy : Entry PmcStPgInit : Entry ST_PG_FDIS_PMC_1 = 0x00000014 PmcStPgInit : Exit PchOnPolicyInstalled : Entry (Wdt) IsWdtEnabled - no xHCI: Usb2AfeProgramming Start PCH Revision ID: 0x11 PchSbiExecution: Be careful that the address is not DWORD alignment. PchSbiExecution: Be careful that the address is not DWORD alignment. PchSbiExecution: Be careful that the address is not DWORD alignment. PchSbiExecution: Be careful that the address is not DWORD alignment. PchSbiExecution: Be careful that the address is not DWORD alignment. PchSbiExecution: Be careful that the address is not DWORD alignment. PchSbiExecution: Be careful that the address is not DWORD alignment. PchSbiExecution: Be careful that the address is not DWORD alignment. PchSbiExecution: Be careful that the address is not DWORD alignment. PchSbiExecution: Be careful that the address is not DWORD alignment. PchSbiExecution: Be careful that the address is not DWORD alignment. PchSbiExecution: Be careful that the address is not DWORD alignment. PCH Revision ID: 0x11 MePolicyPpi not located! Error: Not Found (Hsio) ChipsetInitHob not found [HECI] Send msg: 80040007 000001F2 [HECI] Got msg: 80080007 000081F2 ... (Hsio) Creating HOB to adjust Hsio settings in PchInit, if required (Hsio) ME Reported CRC=0x12FD (Hsio) BIOS Hsio CRC=0x12FD PchHsioBiosProg() Start PostCode <> FIA LOS1 = 22220000 FIA LOS2 = 22220000 FIA LOS3 = 00001121 PCH Revision ID: 0x11 Was detected stepping 3 POSTCODE << C5 >> LaneNum unsupported LaneNum unsupported LaneNum unsupported LaneNum unsupported LaneNum unsupported LaneNum unsupported LaneNum unsupported LaneNum unsupported LaneNum unsupported LaneNum unsupported LaneNum unsupported LaneNum unsupported LaneNum unsupported LaneNum unsupported LaneNum unsupported POSTCODE << C6 >> PchHsioBiosProg() End PostCode <> PchDciConfiguration : Entry ECTRL = 0x00000000 PchDciConfiguration : Exit TraceHubManagePowerGateControl() Hide config space of Trace Hub device TraceHubManagePowerGateControl() Disable config space of Trace Hub ACPI device TraceHubManagePowerGateControl() Power gating Trace Hub device ConfigurePchHSata() Start SataDeviceNumber: 0x13 DisablePchHSataController: DisablePchHSataController() Started Sata Controller Device Number: 0x13 DisablePchHSataController: DisablePchHSataController() Ended ConfigurePchSataAhci() Start SataDeviceNumber: 13 SATA: LPM disable SATA: SALP disable ConfigurePchSataAhci() End ConfigurePchHSata() End ConfigurePchHSata() Start SataDeviceNumber: 0x14 Setting PMC message to enable controller 0x14 ConfigurePchSataAhci() Start SataDeviceNumber: 14 SATA: LPM disable SATA: SALP disable ConfigurePchSataAhci() End ConfigurePchHSata() End InitializePchSmbus() Start Install PPI: 9CA93627-B65B-4324-A202-C0B461764543 InitializePchSmbus() End PchProgramSvidSid : Entry PchProgramSvidSid : Exit PCH Revision ID: 0x11 ConfigureXhciPreMem : Entry XHCI is present USB2PDO = 0xFE6084F8 Value = 0x00000000 USB3PDO = 0xFE6084FC Value = 0x00000003 PCH Revision ID: 0x11 Before XhciHcInit() POSTCODE << C7 >> Xhci Mmio Base = 0xFE600000 Xhci Mmio Base + 0x0000 (Register 0x0000 to 0x001F) = Xhci Mmio Base + 0x0080 (Register 0x0080 to 0x00BF) = Xhci Mmio Base + 0x0480 (Register 0x0480 to 0x05CF) = Xhci Mmio Base + 0x8000 (Register 0x8000 to 0x833F) = Max number of Super Speed Ports = 4 Max number of High Speed Ports = 4 PCH Revision ID: 0x11 PCH Revision ID: 0x11 XHCC1 = 0xE00A8040 Value = 0x003401FD XHCC2 = 0xE00A8044 Value = 0x03CFC68F PCE_REG = 0xE00A80A2 Value = 0x00000002 XHCLKGTEN = 0xE00A8050 Value = 0x07CE6E5B PMCTRL = 0xFE6080A4 Value = 0x49AC509C PM_CS = 0xE00A8074 Value = 0x00000008 PCH Revision ID: 0x11 PCH Revision ID: 0x11 HOST_CTRL_MISC_REG2 = 0xFE6080B4 Value = 0x00000000 PCH Revision ID: 0x11 PCH Revision ID: 0x11 PGCBCTRL_REG = 0xFE6080A8 Value = 0x0D315555 PCH Revision ID: 0x11 PCH Revision ID: 0x11 AUX_CTRL_REG1 = 0xFE6080E0 Value = 0x808CBCE0 XHCI_AUX_CCR = 0xFE60816C Value = 0x0003401C HOST_CTRL_BW_MAX_REG = 0xFE608128 Value = 0x05647F42 USB_LPM_PARAM = 0xFE608170 Value = 0x0C890032 SSPE_REG = 0xFE6080B8 Value = 0x4000000C PchUsbCommon XHCI Capability Pointer = 0xFE608000 POSTCODE << C8 >> XhciOverCurrentMapping : Entry U3OCM1 = 0xE00A80D0 Value = 0x00000000 U2OCM1 = 0xE00A80B0 Value = 0x00000000 XhciOverCurrentMapping : Exit ConfigureXhciPreMem : Exit ConfigureLpcOnPolicy() PchOnPolicyInstalled : Exit SiInitPreMemOnPolicy : Exit SiInitPrePolicy : Exit Loading PEIM at 0x000FFF669A4 EntryPoint=0x000FFF66A74 ME UMA: ME UMA PPI Driver EntryPoint Install PPI: 8C376010-2400-4D7D-B47B-9D851DF3C9D1 ME UMA: ME UMA PPI Installation status Success Loading PEIM at 0x000FFF6A5EC EntryPoint=0x000FFF6A6C4 [ME Policy] SSC set as auto, checking board id... [ME Policy] SSC enabled. Install PPI: 9F685891-4E6F-445C-BB9E-E57A28FA53A0 [ME Policy] ME PEI Platform Policy PPI Installed Loading PEIM at 0x000FFF6D1E0 EntryPoint=0x000FFF6D2C0 [SPS] SpsPeiEntryPoint called. [SPS] Pre-DID reset is disabled [SPS] Non S3 boot path Register PPI Notify: 12AA57CB-E6F0-40A3-BDF4-B0690C9CCF06 Loading PEIM at 0x000FFF7262C EntryPoint=0x000FFF726FC Install PPI: C884CCCD-2760-400E-AA9D-6D1A9241D539 Platform Policy read successfully UMA: ME UMA size set to 0. Isoc is Disabled. SMBus Legacy: SPD Write Disable bit is locked now! SMBus Host: SPD Write Disable bit is locked now! MRC VERSION: 0x95043C MRCDATA Size: 115DE MRC_SAVE_RESTORE Size: 6F2C SocStepping: 16 Warning: MspData data structure hasn't been locked yet Dunit Fuse Configuration SCRAMBLER_SUPPORTED: 1 DDR_MAX_FREQ_LIMIT: 2 DDR_CURRENT_FREQ: 2 SINGLE_CHANNEL: 0 IPROCTRIM: 2 TIMING_1N_SUPPORTED: 1 X4_SUPPORTED: 1 X8_SUPPORTED: 1 DDR4_SUPPORTED: 1 DDR3_SUPPORTED: 1 DOUBLE_RANK_SUPPORTED: 1 POPULATE_2DPC_SUPPORTED: 1 ECC_SUPPORTED: 1 MAX_DEN_SUPPORTED: 3 MAX_MEM_SUPPORTED: 7 Warning: MspData data structure hasn't been locked yet Dunit Fuse Configuration SCRAMBLER_SUPPORTED: 1 DDR_MAX_FREQ_LIMIT: 2 DDR_CURRENT_FREQ: 2 SINGLE_CHANNEL: 0 IPROCTRIM: 2 TIMING_1N_SUPPORTED: 1 X4_SUPPORTED: 1 X8_SUPPORTED: 1 DDR4_SUPPORTED: 1 DDR3_SUPPORTED: 1 DOUBLE_RANK_SUPPORTED: 1 POPULATE_2DPC_SUPPORTED: 1 ECC_SUPPORTED: 1 MAX_DEN_SUPPORTED: 3 MAX_MEM_SUPPORTED: 7 DDR4 dimm detected C0.D0: SPD byte 1 = 0x10 C0.D0: SPD byte 2 = 0xC C0.D0: SPD byte 3 = 0x9 C0.D0: SPD byte 4 = 0x84 C0.D0: SPD byte 5 = 0x19 C0.D0: SPD byte 6 = 0x0 C0.D0: SPD byte 7 = 0x8 C0.D0: SPD byte 8 = 0x0 C0.D0: SPD byte 9 = 0x60 C0.D0: SPD byte 11 = 0x3 C0.D0: SPD byte 12 = 0x9 C0.D0: SPD byte 13 = 0xB C0.D0: SPD byte 14 = 0x80 C0.D0: SPD byte 17 = 0x0 C0.D0: SPD byte 18 = 0x7 C0.D0: SPD byte 19 = 0xC C0.D0: SPD byte 20 = 0xF8 C0.D0: SPD byte 21 = 0xF C0.D0: SPD byte 22 = 0x0 C0.D0: SPD byte 23 = 0x0 C0.D0: SPD byte 24 = 0x6E C0.D0: SPD byte 25 = 0x6E C0.D0: SPD byte 26 = 0x6E C0.D0: SPD byte 27 = 0x11 C0.D0: SPD byte 28 = 0x0 C0.D0: SPD byte 29 = 0x6E C0.D0: SPD byte 30 = 0x20 C0.D0: SPD byte 31 = 0x8 C0.D0: SPD byte 36 = 0x0 C0.D0: SPD byte 37 = 0xA8 C0.D0: SPD byte 38 = 0x1B C0.D0: SPD byte 39 = 0x28 C0.D0: SPD byte 40 = 0x28 C0.D0: SPD byte 117 = 0x0 C0.D0: SPD byte 120 = 0x0 C0.D0: SPD byte 121 = 0x0 C0.D0: SPD byte 122 = 0x0 C0.D0: SPD byte 123 = 0x0 C0.D0: SPD byte 124 = 0xE7 C0.D0: SPD byte 125 = 0xD6 C0.D0: SPD byte 131 = 0x1 C0.D0: SPD byte 133 = 0x0 C0.D0: SPD byte 134 = 0x0 C0.D0: SPD byte 135 = 0x0 C0.D0: SPD byte 136 = 0x0 C0.D0: SPD byte 137 = 0x0 C0.D0: SPD byte 138 = 0x0 C0.D0: SPD byte 320 = 0x1 C0.D0: SPD byte 321 = 0x7A C0.D0: SPD byte 322 = 0x10 C0.D0: SPD byte 323 = 0x17 C0.D0: SPD byte 325 = 0x49 C0.D0: SPD byte 326 = 0x51 C0.D0: SPD byte 327 = 0x73 C0.D0: SPD byte 328 = 0x83 C0.D0: SPD byte 329 = 0x37 C0.D0: SPD byte 330 = 0x36 C0.D0: SPD byte 331 = 0x2E C0.D0: SPD byte 332 = 0x43 C0.D0: SPD byte 333 = 0x33 C0.D0: SPD byte 334 = 0x35 C0.D0: SPD byte 335 = 0x35 C0.D0: SPD byte 336 = 0x47 C0.D0: SPD byte 337 = 0x2E C0.D0: SPD byte 338 = 0x44 C0.D0: SPD byte 339 = 0x33 C0.D0: SPD byte 340 = 0x34 C0.D0: SPD byte 341 = 0x30 C0.D0: SPD byte 342 = 0x42 C0.D0: SPD byte 343 = 0x20 C0.D0: SPD byte 344 = 0x20 C0.D0: SPD byte 345 = 0x20 C0.D0: SPD byte 346 = 0x20 C0.D0: SPD byte 347 = 0x20 C0.D0: SPD byte 348 = 0x20 C0.D0: SPD byte 349 = 0x0 C0.D0: SPD byte 350 = 0x80 C0.D0: SPD byte 351 = 0xCE C0.D0: SPD byte 352 = 0x0 C0.D0: SPD byte 382 = 0x0 C0.D0: SPD byte 383 = 0x0 DDR Common Frequency - DIMM capability: 6 Setup DDR Frequency - minimum of setup and cap: 5 Warning: MspData data structure hasn't been locked yet MrcFlowStatus = 0x00000000 SpdResetStatus (Fuse) = 0x00000000 SPD_RESET_PCODE (Soft Strap) = 0x00000000 SPD_BIOS_RESET = 0x00000000 SpdSpeedCurrentHw = 0x00000002 DDR Frequency : 2133 VSafe VDDQ_DDR4 Command = 8 Address = 3 Data = BF Polling Busy Bit MEM read to offset=0xFED17084; data=0x00000000 Writing Data register 7080 = BF MEM write to offset=0xFED17080; data=0x000000BF Writing Interface register 7084 = 80000308 MEM write to offset=0xFED17084; data=0x80000308 MEM read to offset=0xFED17084; data=0x00000000 MEM read to offset=0xFED17084; data=0x00000000 SPD_DDR4_MMIDH: 0x007A PPR: 1 S/H: 1 taaminall 13750, tckminall 938, CLdesired 15 CH0 TCL 15 TRAS = 35 TRP = 15 TRCD = 15 TWR = 16 TRFCL = 278 TWTR = 8 TRRDS = 6 TRTP = 8 TFAW = 23 TCCD = 6 DimmConfig = 0x00002226 DimmConfigs = 531 Ch 0, Dimm 0, Rank 0, MaxDq: 9 DevWidth: 8 Ch 0, Dimm 0, Rank 1, MaxDq: 9 DevWidth: 8 Normal Path Ch 0 3N timing Ch 0 TWCL = 14 Ch 0 TWTP = 34 Ch 0 TFAW = 16 Ch 0 TCCD = 6 CmdOffsetValue = 148 CH0 P: 0x40 CH0 F: 0x04 CH0 C: 0x04 CH0 T: 0x02 CH1 P: 0x40 CH1 F: 0x04 CH1 C: 0x04 CH1 T: 0x01 DESTROY_CONTENT_S0: 1:1 DIMM0 Memory Size: 8192MB CH0 R[0]: 1 / 0 (RDIMM) R[1]: 1 / 0 (RDIMM) R[2]: 0 / 0 (RDIMM) R[3]: 0 / 0 (RDIMM) TSegSize: 0x00000002 MmioAllocation: 0x00000800 TOM: 0x00002000 LowMemory: 0x00000800 HighMemory: 0x00002800 Channel 0 state: 1 Channel 1 state: 0 C[0] at 1N Common at 1N C0 TRRD_S: 0 TRRD_L: 2 Channel[0] Self Refresh = 0 Channel[0] using 30us (0x000007CE) Self Refreshed Delay for DDR 2132MHz Channel 0 PMOP Level = 3 LeakRate - 0x0000000000000000 Demand scrub enabled. CH 0 RK2RK: 1 C0 TCCD_RD: 0 TCCD_WR: 0 TCCD_L_RD: 2 TCCD_L_WR: 2 C0 TWTR_L: 4 TRWSR: 7 TRRDR: 4 TWWDR: 4 TRWDR: 4 TWRDR: 4 TRRDD: 4 TWWDD: 4 TRWDD: 4 TWRDD: 4 C0 0 A0DllWorkAroundEnabled:0 Setting MEMHOT THRT Crit/Hi/Med levels to customer defaults... Setting MEMHOT THRT Crit/Hi/Med levels to customer defaults... MEMHOT set to Critical Level... Disabling MEMTRIP because MTM is disabled... Warning: MspData data structure hasn't been locked yet CP B1 CP 02 CP 03 CP 04 CP 05 CP 06 CP 07 CP 08 CP 09 CP 10 CP 11 CP 12 CP 13 CP 1A CP 14 CP 15 CP 16 CP 17 CP 18 CP 19 CP 20 CP 21 CP 22 CP 23 CP 24 CP 25 CP 26 CP 27 CP 28 CP 29 CP 30 CP 31 CP 32 CP 33 CP 34 CP 35 CP 35 CP 56 CmdOverrideSettings elapsedTime: 41988(us) CP 37 EnableChannels Box Port Offset Mask Action Delay Value +DUNIT_COMMON MEM 0xFED11400 0x0000000000000004 SET 0x00000000 0x0000000000000004 +AUNIT_MCHBAR MEM 0xFED165C0 0x00000000000000FF SET 0x00000000 0x0000000000000001 +DUNIT_COMMON MEM 0xFED11400 0x00000000000000FF SET 0x00000000 0x0000000000000005 CP 37 DisableChannel CP 36 CP 39 elapsedTime: 31(us) CP 40 elapsedTime: 298(us) CP D0 GroupSaveRestore Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ------- -- -- -- -- -- --- --- --- - --- --- --- ---- ---- CtlGrp0 00 00 00 00 00 -- 02 00 - 3 - 2 -- 0192 CtlGrp0 00 01 00 00 00 -- 02 00 - 3 - 2 -- 0192 Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ------- -- -- -- -- -- --- --- --- - --- --- --- ---- ---- CtlGrp1 00 00 00 00 00 -- 02 00 - 3 - 2 -- 0192 CtlGrp1 00 01 00 00 00 -- 02 00 - 3 - 2 -- 0192 Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ------- -- -- -- -- -- --- --- --- - --- --- --- ---- ---- CtlGrp2 00 00 00 00 00 -- 02 00 - 3 - 2 -- 0192 CtlGrp2 00 01 00 00 00 -- 02 00 - 3 - 2 -- 0192 Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ------ -- -- -- -- -- --- --- --- - --- --- --- ---- ---- CkAll 00 00 00 00 00 -- 02 00 - 3 - 2 -- 0192 CkAll 00 01 00 00 00 -- 02 00 - 3 - 2 -- 0192 elapsedTime: 396572(us) CP 44 elapsedTime: 11(us) CP 45 elapsedTime: 163(us) CP 46 MmapForTrain Box Port Offset Mask Action Delay Value +DUNIT MEM 0xFED11174 0x00000000FFFFFFFF SET 0x00000000 0x0000000020F08107 +DUNIT MEM 0xFED110B4 0x00000000FFFFFFFF SET 0x00000000 0x000000000000003F +DUNIT MEM 0xFED11148 0x00000000FFFFFFFF SET 0x00000000 0x0000000020F7358B +DUNIT MEM 0xFED1114C 0x00000000FFFFFFFF SET 0x00000000 0x00000000315A4E51 +DUNIT MEM 0xFED11150 0x00000000FFFFFFFF SET 0x00000000 0x000000003FFFFF59 +DUNIT MEM 0xFED11154 0x00000000FFFFFFFF SET 0x00000000 0x00000000065432A9 elapsedTime: 274064(us) CP 47 elapsedTime: 61(us) CP 48 elapsedTime: 4(us) CP 49 ReInitializeFunction ReInitializeFunction DISABLE_CKE Box Port Offset Mask Action Delay Value +DUNIT MEM 0xFED11170 0x000000000000000F SET_DELAY 0x00000064 0x0000000000000000 +DUNIT MEM 0xFED11170 0x0000000000000010 SET_DELAY 0x00000064 0x0000000000000010 RESETDRAMS_COMMON_SET Box Port Offset Mask Action Delay Value +DDRCC1_PHY MEM 0xFD15501C 0x0000000000000001 SET_DELAY 0x00000064 0x0000000000000000 +DDRCC1_PHY MEM 0xFD15501C 0x0000000000000002 SET_DELAY 0x00000064 0x0000000000000002 DELAY: 200us RESETDRAMS_COMMON_CLEAR Box Port Offset Mask Action Delay Value +DDRCC1_PHY MEM 0xFD15501C 0x0000000000000002 SET_DELAY 0x00000064 0x0000000000000000 +DDRCC1_PHY MEM 0xFD15501C 0x0000000000000001 SET_DELAY 0x00000064 0x0000000000000001 +DELAY: 500000ns ENABLE_RELEASE_CKE Box Port Offset Mask Action Delay Value +DUNIT MEM 0xFED11170 0x000000000000001F SET_DELAY 0x00000064 0x000000000000001F +DUNIT MEM 0xFED11170 0x000000000000001F SET_DELAY 0x00001388 0x000000000000000F FORCEODT_OFF Box Port Offset Mask Action Delay Value +DUNIT MEM 0xFED11170 0x0000000000000F00 SET_DELAY 0x00000032 0x0000000000000000 +DUNIT MEM 0xFED11170 0x0000000000001000 SET 0x00000000 0x0000000000001000 RELEASE_CKE Box Port Offset Mask Action Delay Value +DUNIT MEM 0xFED11170 0x000000000000000F SET_DELAY 0x00000064 0x000000000000000F +DUNIT MEM 0xFED11170 0x0000000000000010 SET_DELAY 0x00000064 0x0000000000000000 R0 NOP R1 NOP JedecInit Box Port Offset Mask Action Delay Value +DELAY: 400ns +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x0000000000020038 MR3_R0 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x0000000000089168 MR6.Vref=1 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x0000000000089168 MR6.VrefValue +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x0000000000081168 MR6 Vref = 0 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x0000000000018058 MR5 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x0000000000000048 MR4 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x000000000004E028 MR2 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x00000000000C0318 MR1 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x0000000000073008 MR0 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x0000000004020038 MR3_R1 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x0000000004210998 MR6.Vref=1 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x0000000004210998 MR6.VrefValue +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x0000000004200998 MR6 Vref = 0 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x00000000040180A8 MR5 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x0000000004000088 MR4 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x0000000004056018 MR2 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x0000000004240328 MR1 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x000000000406C808 MR0 R0 PRE_A R1 PRE_A R0 ZqCal Long R1 ZqCal Long FORCEODT_REL Box Port Offset Mask Action Delay Value +DUNIT MEM 0xFED11170 0x0000000000001000 SET_DELAY 0x00000032 0x0000000000000000 +DUNIT MEM 0xFED11170 0x0000000000000F00 SET 0x00000000 0x0000000000000000 CP 50 elapsedTime: 12(us) CP 51 elapsedTime: 54(us) CP 52 CP 53 elapsedTime: 27(us) CP 54 elapsedTime: 8(us) CP 55 CP 56 VocTraining R[0] = 0 R[1] = 255 C = 0 C0RxVocEn = 1 Pull Up = 27 Pull Down = 19 VREF Set RxVoc = 0 SL00:57:61:57:58 SL01:63:59:60:62 SL02:62:59:60:59 SL03:60:61:61:60 SL04:59:60:61:59 SL05:61:64:60:58 SL06:60:60:57:61 SL07:58:59:62:58 SL08:60:60:61:61 SL09:62:66:62:61 SL10:63:60:60:61 SL11:61:61:66:61 SL12:66:60:63:59 SL13:57:58:59:59 SL14:63:60:59:59 SL15:61:55:61:58 SL16:59:58:60:57 SL17:63:63:61:61 Set RxVoc = 1 SL00:59:64:60:61 SL01:65:61:63:64 SL02:65:62:62:62 SL03:62:64:63:63 SL04:62:63:64:62 SL05:63:67:62:61 SL06:63:62:59:63 SL07:61:62:64:61 SL08:63:62:63:64 SL09:64:68:65:64 SL10:66:62:63:64 SL11:64:64:68:64 SL12:68:62:65:62 SL13:60:60:62:62 SL14:65:62:62:61 SL15:64:58:64:61 SL16:61:61:63:60 SL17:65:66:63:64 Set RxVoc = 2 SL00:62:66:63:64 SL01:68:64:66:68 SL02:67:64:65:65 SL03:65:66:66:65 SL04:65:66:67:64 SL05:66:69:65:63 SL06:65:65:62:66 SL07:64:64:67:64 SL08:65:65:66:67 SL09:67:70:67:66 SL10:68:65:66:67 SL11:66:67:71:67 SL12:71:65:69:64 SL13:63:63:64:64 SL14:68:65:65:64 SL15:67:61:67:63 SL16:65:63:66:63 SL17:68:69:66:66 Set RxVoc = 3 SL00:65:69:65:66 SL01:70:67:69:70 SL02:70:67:68:67 SL03:68:69:68:68 SL04:68:68:69:67 SL05:68:72:68:66 SL06:68:67:64:68 SL07:66:67:69:66 SL08:67:68:69:69 SL09:69:73:70:68 SL10:71:68:68:69 SL11:69:70:73:69 SL12:73:67:71:67 SL13:66:66:67:67 SL14:70:68:67:67 SL15:69:64:70:66 SL16:67:67:68:65 SL17:71:72:69:69 Set RxVoc = 4 SL00:68:72:68:70 SL01:74:70:72:73 SL02:73:70:71:70 SL03:71:72:71:72 SL04:71:71:73:70 SL05:71:75:71:69 SL06:72:70:68:71 SL07:70:70:72:70 SL08:71:71:71:72 SL09:72:75:73:71 SL10:73:71:71:73 SL11:72:72:75:71 SL12:75:70:74:70 SL13:69:69:71:70 SL14:73:71:70:69 SL15:72:67:73:69 SL16:71:70:71:68 SL17:74:75:72:72 Set RxVoc = 5 SL00:71:74:71:72 SL01:76:73:75:76 SL02:75:73:74:73 SL03:74:75:74:75 SL04:74:74:75:73 SL05:74:77:73:72 SL06:74:73:71:74 SL07:73:73:75:73 SL08:73:74:74:75 SL09:75:77:75:74 SL10:76:74:75:75 SL11:75:75:78:74 SL12:78:73:76:73 SL13:72:72:74:73 SL14:75:74:73:72 SL15:75:70:75:72 SL16:74:73:74:71 SL17:75:77:74:75 Set RxVoc = 6 SL00:75:77:74:75 SL01:79:76:78:80 SL02:78:76:76:76 SL03:76:77:77:77 SL04:76:76:78:76 SL05:76:80:76:75 SL06:77:76:74:76 SL07:76:76:77:75 SL08:75:77:77:78 SL09:77:80:78:77 SL10:79:77:77:78 SL11:77:77:81:77 SL12:81:75:79:76 SL13:75:75:76:75 SL14:78:76:75:75 SL15:78:74:78:75 SL16:76:76:77:75 SL17:79:80:77:78 Set RxVoc = 7 SL00:77:80:77:77 SL01:82:79:80:82 SL02:81:79:79:79 SL03:79:80:79:80 SL04:79:79:81:78 SL05:79:82:78:77 SL06:80:78:76:79 SL07:79:78:80:78 SL08:78:80:80:81 SL09:80:82:80:79 SL10:82:80:80:81 SL11:80:80:83:80 SL12:84:78:82:79 SL13:78:77:79:78 SL14:81:79:78:77 SL15:80:76:81:78 SL16:79:78:80:77 SL17:82:82:80:80 TargetVref 0=66 1=63 2=66 3=66 4=61 5=64 6=61 7=62 8=63 9=66 10=63 11=66 12=66 13=61 14=64 15=61 16=62 17=63 VREF table VREF55: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:00:--:--: --:--:--:--: --:--:--:--: VREF56: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: VREF57: 00:--:00:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:00:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: 00:--:--:--: --:--:--:--: --:--:--:--: --:--:--:00: --:--:--:--: VREF58: --:--:--:00: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:00: --:--:--:--: 00:--:--:00: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:00:--:--: --:--:--:--: --:01:--:00: --:00:--:--: --:--:--:--: VREF59: 01:--:--:--: --:00:--:--: --:00:--:00: --:--:--:--: 00:--:--:00: --:--:--:--: --:--:01:--: --:00:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:00: --:--:00:00: --:--:00:00: --:--:--:--: 00:--:--:--: --:--:--:--: VREF60: --:--:01:--: --:--:00:--: --:--:00:--: 00:--:--:00: --:00:--:--: --:--:00:--: 00:00:--:--: --:--:--:--: 00:00:--:--: --:--:--:--: --:00:00:--: --:--:--:--: --:00:--:--: 01:01:--:--: --:00:--:--: --:--:--:--: --:--:00:01: --:--:--:--: VREF61: --:00:--:01: --:01:--:--: --:--:--:--: --:00:00:--: --:--:00:--: 00:--:--:01: --:--:--:00: 01:--:--:01: --:--:00:00: --:--:--:00: --:--:--:00: 00:00:--:00: --:--:--:--: --:--:--:--: --:--:--:01: 00:02:00:01: 01:01:--:--: --:--:00:00: VREF62: 02:--:--:--: --:--:--:00: 00:01:01:01: 01:--:--:--: 01:--:--:01: --:--:01:--: --:01:02:--: --:01:00:--: --:01:--:--: 00:--:00:--: --:01:--:--: --:--:--:--: --:01:--:01: --:--:01:01: --:01:01:--: --:--:--:--: --:--:--:--: --:--:--:--: VREF63: --:--:02:--: 00:--:01:--: --:--:--:--: --:--:01:01: --:01:--:--: 01:--:--:02: 01:--:--:01: --:--:--:--: 01:--:01:--: --:--:--:--: 00:--:01:--: --:--:--:--: --:--:00:--: 02:02:--:--: 00:--:--:--: --:--:--:02: --:02:01:02: 00:00:01:--: VREF64: --:01:--:02: --:02:--:01: --:02:--:--: --:01:--:--: --:--:01:02: --:00:--:--: --:--:03:--: 02:02:01:02: --:--:--:01: 01:--:--:01: --:--:--:01: 01:01:--:01: --:--:--:02: --:--:02:02: --:--:--:02: 01:03:01:--: --:--:--:--: --:--:--:01: VREF65: 03:--:03:--: 01:--:--:--: 01:--:02:02: 02:--:--:02: 02:--:--:--: --:--:02:--: 02:02:--:--: --:--:--:--: 02:02:--:--: --:--:01:--: --:02:--:--: --:--:--:--: --:02:01:--: --:--:--:--: 01:02:02:--: --:--:--:--: 02:--:--:03: 01:--:--:--: VREF66: --:02:--:03: --:--:02:--: --:--:--:--: --:02:02:--: --:02:--:--: 02:--:--:03: --:--:--:02: 03:--:--:03: --:--:02:--: --:00:--:02: 01:--:02:--: 02:--:00:--: 00:--:--:--: 03:03:--:--: --:--:--:--: --:--:--:03: --:--:02:--: --:01:02:02: VREF67: --:--:--:--: --:03:--:--: 02:03:--:03: --:--:--:--: --:--:02:03: --:01:--:--: --:03:--:--: --:03:02:--: 03:--:--:02: 02:--:02:--: --:--:--:02: --:02:--:02: --:03:--:03: --:--:03:03: --:--:03:03: 02:04:02:--: 03:03:--:--: --:--:--:--: VREF68: 04:--:04:--: 02:--:--:02: --:--:03:--: 03:--:03:03: 03:03:--:--: 03:--:03:--: 03:--:04:03: --:--:--:--: --:03:--:--: --:01:--:03: 02:03:03:--: --:--:01:--: 01:--:--:--: --:--:--:--: 02:03:--:--: --:--:--:--: --:--:03:04: 02:--:--:--: VREF69: --:03:--:--: --:--:03:--: --:--:--:--: --:03:--:--: --:--:03:--: --:02:--:04: --:--:--:--: --:--:03:--: --:--:03:03: 03:--:--:--: --:--:--:03: 03:--:--:03: --:--:02:--: 04:04:--:--: --:--:--:04: 03:--:--:04: --:--:--:--: --:02:03:03: VREF70: --:--:--:04: 03:04:--:03: 03:04:--:04: --:--:--:--: --:--:--:04: --:--:--:--: --:04:--:--: 04:04:--:04: --:--:--:--: --:02:03:--: --:--:--:--: --:03:--:--: --:04:--:04: --:--:--:04: 03:--:04:--: --:--:03:--: --:04:--:--: --:--:--:--: VREF71: --:--:--:--: --:--:--:--: --:--:04:--: 04:--:04:--: 04:04:--:--: 04:--:04:--: --:--:--:04: --:--:--:--: 04:04:04:--: --:--:--:04: 03:04:04:--: --:--:02:04: 02:--:03:--: --:--:04:--: --:04:--:--: --:--:--:--: 04:--:04:--: 03:--:--:--: VREF72: --:04:--:--: --:--:04:--: --:--:--:--: --:04:--:04: --:--:--:--: --:03:--:--: 04:--:--:--: --:--:04:--: --:--:--:04: 04:--:--:--: --:--:--:--: 04:04:--:--: --:--:--:--: --:--:--:--: --:--:--:--: 04:--:--:--: --:--:--:--: --:03:04:04: VREF73: --:--:--:--: --:--:--:04: 04:--:--:--: --:--:--:--: --:--:04:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:03:04:--: 04:--:--:04: --:--:03:--: 03:--:--:--: --:--:--:--: 04:--:--:--: --:--:04:--: --:--:--:--: --:--:--:--: VREF74: --:--:--:--: 04:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:04:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: 04:--:--:--: VREF75: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:04:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:04:--:--: --:--:--:--: --:--:04:--: 04:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:04:--:--: VREF76: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: VREF77: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: VREF78: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: VREF79: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: VREF80: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: VREF81: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: VREF82: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: VREF83: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: VREF84: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: VOC SL00:03:02:03:03 SL01:00:02:01:01 SL02:02:03:02:03 SL03:02:02:02:02 SL04:01:00:00:01 SL05:01:00:02:02 SL06:00:01:02:00 SL07:01:01:00:01 SL08:01:01:01:01 SL09:02:00:02:02 SL10:00:01:01:01 SL11:02:02:00:02 SL12:00:03:01:03 SL13:01:01:01:01 SL14:01:02:02:02 SL15:00:02:00:01 SL16:01:02:01:02 SL17:00:00:01:01 VREF SL00:65:66:65:66 SL01:63:64:63:65 SL02:67:67:65:67 SL03:65:66:66:66 SL04:62:60:62:62 SL05:63:64:65:63 SL06:60:62:62:61 SL07:61:62:62:61 SL08:63:62:63:64 SL09:67:66:68:66 SL10:63:62:63:64 SL11:66:67:66:66 SL12:65:67:66:67 SL13:60:60:62:62 SL14:65:65:65:64 SL15:61:61:62:61 SL16:61:64:63:62 SL17:63:64:63:64 elapsedTime: 5018255(us) CP 57 START_ReceiveEnable Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ---------- -- -- -- -- -- --- --- --- - --- --- --- ---- ---- RecEnDelay 00 00 00 00 00 12 02 17 - 1 - 2 -- 1745 RecEnDelay 00 00 01 00 00 12 03 37 - 0 - 3 -- 1765 RecEnDelay 00 00 02 00 00 12 02 45 - 0 - 2 -- 1709 RecEnDelay 00 00 03 00 00 12 02 55 - 2 - 2 -- 1783 RecEnDelay 00 00 04 00 00 12 03 54 - 2 - 3 -- 1846 RecEnDelay 00 00 05 00 00 12 05 07 - 3 - 5 -- 1927 RecEnDelay 00 00 06 00 00 12 04 29 - 1 - 4 -- 1885 RecEnDelay 00 00 07 00 00 12 05 42 - 0 - 5 -- 1898 RecEnDelay 00 00 08 00 00 12 03 11 - 3 - 3 -- 1803 RecEnDelay 00 00 09 00 00 12 02 38 - 0 - 2 -- 1702 RecEnDelay 00 00 10 00 00 12 02 38 - 0 - 2 -- 1702 RecEnDelay 00 00 11 00 00 12 02 38 - 0 - 2 -- 1702 RecEnDelay 00 00 12 00 00 12 02 38 - 0 - 2 -- 1702 RecEnDelay 00 00 13 00 00 12 02 39 - 0 - 2 -- 1703 RecEnDelay 00 00 14 00 00 12 02 39 - 0 - 2 -- 1703 RecEnDelay 00 00 15 00 00 12 02 39 - 0 - 2 -- 1703 RecEnDelay 00 00 16 00 00 12 02 39 - 0 - 2 -- 1703 RecEnDelay 00 00 17 00 00 12 02 38 - 0 - 2 -- 1702 RecEnDelay 00 01 00 00 00 12 02 10 - 3 - 2 -- 1738 RecEnDelay 00 01 01 00 00 12 03 36 - 0 - 3 -- 1764 RecEnDelay 00 01 02 00 00 12 02 41 - 0 - 2 -- 1705 RecEnDelay 00 01 03 00 00 12 02 52 - 2 - 2 -- 1780 RecEnDelay 00 01 04 00 00 12 03 52 - 2 - 3 -- 1844 RecEnDelay 00 01 05 00 00 12 05 02 - 3 - 5 -- 1922 RecEnDelay 00 01 06 00 00 12 04 30 - 1 - 4 -- 1886 RecEnDelay 00 01 07 00 00 12 05 36 - 0 - 5 -- 1892 RecEnDelay 00 01 08 00 00 12 03 04 - 3 - 3 -- 1796 RecEnDelay 00 01 09 00 00 12 02 39 - 0 - 2 -- 1703 RecEnDelay 00 01 10 00 00 12 02 39 - 0 - 2 -- 1703 RecEnDelay 00 01 11 00 00 12 02 39 - 0 - 2 -- 1703 RecEnDelay 00 01 12 00 00 12 02 39 - 0 - 2 -- 1703 RecEnDelay 00 01 13 00 00 12 02 38 - 0 - 2 -- 1702 RecEnDelay 00 01 14 00 00 12 02 38 - 0 - 2 -- 1702 RecEnDelay 00 01 15 00 00 12 02 38 - 0 - 2 -- 1702 RecEnDelay 00 01 16 00 00 12 02 38 - 0 - 2 -- 1702 RecEnDelay 00 01 17 00 00 12 02 39 - 0 - 2 -- 1703 S00 S01 S02 S03 S04 S05 S06 S07 S08 R0 209 229 173 247 310 391 349 362 267 R1 202 228 169 244 308 386 350 356 260 elapsedTime: 1220995(us) CP 58 STOP_ReceiveEnable START_EarlyMprRead CH00 RxVref = 000 CH00 RxVref = 002 CH00 RxVref = 004 CH00 RxVref = 006 CH00 RxVref = 008 CH00 RxVref = 010 CH00 RxVref = 012 CH00 RxVref = 014 CH00 RxVref = 016 CH00 RxVref = 018 CH00 RxVref = 020 CH00 RxVref = 022 CH00 RxVref = 024 CH00 RxVref = 026 CH00 RxVref = 028 CH00 RxVref = 030 CH00 RxVref = 032 CH00 RxVref = 034 CH00 RxVref = 036 CH00 RxVref = 038 CH00 RxVref = 040 CH00 RxVref = 042 CH00 RxVref = 044 CH00 RxVref = 046 CH00 RxVref = 048 CH00 RxVref = 050 CH00 RxVref = 052 CH00 RxVref = 054 CH00 RxVref = 056 CH00 RxVref = 058 CH00 RxVref = 060 CH00 RxVref = 062 CH00 RxVref = 064 CH00 RxVref = 066 CH00 RxVref = 068 CH00 RxVref = 070 CH00 RxVref = 072 CH00 RxVref = 074 CH00 RxVref = 076 CH00 RxVref = 078 CH00 RxVref = 080 CH00 RxVref = 082 CH00 RxVref = 084 CH00 RxVref = 086 CH00 RxVref = 088 CH00 RxVref = 090 CH00 RxVref = 092 CH00 RxVref = 094 C0.R0.S0: DQ7, DQ6, DQ5, DQ4, DQ3, DQ2, DQ1, DQ0, Cx: 30 Cy: 73 * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C0.R0.S1: DQ15, DQ14, DQ13, DQ12, DQ11, DQ10, DQ9, DQ8, Cx: 27 Cy: 71 * * * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C0.R0.S2: DQ23, DQ22, DQ21, DQ20, DQ19, DQ18, DQ17, DQ16, Cx: 30 Cy: 72 * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C0.R0.S3: DQ31, DQ30, DQ29, DQ28, DQ27, DQ26, DQ25, DQ24, Cx: 30 Cy: 73 * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C0.R0.S4: DQ39, DQ38, DQ37, DQ36, DQ35, DQ34, DQ33, DQ32, Cx: 31 Cy: 66 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C0.R0.S5: DQ47, DQ46, DQ45, DQ44, DQ43, DQ42, DQ41, DQ40, Cx: 25 Cy: 72 * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C0.R0.S6: DQ55, DQ54, DQ53, DQ52, DQ51, DQ50, DQ49, DQ48, Cx: 29 Cy: 68 * * * * * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C0.R0.S7: DQ63, DQ62, DQ61, DQ60, DQ59, DQ58, DQ57, DQ56, Cx: 29 Cy: 68 * * * * * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C0.R0.S8: DQ71, DQ70, DQ69, DQ68, DQ67, DQ66, DQ65, DQ64, Cx: 30 Cy: 69 * * * * * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ** CH00 RxVref = 000 CH00 RxVref = 002 CH00 RxVref = 004 CH00 RxVref = 006 CH00 RxVref = 008 CH00 RxVref = 010 CH00 RxVref = 012 CH00 RxVref = 014 CH00 RxVref = 016 CH00 RxVref = 018 CH00 RxVref = 020 CH00 RxVref = 022 CH00 RxVref = 024 CH00 RxVref = 026 CH00 RxVref = 028 CH00 RxVref = 030 CH00 RxVref = 032 CH00 RxVref = 034 CH00 RxVref = 036 CH00 RxVref = 038 CH00 RxVref = 040 CH00 RxVref = 042 CH00 RxVref = 044 CH00 RxVref = 046 CH00 RxVref = 048 CH00 RxVref = 050 CH00 RxVref = 052 CH00 RxVref = 054 CH00 RxVref = 056 CH00 RxVref = 058 CH00 RxVref = 060 CH00 RxVref = 062 CH00 RxVref = 064 CH00 RxVref = 066 CH00 RxVref = 068 CH00 RxVref = 070 CH00 RxVref = 072 CH00 RxVref = 074 CH00 RxVref = 076 CH00 RxVref = 078 CH00 RxVref = 080 CH00 RxVref = 082 CH00 RxVref = 084 CH00 RxVref = 086 CH00 RxVref = 088 CH00 RxVref = 090 CH00 RxVref = 092 CH00 RxVref = 094 C0.R1.S0: DQ7, DQ6, DQ5, DQ4, DQ3, DQ2, DQ1, DQ0, Cx: 29 Cy: 70 * * * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C0.R1.S1: DQ15, DQ14, DQ13, DQ12, DQ11, DQ10, DQ9, DQ8, Cx: 28 Cy: 68 * * * * * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C0.R1.S2: DQ23, DQ22, DQ21, DQ20, DQ19, DQ18, DQ17, DQ16, Cx: 30 Cy: 72 * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C0.R1.S3: DQ31, DQ30, DQ29, DQ28, DQ27, DQ26, DQ25, DQ24, Cx: 30 Cy: 71 * * * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C0.R1.S4: DQ39, DQ38, DQ37, DQ36, DQ35, DQ34, DQ33, DQ32, Cx: 33 Cy: 65 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C0.R1.S5: DQ47, DQ46, DQ45, DQ44, DQ43, DQ42, DQ41, DQ40, Cx: 25 Cy: 71 * * * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C0.R1.S6: DQ55, DQ54, DQ53, DQ52, DQ51, DQ50, DQ49, DQ48, Cx: 29 Cy: 68 * * * * * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C0.R1.S7: DQ63, DQ62, DQ61, DQ60, DQ59, DQ58, DQ57, DQ56, Cx: 29 Cy: 68 * * * * * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C0.R1.S8: DQ71, DQ70, DQ69, DQ68, DQ67, DQ66, DQ65, DQ64, Cx: 31 Cy: 70 * * * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ----------- -- -- -- -- -- --- --- --- - --- --- --- ---- ---- RxDqsPDelay 00 00 00 00 00 -- -- 30 - - - - 0070 0030 RxDqsPDelay 00 00 01 00 00 -- -- 27 - - - - 0068 0027 RxDqsPDelay 00 00 02 00 00 -- -- 30 - - - - 0072 0030 RxDqsPDelay 00 00 03 00 00 -- -- 30 - - - - 0071 0030 RxDqsPDelay 00 00 04 00 00 -- -- 31 - - - - 0065 0031 RxDqsPDelay 00 00 05 00 00 -- -- 25 - - - - 0071 0025 RxDqsPDelay 00 00 06 00 00 -- -- 29 - - - - 0068 0029 RxDqsPDelay 00 00 07 00 00 -- -- 29 - - - - 0068 0029 RxDqsPDelay 00 00 08 00 00 -- -- 30 - - - - 0070 0030 RxDqsPDelay 00 00 09 00 00 -- -- 11 - - - - 0070 0011 RxDqsPDelay 00 00 10 00 00 -- -- 11 - - - - 0068 0011 RxDqsPDelay 00 00 11 00 00 -- -- 11 - - - - 0072 0011 RxDqsPDelay 00 00 12 00 00 -- -- 11 - - - - 0071 0011 RxDqsPDelay 00 00 13 00 00 -- -- 12 - - - - 0065 0012 RxDqsPDelay 00 00 14 00 00 -- -- 12 - - - - 0071 0012 RxDqsPDelay 00 00 15 00 00 -- -- 12 - - - - 0068 0012 RxDqsPDelay 00 00 16 00 00 -- -- 12 - - - - 0068 0012 RxDqsPDelay 00 00 17 00 00 -- -- 11 - - - - 0070 0011 RxDqsPDelay 00 01 00 00 00 -- -- 29 - - - - 0070 0029 RxDqsPDelay 00 01 01 00 00 -- -- 28 - - - - 0068 0028 RxDqsPDelay 00 01 02 00 00 -- -- 30 - - - - 0072 0030 RxDqsPDelay 00 01 03 00 00 -- -- 30 - - - - 0071 0030 RxDqsPDelay 00 01 04 00 00 -- -- 33 - - - - 0065 0033 RxDqsPDelay 00 01 05 00 00 -- -- 25 - - - - 0071 0025 RxDqsPDelay 00 01 06 00 00 -- -- 29 - - - - 0068 0029 RxDqsPDelay 00 01 07 00 00 -- -- 29 - - - - 0068 0029 RxDqsPDelay 00 01 08 00 00 -- -- 31 - - - - 0070 0031 RxDqsPDelay 00 01 09 00 00 -- -- 12 - - - - 0070 0012 RxDqsPDelay 00 01 10 00 00 -- -- 12 - - - - 0068 0012 RxDqsPDelay 00 01 11 00 00 -- -- 12 - - - - 0072 0012 RxDqsPDelay 00 01 12 00 00 -- -- 12 - - - - 0071 0012 RxDqsPDelay 00 01 13 00 00 -- -- 11 - - - - 0065 0011 RxDqsPDelay 00 01 14 00 00 -- -- 11 - - - - 0071 0011 RxDqsPDelay 00 01 15 00 00 -- -- 11 - - - - 0068 0011 RxDqsPDelay 00 01 16 00 00 -- -- 11 - - - - 0068 0011 RxDqsPDelay 00 01 17 00 00 -- -- 12 - - - - 0070 0012 Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ----------- -- -- -- -- -- --- --- --- - --- --- --- ---- ---- RxDqsNDelay 00 00 00 00 00 -- -- 30 - - - - 0070 0030 RxDqsNDelay 00 00 01 00 00 -- -- 27 - - - - 0068 0027 RxDqsNDelay 00 00 02 00 00 -- -- 30 - - - - 0072 0030 RxDqsNDelay 00 00 03 00 00 -- -- 30 - - - - 0071 0030 RxDqsNDelay 00 00 04 00 00 -- -- 31 - - - - 0065 0031 RxDqsNDelay 00 00 05 00 00 -- -- 25 - - - - 0071 0025 RxDqsNDelay 00 00 06 00 00 -- -- 29 - - - - 0068 0029 RxDqsNDelay 00 00 07 00 00 -- -- 29 - - - - 0068 0029 RxDqsNDelay 00 00 08 00 00 -- -- 30 - - - - 0070 0030 RxDqsNDelay 00 00 09 00 00 -- -- 11 - - - - 0070 0011 RxDqsNDelay 00 00 10 00 00 -- -- 11 - - - - 0068 0011 RxDqsNDelay 00 00 11 00 00 -- -- 11 - - - - 0072 0011 RxDqsNDelay 00 00 12 00 00 -- -- 11 - - - - 0071 0011 RxDqsNDelay 00 00 13 00 00 -- -- 12 - - - - 0065 0012 RxDqsNDelay 00 00 14 00 00 -- -- 12 - - - - 0071 0012 RxDqsNDelay 00 00 15 00 00 -- -- 12 - - - - 0068 0012 RxDqsNDelay 00 00 16 00 00 -- -- 12 - - - - 0068 0012 RxDqsNDelay 00 00 17 00 00 -- -- 11 - - - - 0070 0011 RxDqsNDelay 00 01 00 00 00 -- -- 29 - - - - 0070 0029 RxDqsNDelay 00 01 01 00 00 -- -- 28 - - - - 0068 0028 RxDqsNDelay 00 01 02 00 00 -- -- 30 - - - - 0072 0030 RxDqsNDelay 00 01 03 00 00 -- -- 30 - - - - 0071 0030 RxDqsNDelay 00 01 04 00 00 -- -- 33 - - - - 0065 0033 RxDqsNDelay 00 01 05 00 00 -- -- 25 - - - - 0071 0025 RxDqsNDelay 00 01 06 00 00 -- -- 29 - - - - 0068 0029 RxDqsNDelay 00 01 07 00 00 -- -- 29 - - - - 0068 0029 RxDqsNDelay 00 01 08 00 00 -- -- 31 - - - - 0070 0031 RxDqsNDelay 00 01 09 00 00 -- -- 12 - - - - 0070 0012 RxDqsNDelay 00 01 10 00 00 -- -- 12 - - - - 0068 0012 RxDqsNDelay 00 01 11 00 00 -- -- 12 - - - - 0072 0012 RxDqsNDelay 00 01 12 00 00 -- -- 12 - - - - 0071 0012 RxDqsNDelay 00 01 13 00 00 -- -- 11 - - - - 0065 0011 RxDqsNDelay 00 01 14 00 00 -- -- 11 - - - - 0071 0011 RxDqsNDelay 00 01 15 00 00 -- -- 11 - - - - 0068 0011 RxDqsNDelay 00 01 16 00 00 -- -- 11 - - - - 0068 0011 RxDqsNDelay 00 01 17 00 00 -- -- 12 - - - - 0070 0012 Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ------------ -- -- -- -- -- --- --- --- - --- --- --- ---- ---- RxDqBitDelay 00 00 00 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 00 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 00 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 00 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 01 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 01 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 01 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 01 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 02 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 02 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 02 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 02 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 03 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 03 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 03 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 03 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 04 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 04 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 04 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 04 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 05 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 05 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 05 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 05 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 06 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 06 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 06 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 06 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 07 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 07 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 07 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 07 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 08 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 08 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 08 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 08 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 09 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 09 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 09 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 09 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 10 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 10 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 10 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 10 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 11 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 11 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 11 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 11 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 12 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 12 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 12 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 12 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 13 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 13 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 13 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 13 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 14 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 14 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 14 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 14 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 15 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 15 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 15 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 15 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 16 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 16 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 16 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 16 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 17 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 17 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 17 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 17 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 00 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 00 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 00 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 00 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 01 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 01 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 01 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 01 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 02 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 02 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 02 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 02 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 03 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 03 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 03 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 03 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 04 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 04 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 04 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 04 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 05 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 05 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 05 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 05 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 06 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 06 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 06 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 06 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 07 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 07 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 07 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 07 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 08 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 08 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 08 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 08 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 09 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 09 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 09 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 09 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 10 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 10 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 10 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 10 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 11 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 11 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 11 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 11 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 12 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 12 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 12 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 12 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 13 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 13 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 13 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 13 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 14 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 14 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 14 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 14 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 15 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 15 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 15 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 15 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 16 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 16 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 16 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 16 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 17 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 17 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 17 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 17 03 00 -- -- 991 - - - - -- 0991 elapsedTime: 22984083(us) CP 57 DnvNibbleTrainingHook CP 59 STOP_EarlyMprRead START_FineWriteLeveling Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ---------- -- -- -- -- -- --- --- --- - --- --- --- ---- ---- TxDqsDelay 00 00 00 00 00 -- 02 59 - 2 - 2 -- 0251 TxDqsDelay 00 00 01 00 00 -- 04 34 - 0 - 4 -- 0290 TxDqsDelay 00 00 02 00 00 -- 04 49 - 2 - 4 -- 0369 TxDqsDelay 00 00 03 00 00 -- 03 58 - 2 - 3 -- 0314 TxDqsDelay 00 00 04 00 00 -- 04 23 - 1 - 4 -- 0343 TxDqsDelay 00 00 05 00 00 -- 03 20 - 1 - 3 -- 0276 TxDqsDelay 00 00 06 00 00 -- 04 26 - 1 - 4 -- 0346 TxDqsDelay 00 00 07 00 00 -- 03 04 - 3 - 3 -- 0260 TxDqsDelay 00 00 08 00 00 -- 04 22 - 1 - 4 -- 0342 TxDqsDelay 00 00 09 00 00 -- 02 59 - 2 - 2 -- 0251 TxDqsDelay 00 00 10 00 00 -- 04 34 - 0 - 4 -- 0290 TxDqsDelay 00 00 11 00 00 -- 04 49 - 2 - 4 -- 0369 TxDqsDelay 00 00 12 00 00 -- 03 58 - 2 - 3 -- 0314 TxDqsDelay 00 00 13 00 00 -- 04 23 - 1 - 4 -- 0343 TxDqsDelay 00 00 14 00 00 -- 03 20 - 1 - 3 -- 0276 TxDqsDelay 00 00 15 00 00 -- 04 26 - 1 - 4 -- 0346 TxDqsDelay 00 00 16 00 00 -- 03 04 - 3 - 3 -- 0260 TxDqsDelay 00 00 17 00 00 -- 04 22 - 1 - 4 -- 0342 TxDqsDelay 00 01 00 00 00 -- 04 54 - 2 - 4 -- 0374 TxDqsDelay 00 01 01 00 00 -- 03 28 - 1 - 3 -- 0284 TxDqsDelay 00 01 02 00 00 -- 05 44 - 0 - 5 -- 0364 TxDqsDelay 00 01 03 00 00 -- 03 53 - 2 - 3 -- 0309 TxDqsDelay 00 01 04 00 00 -- 04 19 - 1 - 4 -- 0339 TxDqsDelay 00 01 05 00 00 -- 03 15 - 3 - 3 -- 0271 TxDqsDelay 00 01 06 00 00 -- 04 20 - 1 - 4 -- 0340 TxDqsDelay 00 01 07 00 00 -- 04 63 - 2 - 4 -- 0383 TxDqsDelay 00 01 08 00 00 -- 04 14 - 3 - 4 -- 0334 TxDqsDelay 00 01 09 00 00 -- 04 54 - 2 - 4 -- 0374 TxDqsDelay 00 01 10 00 00 -- 03 28 - 1 - 3 -- 0284 TxDqsDelay 00 01 11 00 00 -- 05 44 - 0 - 5 -- 0364 TxDqsDelay 00 01 12 00 00 -- 03 53 - 2 - 3 -- 0309 TxDqsDelay 00 01 13 00 00 -- 04 19 - 1 - 4 -- 0339 TxDqsDelay 00 01 14 00 00 -- 03 15 - 3 - 3 -- 0271 TxDqsDelay 00 01 15 00 00 -- 04 20 - 1 - 4 -- 0340 TxDqsDelay 00 01 16 00 00 -- 04 63 - 2 - 4 -- 0383 TxDqsDelay 00 01 17 00 00 -- 04 14 - 3 - 4 -- 0334 S00 S01 S02 S03 S04 S05 S06 S07 S08 S09 S10 S11 S12 S13 S14 S15 S16 S17 R0 251 290 369 314 343 276 346 260 342 251 290 369 314 343 276 346 260 342 R1 374 284 364 309 339 271 340 383 334 374 284 364 309 339 271 340 383 334 elapsedTime: 1301763(us) CP 60 STOP_FineWriteLeveling START_CoarseWriteLeveling Dq: 219 Dq: 261 Dq: 209 Dq: 283 Dq: 308 Dq: 375 Dq: 314 Dq: 360 Dq: 312 Dq: 214 Dq: 254 Dq: 204 Dq: 279 Dq: 308 Dq: 377 Dq: 314 Dq: 358 Dq: 305 Dq: 212 Dq: 254 Dq: 204 Dq: 279 Dq: 304 Dq: 370 Dq: 308 Dq: 352 Dq: 303 Dq: 209 Dq: 248 Dq: 201 Dq: 274 Dq: 305 Dq: 372 Dq: 307 Dq: 352 Dq: 296 Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ---------- -- -- -- -- -- --- --- --- - --- --- --- ---- ---- TxDqsDelay 00 00 00 00 00 -- 02 59 - 2 - 2 -- 0251 TxDqsDelay 00 00 01 00 00 -- 04 34 - 0 - 4 -- 0290 TxDqsDelay 00 00 02 00 00 -- 02 49 - 2 - 2 -- 0241 TxDqsDelay 00 00 03 00 00 -- 03 58 - 2 - 3 -- 0314 TxDqsDelay 00 00 04 00 00 -- 04 23 - 1 - 4 -- 0343 TxDqsDelay 00 00 05 00 00 -- 05 20 - 1 - 5 -- 0404 TxDqsDelay 00 00 06 00 00 -- 04 26 - 1 - 4 -- 0346 TxDqsDelay 00 00 07 00 00 -- 05 04 - 3 - 5 -- 0388 TxDqsDelay 00 00 08 00 00 -- 04 22 - 1 - 4 -- 0342 TxDqsDelay 00 00 09 00 00 -- 02 59 - 2 - 2 -- 0251 TxDqsDelay 00 00 10 00 00 -- 04 34 - 0 - 4 -- 0290 TxDqsDelay 00 00 11 00 00 -- 02 49 - 2 - 2 -- 0241 TxDqsDelay 00 00 12 00 00 -- 03 58 - 2 - 3 -- 0314 TxDqsDelay 00 00 13 00 00 -- 04 23 - 1 - 4 -- 0343 TxDqsDelay 00 00 14 00 00 -- 05 20 - 1 - 5 -- 0404 TxDqsDelay 00 00 15 00 00 -- 04 26 - 1 - 4 -- 0346 TxDqsDelay 00 00 16 00 00 -- 05 04 - 3 - 5 -- 0388 TxDqsDelay 00 00 17 00 00 -- 04 22 - 1 - 4 -- 0342 TxDqsDelay 00 01 00 00 00 -- 02 54 - 2 - 2 -- 0246 TxDqsDelay 00 01 01 00 00 -- 03 28 - 1 - 3 -- 0284 TxDqsDelay 00 01 02 00 00 -- 03 44 - 0 - 3 -- 0236 TxDqsDelay 00 01 03 00 00 -- 03 53 - 2 - 3 -- 0309 TxDqsDelay 00 01 04 00 00 -- 04 19 - 1 - 4 -- 0339 TxDqsDelay 00 01 05 00 00 -- 05 15 - 3 - 5 -- 0399 TxDqsDelay 00 01 06 00 00 -- 04 20 - 1 - 4 -- 0340 TxDqsDelay 00 01 07 00 00 -- 04 63 - 2 - 4 -- 0383 TxDqsDelay 00 01 08 00 00 -- 04 14 - 3 - 4 -- 0334 TxDqsDelay 00 01 09 00 00 -- 02 54 - 2 - 2 -- 0246 TxDqsDelay 00 01 10 00 00 -- 03 28 - 1 - 3 -- 0284 TxDqsDelay 00 01 11 00 00 -- 03 44 - 0 - 3 -- 0236 TxDqsDelay 00 01 12 00 00 -- 03 53 - 2 - 3 -- 0309 TxDqsDelay 00 01 13 00 00 -- 04 19 - 1 - 4 -- 0339 TxDqsDelay 00 01 14 00 00 -- 05 15 - 3 - 5 -- 0399 TxDqsDelay 00 01 15 00 00 -- 04 20 - 1 - 4 -- 0340 TxDqsDelay 00 01 16 00 00 -- 04 63 - 2 - 4 -- 0383 TxDqsDelay 00 01 17 00 00 -- 04 14 - 3 - 4 -- 0334 Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly --------- -- -- -- -- -- --- --- --- - --- --- --- ---- ---- TxDqDelay 00 00 00 00 00 -- 02 27 - 1 - 2 0040 0219 TxDqDelay 00 00 01 00 00 -- 03 05 - 3 - 3 0040 0261 TxDqDelay 00 00 02 00 00 -- 02 17 - 1 - 2 0040 0209 TxDqDelay 00 00 03 00 00 -- 03 27 - 1 - 3 0040 0283 TxDqDelay 00 00 04 00 00 -- 03 52 - 2 - 3 0040 0308 TxDqDelay 00 00 05 00 00 -- 04 55 - 2 - 4 0040 0375 TxDqDelay 00 00 06 00 00 -- 03 58 - 2 - 3 0040 0314 TxDqDelay 00 00 07 00 00 -- 05 40 - 0 - 5 0040 0360 TxDqDelay 00 00 08 00 00 -- 03 56 - 2 - 3 0040 0312 TxDqDelay 00 00 09 00 00 -- 02 22 - 1 - 2 0040 0214 TxDqDelay 00 00 10 00 00 -- 02 62 - 2 - 2 0040 0254 TxDqDelay 00 00 11 00 00 -- 02 12 - 3 - 2 0040 0204 TxDqDelay 00 00 12 00 00 -- 03 23 - 1 - 3 0040 0279 TxDqDelay 00 00 13 00 00 -- 03 52 - 2 - 3 0040 0308 TxDqDelay 00 00 14 00 00 -- 04 57 - 2 - 4 0040 0377 TxDqDelay 00 00 15 00 00 -- 03 58 - 2 - 3 0040 0314 TxDqDelay 00 00 16 00 00 -- 05 38 - 0 - 5 0040 0358 TxDqDelay 00 00 17 00 00 -- 03 49 - 2 - 3 0040 0305 TxDqDelay 00 01 00 00 00 -- 02 20 - 1 - 2 0040 0212 TxDqDelay 00 01 01 00 00 -- 02 62 - 2 - 2 0040 0254 TxDqDelay 00 01 02 00 00 -- 02 12 - 3 - 2 0040 0204 TxDqDelay 00 01 03 00 00 -- 03 23 - 1 - 3 0040 0279 TxDqDelay 00 01 04 00 00 -- 03 48 - 2 - 3 0040 0304 TxDqDelay 00 01 05 00 00 -- 04 50 - 2 - 4 0040 0370 TxDqDelay 00 01 06 00 00 -- 03 52 - 2 - 3 0040 0308 TxDqDelay 00 01 07 00 00 -- 05 32 - 0 - 5 0040 0352 TxDqDelay 00 01 08 00 00 -- 04 47 - 0 - 4 0040 0303 TxDqDelay 00 01 09 00 00 -- 02 17 - 1 - 2 0040 0209 TxDqDelay 00 01 10 00 00 -- 02 56 - 2 - 2 0040 0248 TxDqDelay 00 01 11 00 00 -- 02 09 - 3 - 2 0040 0201 TxDqDelay 00 01 12 00 00 -- 03 18 - 1 - 3 0040 0274 TxDqDelay 00 01 13 00 00 -- 03 49 - 2 - 3 0040 0305 TxDqDelay 00 01 14 00 00 -- 04 52 - 2 - 4 0040 0372 TxDqDelay 00 01 15 00 00 -- 03 51 - 2 - 3 0040 0307 TxDqDelay 00 01 16 00 00 -- 05 32 - 0 - 5 0040 0352 TxDqDelay 00 01 17 00 00 -- 04 40 - 0 - 4 0040 0296 Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ------------ -- -- -- -- -- --- --- --- - --- --- --- ---- ---- TxDqDrvDelay 00 00 00 00 00 -- 02 27 - 1 - 2 -- 0219 TxDqDrvDelay 00 00 01 00 00 -- 03 05 - 3 - 3 -- 0261 TxDqDrvDelay 00 00 02 00 00 -- 02 17 - 1 - 2 -- 0209 TxDqDrvDelay 00 00 03 00 00 -- 03 27 - 1 - 3 -- 0283 TxDqDrvDelay 00 00 04 00 00 -- 03 52 - 2 - 3 -- 0308 TxDqDrvDelay 00 00 05 00 00 -- 04 55 - 2 - 4 -- 0375 TxDqDrvDelay 00 00 06 00 00 -- 03 58 - 2 - 3 -- 0314 TxDqDrvDelay 00 00 07 00 00 -- 05 40 - 0 - 5 -- 0360 TxDqDrvDelay 00 00 08 00 00 -- 03 56 - 2 - 3 -- 0312 TxDqDrvDelay 00 00 09 00 00 -- 02 22 - 1 - 2 -- 0214 TxDqDrvDelay 00 00 10 00 00 -- 02 62 - 2 - 2 -- 0254 TxDqDrvDelay 00 00 11 00 00 -- 02 12 - 3 - 2 -- 0204 TxDqDrvDelay 00 00 12 00 00 -- 03 23 - 1 - 3 -- 0279 TxDqDrvDelay 00 00 13 00 00 -- 03 52 - 2 - 3 -- 0308 TxDqDrvDelay 00 00 14 00 00 -- 04 57 - 2 - 4 -- 0377 TxDqDrvDelay 00 00 15 00 00 -- 03 58 - 2 - 3 -- 0314 TxDqDrvDelay 00 00 16 00 00 -- 05 38 - 0 - 5 -- 0358 TxDqDrvDelay 00 00 17 00 00 -- 03 49 - 2 - 3 -- 0305 TxDqDrvDelay 00 01 00 00 00 -- 02 20 - 1 - 2 -- 0212 TxDqDrvDelay 00 01 01 00 00 -- 02 62 - 2 - 2 -- 0254 TxDqDrvDelay 00 01 02 00 00 -- 02 12 - 3 - 2 -- 0204 TxDqDrvDelay 00 01 03 00 00 -- 03 23 - 1 - 3 -- 0279 TxDqDrvDelay 00 01 04 00 00 -- 03 48 - 2 - 3 -- 0304 TxDqDrvDelay 00 01 05 00 00 -- 04 50 - 2 - 4 -- 0370 TxDqDrvDelay 00 01 06 00 00 -- 03 52 - 2 - 3 -- 0308 TxDqDrvDelay 00 01 07 00 00 -- 05 32 - 0 - 5 -- 0352 TxDqDrvDelay 00 01 08 00 00 -- 04 47 - 0 - 4 -- 0303 TxDqDrvDelay 00 01 09 00 00 -- 02 17 - 1 - 2 -- 0209 TxDqDrvDelay 00 01 10 00 00 -- 02 56 - 2 - 2 -- 0248 TxDqDrvDelay 00 01 11 00 00 -- 02 09 - 3 - 2 -- 0201 TxDqDrvDelay 00 01 12 00 00 -- 03 18 - 1 - 3 -- 0274 TxDqDrvDelay 00 01 13 00 00 -- 03 49 - 2 - 3 -- 0305 TxDqDrvDelay 00 01 14 00 00 -- 04 52 - 2 - 4 -- 0372 TxDqDrvDelay 00 01 15 00 00 -- 03 51 - 2 - 3 -- 0307 TxDqDrvDelay 00 01 16 00 00 -- 05 32 - 0 - 5 -- 0352 TxDqDrvDelay 00 01 17 00 00 -- 04 40 - 0 - 4 -- 0296 S00 S01 S02 S03 S04 S05 S06 S07 S08 S09 S10 S11 S12 S13 S14 S15 S16 S17 R0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 elapsedTime: 5562816(us) CP 57 DnvNibbleTrainingExitHook CP 62 STOP_CoarseWriteLeveling START_ReadTraining bSweepFlags = 0x01 aSweepFlags = 0x13 2nd Timing: 2nd Timing: 2nd Timing: 2nd Timing: 2nd Timing: Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ----------- -- -- -- -- -- --- --- --- - --- --- --- ---- ---- RxDqsPDelay 00 00 00 00 00 -- -- 30 - - - - 0065 0030 RxDqsPDelay 00 00 01 00 00 -- -- 24 - - - - 0060 0024 RxDqsPDelay 00 00 02 00 00 -- -- 28 - - - - 0063 0028 RxDqsPDelay 00 00 03 00 00 -- -- 27 - - - - 0067 0027 RxDqsPDelay 00 00 04 00 00 -- -- 27 - - - - 0061 0027 RxDqsPDelay 00 00 05 00 00 -- -- 22 - - - - 0060 0022 RxDqsPDelay 00 00 06 00 00 -- -- 28 - - - - 0060 0028 RxDqsPDelay 00 00 07 00 00 -- -- 26 - - - - 0058 0026 RxDqsPDelay 00 00 08 00 00 -- -- 26 - - - - 0062 0026 RxDqsPDelay 00 00 09 00 00 -- -- 11 - - - - 0065 0011 RxDqsPDelay 00 00 10 00 00 -- -- 11 - - - - 0060 0011 RxDqsPDelay 00 00 11 00 00 -- -- 11 - - - - 0063 0011 RxDqsPDelay 00 00 12 00 00 -- -- 11 - - - - 0067 0011 RxDqsPDelay 00 00 13 00 00 -- -- 12 - - - - 0061 0012 RxDqsPDelay 00 00 14 00 00 -- -- 12 - - - - 0060 0012 RxDqsPDelay 00 00 15 00 00 -- -- 12 - - - - 0060 0012 RxDqsPDelay 00 00 16 00 00 -- -- 12 - - - - 0058 0012 RxDqsPDelay 00 00 17 00 00 -- -- 11 - - - - 0062 0011 RxDqsPDelay 00 01 00 00 00 -- -- 30 - - - - 0065 0030 RxDqsPDelay 00 01 01 00 00 -- -- 27 - - - - 0060 0027 RxDqsPDelay 00 01 02 00 00 -- -- 29 - - - - 0063 0029 RxDqsPDelay 00 01 03 00 00 -- -- 28 - - - - 0067 0028 RxDqsPDelay 00 01 04 00 00 -- -- 29 - - - - 0061 0029 RxDqsPDelay 00 01 05 00 00 -- -- 24 - - - - 0060 0024 RxDqsPDelay 00 01 06 00 00 -- -- 27 - - - - 0060 0027 RxDqsPDelay 00 01 07 00 00 -- -- 28 - - - - 0058 0028 RxDqsPDelay 00 01 08 00 00 -- -- 28 - - - - 0062 0028 RxDqsPDelay 00 01 09 00 00 -- -- 12 - - - - 0065 0012 RxDqsPDelay 00 01 10 00 00 -- -- 12 - - - - 0060 0012 RxDqsPDelay 00 01 11 00 00 -- -- 12 - - - - 0063 0012 RxDqsPDelay 00 01 12 00 00 -- -- 12 - - - - 0067 0012 RxDqsPDelay 00 01 13 00 00 -- -- 11 - - - - 0061 0011 RxDqsPDelay 00 01 14 00 00 -- -- 11 - - - - 0060 0011 RxDqsPDelay 00 01 15 00 00 -- -- 11 - - - - 0060 0011 RxDqsPDelay 00 01 16 00 00 -- -- 11 - - - - 0058 0011 RxDqsPDelay 00 01 17 00 00 -- -- 12 - - - - 0062 0012 Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ----------- -- -- -- -- -- --- --- --- - --- --- --- ---- ---- RxDqsNDelay 00 00 00 00 00 -- -- 32 - - - - 0065 0032 RxDqsNDelay 00 00 01 00 00 -- -- 29 - - - - 0060 0029 RxDqsNDelay 00 00 02 00 00 -- -- 32 - - - - 0063 0032 RxDqsNDelay 00 00 03 00 00 -- -- 30 - - - - 0067 0030 RxDqsNDelay 00 00 04 00 00 -- -- 31 - - - - 0061 0031 RxDqsNDelay 00 00 05 00 00 -- -- 29 - - - - 0060 0029 RxDqsNDelay 00 00 06 00 00 -- -- 29 - - - - 0060 0029 RxDqsNDelay 00 00 07 00 00 -- -- 31 - - - - 0058 0031 RxDqsNDelay 00 00 08 00 00 -- -- 27 - - - - 0062 0027 RxDqsNDelay 00 00 09 00 00 -- -- 11 - - - - 0065 0011 RxDqsNDelay 00 00 10 00 00 -- -- 11 - - - - 0060 0011 RxDqsNDelay 00 00 11 00 00 -- -- 11 - - - - 0063 0011 RxDqsNDelay 00 00 12 00 00 -- -- 11 - - - - 0067 0011 RxDqsNDelay 00 00 13 00 00 -- -- 12 - - - - 0061 0012 RxDqsNDelay 00 00 14 00 00 -- -- 12 - - - - 0060 0012 RxDqsNDelay 00 00 15 00 00 -- -- 12 - - - - 0060 0012 RxDqsNDelay 00 00 16 00 00 -- -- 12 - - - - 0058 0012 RxDqsNDelay 00 00 17 00 00 -- -- 11 - - - - 0062 0011 RxDqsNDelay 00 01 00 00 00 -- -- 31 - - - - 0065 0031 RxDqsNDelay 00 01 01 00 00 -- -- 26 - - - - 0060 0026 RxDqsNDelay 00 01 02 00 00 -- -- 31 - - - - 0063 0031 RxDqsNDelay 00 01 03 00 00 -- -- 30 - - - - 0067 0030 RxDqsNDelay 00 01 04 00 00 -- -- 30 - - - - 0061 0030 RxDqsNDelay 00 01 05 00 00 -- -- 28 - - - - 0060 0028 RxDqsNDelay 00 01 06 00 00 -- -- 28 - - - - 0060 0028 RxDqsNDelay 00 01 07 00 00 -- -- 31 - - - - 0058 0031 RxDqsNDelay 00 01 08 00 00 -- -- 29 - - - - 0062 0029 RxDqsNDelay 00 01 09 00 00 -- -- 12 - - - - 0065 0012 RxDqsNDelay 00 01 10 00 00 -- -- 12 - - - - 0060 0012 RxDqsNDelay 00 01 11 00 00 -- -- 12 - - - - 0063 0012 RxDqsNDelay 00 01 12 00 00 -- -- 12 - - - - 0067 0012 RxDqsNDelay 00 01 13 00 00 -- -- 11 - - - - 0061 0011 RxDqsNDelay 00 01 14 00 00 -- -- 11 - - - - 0060 0011 RxDqsNDelay 00 01 15 00 00 -- -- 11 - - - - 0060 0011 RxDqsNDelay 00 01 16 00 00 -- -- 11 - - - - 0058 0011 RxDqsNDelay 00 01 17 00 00 -- -- 12 - - - - 0062 0012 Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ------------ -- -- -- -- -- --- --- --- - --- --- --- ---- ---- RxDqBitDelay 00 00 00 00 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 00 01 00 -- -- 255 - - - - -- 0255 RxDqBitDelay 00 00 00 02 00 -- -- 495 - - - - -- 0495 RxDqBitDelay 00 00 00 03 00 -- -- 287 - - - - -- 0287 RxDqBitDelay 00 00 01 00 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 01 01 00 -- -- 623 - - - - -- 0623 RxDqBitDelay 00 00 01 02 00 -- -- 671 - - - - -- 0671 RxDqBitDelay 00 00 01 03 00 -- -- 751 - - - - -- 0751 RxDqBitDelay 00 00 02 00 00 -- -- 607 - - - - -- 0607 RxDqBitDelay 00 00 02 01 00 -- -- 399 - - - - -- 0399 RxDqBitDelay 00 00 02 02 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 02 03 00 -- -- 447 - - - - -- 0447 RxDqBitDelay 00 00 03 00 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 03 01 00 -- -- 911 - - - - -- 0911 RxDqBitDelay 00 00 03 02 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 03 03 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 04 00 00 -- -- 831 - - - - -- 0831 RxDqBitDelay 00 00 04 01 00 -- -- 1007 - - - - -- 1007 RxDqBitDelay 00 00 04 02 00 -- -- 959 - - - - -- 0959 RxDqBitDelay 00 00 04 03 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 05 00 00 -- -- 559 - - - - -- 0559 RxDqBitDelay 00 00 05 01 00 -- -- 911 - - - - -- 0911 RxDqBitDelay 00 00 05 02 00 -- -- 527 - - - - -- 0527 RxDqBitDelay 00 00 05 03 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 06 00 00 -- -- 719 - - - - -- 0719 RxDqBitDelay 00 00 06 01 00 -- -- 591 - - - - -- 0591 RxDqBitDelay 00 00 06 02 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 06 03 00 -- -- 415 - - - - -- 0415 RxDqBitDelay 00 00 07 00 00 -- -- 399 - - - - -- 0399 RxDqBitDelay 00 00 07 01 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 07 02 00 -- -- 383 - - - - -- 0383 RxDqBitDelay 00 00 07 03 00 -- -- 847 - - - - -- 0847 RxDqBitDelay 00 00 08 00 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 08 01 00 -- -- 719 - - - - -- 0719 RxDqBitDelay 00 00 08 02 00 -- -- 671 - - - - -- 0671 RxDqBitDelay 00 00 08 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 09 00 00 -- -- 719 - - - - -- 0719 RxDqBitDelay 00 00 09 01 00 -- -- 367 - - - - -- 0367 RxDqBitDelay 00 00 09 02 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 09 03 00 -- -- 415 - - - - -- 0415 RxDqBitDelay 00 00 10 00 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 10 01 00 -- -- 415 - - - - -- 0415 RxDqBitDelay 00 00 10 02 00 -- -- 575 - - - - -- 0575 RxDqBitDelay 00 00 10 03 00 -- -- 415 - - - - -- 0415 RxDqBitDelay 00 00 11 00 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 11 01 00 -- -- 367 - - - - -- 0367 RxDqBitDelay 00 00 11 02 00 -- -- 623 - - - - -- 0623 RxDqBitDelay 00 00 11 03 00 -- -- 447 - - - - -- 0447 RxDqBitDelay 00 00 12 00 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 12 01 00 -- -- 367 - - - - -- 0367 RxDqBitDelay 00 00 12 02 00 -- -- 447 - - - - -- 0447 RxDqBitDelay 00 00 12 03 00 -- -- 415 - - - - -- 0415 RxDqBitDelay 00 00 13 00 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 13 01 00 -- -- 495 - - - - -- 0495 RxDqBitDelay 00 00 13 02 00 -- -- 607 - - - - -- 0607 RxDqBitDelay 00 00 13 03 00 -- -- 671 - - - - -- 0671 RxDqBitDelay 00 00 14 00 00 -- -- 367 - - - - -- 0367 RxDqBitDelay 00 00 14 01 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 14 02 00 -- -- 527 - - - - -- 0527 RxDqBitDelay 00 00 14 03 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 15 00 00 -- -- 527 - - - - -- 0527 RxDqBitDelay 00 00 15 01 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 15 02 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 15 03 00 -- -- 511 - - - - -- 0511 RxDqBitDelay 00 00 16 00 00 -- -- 607 - - - - -- 0607 RxDqBitDelay 00 00 16 01 00 -- -- 303 - - - - -- 0303 RxDqBitDelay 00 00 16 02 00 -- -- 527 - - - - -- 0527 RxDqBitDelay 00 00 16 03 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 17 00 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 17 01 00 -- -- 575 - - - - -- 0575 RxDqBitDelay 00 00 17 02 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 17 03 00 -- -- 751 - - - - -- 0751 RxDqBitDelay 00 01 00 00 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 01 00 01 00 -- -- 319 - - - - -- 0319 RxDqBitDelay 00 01 00 02 00 -- -- 655 - - - - -- 0655 RxDqBitDelay 00 01 00 03 00 -- -- 335 - - - - -- 0335 RxDqBitDelay 00 01 01 00 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 01 01 01 00 -- -- 703 - - - - -- 0703 RxDqBitDelay 00 01 01 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 01 01 03 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 01 02 00 00 -- -- 1007 - - - - -- 1007 RxDqBitDelay 00 01 02 01 00 -- -- 511 - - - - -- 0511 RxDqBitDelay 00 01 02 02 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 01 02 03 00 -- -- 511 - - - - -- 0511 RxDqBitDelay 00 01 03 00 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 01 03 01 00 -- -- 463 - - - - -- 0463 RxDqBitDelay 00 01 03 02 00 -- -- 735 - - - - -- 0735 RxDqBitDelay 00 01 03 03 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 01 04 00 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 01 04 01 00 -- -- 847 - - - - -- 0847 RxDqBitDelay 00 01 04 02 00 -- -- 847 - - - - -- 0847 RxDqBitDelay 00 01 04 03 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 01 05 00 00 -- -- 511 - - - - -- 0511 RxDqBitDelay 00 01 05 01 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 01 05 02 00 -- -- 639 - - - - -- 0639 RxDqBitDelay 00 01 05 03 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 01 06 00 00 -- -- 1007 - - - - -- 1007 RxDqBitDelay 00 01 06 01 00 -- -- 687 - - - - -- 0687 RxDqBitDelay 00 01 06 02 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 01 06 03 00 -- -- 831 - - - - -- 0831 RxDqBitDelay 00 01 07 00 00 -- -- 319 - - - - -- 0319 RxDqBitDelay 00 01 07 01 00 -- -- 623 - - - - -- 0623 RxDqBitDelay 00 01 07 02 00 -- -- 287 - - - - -- 0287 RxDqBitDelay 00 01 07 03 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 01 08 00 00 -- -- 959 - - - - -- 0959 RxDqBitDelay 00 01 08 01 00 -- -- 879 - - - - -- 0879 RxDqBitDelay 00 01 08 02 00 -- -- 591 - - - - -- 0591 RxDqBitDelay 00 01 08 03 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 01 09 00 00 -- -- 799 - - - - -- 0799 RxDqBitDelay 00 01 09 01 00 -- -- 367 - - - - -- 0367 RxDqBitDelay 00 01 09 02 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 01 09 03 00 -- -- 431 - - - - -- 0431 RxDqBitDelay 00 01 10 00 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 01 10 01 00 -- -- 319 - - - - -- 0319 RxDqBitDelay 00 01 10 02 00 -- -- 575 - - - - -- 0575 RxDqBitDelay 00 01 10 03 00 -- -- 463 - - - - -- 0463 RxDqBitDelay 00 01 11 00 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 01 11 01 00 -- -- 575 - - - - -- 0575 RxDqBitDelay 00 01 11 02 00 -- -- 863 - - - - -- 0863 RxDqBitDelay 00 01 11 03 00 -- -- 335 - - - - -- 0335 RxDqBitDelay 00 01 12 00 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 01 12 01 00 -- -- 447 - - - - -- 0447 RxDqBitDelay 00 01 12 02 00 -- -- 415 - - - - -- 0415 RxDqBitDelay 00 01 12 03 00 -- -- 463 - - - - -- 0463 RxDqBitDelay 00 01 13 00 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 01 13 01 00 -- -- 479 - - - - -- 0479 RxDqBitDelay 00 01 13 02 00 -- -- 655 - - - - -- 0655 RxDqBitDelay 00 01 13 03 00 -- -- 831 - - - - -- 0831 RxDqBitDelay 00 01 14 00 00 -- -- 351 - - - - -- 0351 RxDqBitDelay 00 01 14 01 00 -- -- 1007 - - - - -- 1007 RxDqBitDelay 00 01 14 02 00 -- -- 399 - - - - -- 0399 RxDqBitDelay 00 01 14 03 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 01 15 00 00 -- -- 607 - - - - -- 0607 RxDqBitDelay 00 01 15 01 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 01 15 02 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 01 15 03 00 -- -- 655 - - - - -- 0655 RxDqBitDelay 00 01 16 00 00 -- -- 543 - - - - -- 0543 RxDqBitDelay 00 01 16 01 00 -- -- 431 - - - - -- 0431 RxDqBitDelay 00 01 16 02 00 -- -- 703 - - - - -- 0703 RxDqBitDelay 00 01 16 03 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 01 17 00 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 01 17 01 00 -- -- 463 - - - - -- 0463 RxDqBitDelay 00 01 17 02 00 -- -- 735 - - - - -- 0735 RxDqBitDelay 00 01 17 03 00 -- -- 735 - - - - -- 0735 S00 S01 S02 S03 S04 S05 S06 S07 S08 R0 00 00 00 00 00 00 00 00 00 R1 00 00 00 00 00 00 00 00 00 elapsedTime: 82139538(us) CP 57 DnvNibbleTrainingHook CP 61 STOP_ReadTraining START_WriteTraining TXEQ Final Value = 2 bSweepFlags = 0x01 aSweepFlags = 0x13 bSweepFlags = 0x09 aSweepFlags = 0x1B Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly --------- -- -- -- -- -- --- --- --- - --- --- --- ---- ---- TxDqDelay 00 00 00 00 00 -- 02 25 - 1 - 2 0042 0217 TxDqDelay 00 00 01 00 00 -- 03 03 - 3 - 3 0042 0259 TxDqDelay 00 00 02 00 00 -- 02 14 - 3 - 2 0041 0206 TxDqDelay 00 00 03 00 00 -- 03 26 - 1 - 3 0042 0282 TxDqDelay 00 00 04 00 00 -- 03 50 - 2 - 3 0043 0306 TxDqDelay 00 00 05 00 00 -- 04 52 - 2 - 4 0042 0372 TxDqDelay 00 00 06 00 00 -- 03 56 - 2 - 3 0042 0312 TxDqDelay 00 00 07 00 00 -- 05 35 - 0 - 5 0042 0355 TxDqDelay 00 00 08 00 00 -- 03 54 - 2 - 3 0041 0310 TxDqDelay 00 00 09 00 00 -- 02 21 - 1 - 2 0042 0213 TxDqDelay 00 00 10 00 00 -- 02 60 - 2 - 2 0041 0252 TxDqDelay 00 00 11 00 00 -- 02 10 - 3 - 2 0041 0202 TxDqDelay 00 00 12 00 00 -- 03 22 - 1 - 3 0041 0278 TxDqDelay 00 00 13 00 00 -- 03 53 - 2 - 3 0043 0309 TxDqDelay 00 00 14 00 00 -- 04 55 - 2 - 4 0041 0375 TxDqDelay 00 00 15 00 00 -- 03 58 - 2 - 3 0042 0314 TxDqDelay 00 00 16 00 00 -- 05 37 - 0 - 5 0042 0357 TxDqDelay 00 00 17 00 00 -- 03 48 - 2 - 3 0041 0304 TxDqDelay 00 01 00 00 00 -- 02 19 - 1 - 2 0042 0211 TxDqDelay 00 01 01 00 00 -- 02 59 - 2 - 2 0041 0251 TxDqDelay 00 01 02 00 00 -- 02 10 - 3 - 2 0041 0202 TxDqDelay 00 01 03 00 00 -- 03 20 - 1 - 3 0041 0276 TxDqDelay 00 01 04 00 00 -- 04 46 - 0 - 4 0042 0302 TxDqDelay 00 01 05 00 00 -- 05 46 - 0 - 5 0042 0366 TxDqDelay 00 01 06 00 00 -- 03 51 - 2 - 3 0041 0307 TxDqDelay 00 01 07 00 00 -- 04 26 - 1 - 4 0042 0346 TxDqDelay 00 01 08 00 00 -- 04 44 - 0 - 4 0041 0300 TxDqDelay 00 01 09 00 00 -- 02 16 - 1 - 2 0043 0208 TxDqDelay 00 01 10 00 00 -- 02 54 - 2 - 2 0040 0246 TxDqDelay 00 01 11 00 00 -- 02 08 - 3 - 2 0042 0200 TxDqDelay 00 01 12 00 00 -- 03 17 - 1 - 3 0041 0273 TxDqDelay 00 01 13 00 00 -- 03 48 - 2 - 3 0042 0304 TxDqDelay 00 01 14 00 00 -- 04 49 - 2 - 4 0042 0369 TxDqDelay 00 01 15 00 00 -- 03 51 - 2 - 3 0041 0307 TxDqDelay 00 01 16 00 00 -- 04 30 - 1 - 4 0042 0350 TxDqDelay 00 01 17 00 00 -- 04 39 - 0 - 4 0040 0295 Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ------------ -- -- -- -- -- --- --- --- - --- --- --- ---- ---- TxDqDrvDelay 00 00 00 00 00 -- 02 25 - 1 - 2 -- 0217 TxDqDrvDelay 00 00 01 00 00 -- 03 03 - 3 - 3 -- 0259 TxDqDrvDelay 00 00 02 00 00 -- 02 14 - 3 - 2 -- 0206 TxDqDrvDelay 00 00 03 00 00 -- 03 26 - 1 - 3 -- 0282 TxDqDrvDelay 00 00 04 00 00 -- 03 50 - 2 - 3 -- 0306 TxDqDrvDelay 00 00 05 00 00 -- 04 52 - 2 - 4 -- 0372 TxDqDrvDelay 00 00 06 00 00 -- 03 56 - 2 - 3 -- 0312 TxDqDrvDelay 00 00 07 00 00 -- 05 35 - 0 - 5 -- 0355 TxDqDrvDelay 00 00 08 00 00 -- 03 54 - 2 - 3 -- 0310 TxDqDrvDelay 00 00 09 00 00 -- 02 21 - 1 - 2 -- 0213 TxDqDrvDelay 00 00 10 00 00 -- 02 60 - 2 - 2 -- 0252 TxDqDrvDelay 00 00 11 00 00 -- 02 10 - 3 - 2 -- 0202 TxDqDrvDelay 00 00 12 00 00 -- 03 22 - 1 - 3 -- 0278 TxDqDrvDelay 00 00 13 00 00 -- 03 53 - 2 - 3 -- 0309 TxDqDrvDelay 00 00 14 00 00 -- 04 55 - 2 - 4 -- 0375 TxDqDrvDelay 00 00 15 00 00 -- 03 58 - 2 - 3 -- 0314 TxDqDrvDelay 00 00 16 00 00 -- 05 37 - 0 - 5 -- 0357 TxDqDrvDelay 00 00 17 00 00 -- 03 48 - 2 - 3 -- 0304 TxDqDrvDelay 00 01 00 00 00 -- 02 19 - 1 - 2 -- 0211 TxDqDrvDelay 00 01 01 00 00 -- 02 59 - 2 - 2 -- 0251 TxDqDrvDelay 00 01 02 00 00 -- 02 10 - 3 - 2 -- 0202 TxDqDrvDelay 00 01 03 00 00 -- 03 20 - 1 - 3 -- 0276 TxDqDrvDelay 00 01 04 00 00 -- 04 46 - 0 - 4 -- 0302 TxDqDrvDelay 00 01 05 00 00 -- 05 46 - 0 - 5 -- 0366 TxDqDrvDelay 00 01 06 00 00 -- 03 51 - 2 - 3 -- 0307 TxDqDrvDelay 00 01 07 00 00 -- 04 26 - 1 - 4 -- 0346 TxDqDrvDelay 00 01 08 00 00 -- 04 44 - 0 - 4 -- 0300 TxDqDrvDelay 00 01 09 00 00 -- 02 16 - 1 - 2 -- 0208 TxDqDrvDelay 00 01 10 00 00 -- 02 54 - 2 - 2 -- 0246 TxDqDrvDelay 00 01 11 00 00 -- 02 08 - 3 - 2 -- 0200 TxDqDrvDelay 00 01 12 00 00 -- 03 17 - 1 - 3 -- 0273 TxDqDrvDelay 00 01 13 00 00 -- 03 48 - 2 - 3 -- 0304 TxDqDrvDelay 00 01 14 00 00 -- 04 49 - 2 - 4 -- 0369 TxDqDrvDelay 00 01 15 00 00 -- 03 51 - 2 - 3 -- 0307 TxDqDrvDelay 00 01 16 00 00 -- 04 30 - 1 - 4 -- 0350 TxDqDrvDelay 00 01 17 00 00 -- 04 39 - 0 - 4 -- 0295 Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ------------ -- -- -- -- -- --- --- --- - --- --- --- ---- ---- TxDqBitDelay 00 00 00 00 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 00 01 00 -- -- 335 - - - - -- 0335 TxDqBitDelay 00 00 00 02 00 -- -- 799 - - - - -- 0799 TxDqBitDelay 00 00 00 03 00 -- -- 479 - - - - -- 0479 TxDqBitDelay 00 00 01 00 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 01 01 00 -- -- 591 - - - - -- 0591 TxDqBitDelay 00 00 01 02 00 -- -- 879 - - - - -- 0879 TxDqBitDelay 00 00 01 03 00 -- -- 815 - - - - -- 0815 TxDqBitDelay 00 00 02 00 00 -- -- 591 - - - - -- 0591 TxDqBitDelay 00 00 02 01 00 -- -- 479 - - - - -- 0479 TxDqBitDelay 00 00 02 02 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 02 03 00 -- -- 399 - - - - -- 0399 TxDqBitDelay 00 00 03 00 00 -- -- 575 - - - - -- 0575 TxDqBitDelay 00 00 03 01 00 -- -- 559 - - - - -- 0559 TxDqBitDelay 00 00 03 02 00 -- -- 815 - - - - -- 0815 TxDqBitDelay 00 00 03 03 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 04 00 00 -- -- 591 - - - - -- 0591 TxDqBitDelay 00 00 04 01 00 -- -- 735 - - - - -- 0735 TxDqBitDelay 00 00 04 02 00 -- -- 671 - - - - -- 0671 TxDqBitDelay 00 00 04 03 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 05 00 00 -- -- 447 - - - - -- 0447 TxDqBitDelay 00 00 05 01 00 -- -- 991 - - - - -- 0991 TxDqBitDelay 00 00 05 02 00 -- -- 543 - - - - -- 0543 TxDqBitDelay 00 00 05 03 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 06 00 00 -- -- 543 - - - - -- 0543 TxDqBitDelay 00 00 06 01 00 -- -- 703 - - - - -- 0703 TxDqBitDelay 00 00 06 02 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 06 03 00 -- -- 703 - - - - -- 0703 TxDqBitDelay 00 00 07 00 00 -- -- 383 - - - - -- 0383 TxDqBitDelay 00 00 07 01 00 -- -- 847 - - - - -- 0847 TxDqBitDelay 00 00 07 02 00 -- -- 591 - - - - -- 0591 TxDqBitDelay 00 00 07 03 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 08 00 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 08 01 00 -- -- 847 - - - - -- 0847 TxDqBitDelay 00 00 08 02 00 -- -- 847 - - - - -- 0847 TxDqBitDelay 00 00 08 03 00 -- -- 943 - - - - -- 0943 TxDqBitDelay 00 00 09 00 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 09 01 00 -- -- 735 - - - - -- 0735 TxDqBitDelay 00 00 09 02 00 -- -- 687 - - - - -- 0687 TxDqBitDelay 00 00 09 03 00 -- -- 447 - - - - -- 0447 TxDqBitDelay 00 00 10 00 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 10 01 00 -- -- 479 - - - - -- 0479 TxDqBitDelay 00 00 10 02 00 -- -- 367 - - - - -- 0367 TxDqBitDelay 00 00 10 03 00 -- -- 351 - - - - -- 0351 TxDqBitDelay 00 00 11 00 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 11 01 00 -- -- 367 - - - - -- 0367 TxDqBitDelay 00 00 11 02 00 -- -- 495 - - - - -- 0495 TxDqBitDelay 00 00 11 03 00 -- -- 367 - - - - -- 0367 TxDqBitDelay 00 00 12 00 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 12 01 00 -- -- 447 - - - - -- 0447 TxDqBitDelay 00 00 12 02 00 -- -- 367 - - - - -- 0367 TxDqBitDelay 00 00 12 03 00 -- -- 639 - - - - -- 0639 TxDqBitDelay 00 00 13 00 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 13 01 00 -- -- 703 - - - - -- 0703 TxDqBitDelay 00 00 13 02 00 -- -- 463 - - - - -- 0463 TxDqBitDelay 00 00 13 03 00 -- -- 623 - - - - -- 0623 TxDqBitDelay 00 00 14 00 00 -- -- 415 - - - - -- 0415 TxDqBitDelay 00 00 14 01 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 14 02 00 -- -- 335 - - - - -- 0335 TxDqBitDelay 00 00 14 03 00 -- -- 783 - - - - -- 0783 TxDqBitDelay 00 00 15 00 00 -- -- 623 - - - - -- 0623 TxDqBitDelay 00 00 15 01 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 15 02 00 -- -- 687 - - - - -- 0687 TxDqBitDelay 00 00 15 03 00 -- -- 495 - - - - -- 0495 TxDqBitDelay 00 00 16 00 00 -- -- 911 - - - - -- 0911 TxDqBitDelay 00 00 16 01 00 -- -- 543 - - - - -- 0543 TxDqBitDelay 00 00 16 02 00 -- -- 399 - - - - -- 0399 TxDqBitDelay 00 00 16 03 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 17 00 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 17 01 00 -- -- 639 - - - - -- 0639 TxDqBitDelay 00 00 17 02 00 -- -- 687 - - - - -- 0687 TxDqBitDelay 00 00 17 03 00 -- -- 671 - - - - -- 0671 TxDqBitDelay 00 01 00 00 00 -- -- 607 - - - - -- 0607 TxDqBitDelay 00 01 00 01 00 -- -- 351 - - - - -- 0351 TxDqBitDelay 00 01 00 02 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 01 00 03 00 -- -- 543 - - - - -- 0543 TxDqBitDelay 00 01 01 00 00 -- -- 495 - - - - -- 0495 TxDqBitDelay 00 01 01 01 00 -- -- 447 - - - - -- 0447 TxDqBitDelay 00 01 01 02 00 -- -- 431 - - - - -- 0431 TxDqBitDelay 00 01 01 03 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 01 02 00 00 -- -- 687 - - - - -- 0687 TxDqBitDelay 00 01 02 01 00 -- -- 335 - - - - -- 0335 TxDqBitDelay 00 01 02 02 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 01 02 03 00 -- -- 527 - - - - -- 0527 TxDqBitDelay 00 01 03 00 00 -- -- 495 - - - - -- 0495 TxDqBitDelay 00 01 03 01 00 -- -- 351 - - - - -- 0351 TxDqBitDelay 00 01 03 02 00 -- -- 495 - - - - -- 0495 TxDqBitDelay 00 01 03 03 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 01 04 00 00 -- -- 607 - - - - -- 0607 TxDqBitDelay 00 01 04 01 00 -- -- 527 - - - - -- 0527 TxDqBitDelay 00 01 04 02 00 -- -- 879 - - - - -- 0879 TxDqBitDelay 00 01 04 03 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 01 05 00 00 -- -- 415 - - - - -- 0415 TxDqBitDelay 00 01 05 01 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 01 05 02 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 01 05 03 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 01 06 00 00 -- -- 703 - - - - -- 0703 TxDqBitDelay 00 01 06 01 00 -- -- 543 - - - - -- 0543 TxDqBitDelay 00 01 06 02 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 01 06 03 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 01 07 00 00 -- -- 271 - - - - -- 0271 TxDqBitDelay 00 01 07 01 00 -- -- 463 - - - - -- 0463 TxDqBitDelay 00 01 07 02 00 -- -- 303 - - - - -- 0303 TxDqBitDelay 00 01 07 03 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 01 08 00 00 -- -- 591 - - - - -- 0591 TxDqBitDelay 00 01 08 01 00 -- -- 575 - - - - -- 0575 TxDqBitDelay 00 01 08 02 00 -- -- 703 - - - - -- 0703 TxDqBitDelay 00 01 08 03 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 01 09 00 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 01 09 01 00 -- -- 575 - - - - -- 0575 TxDqBitDelay 00 01 09 02 00 -- -- 831 - - - - -- 0831 TxDqBitDelay 00 01 09 03 00 -- -- 735 - - - - -- 0735 TxDqBitDelay 00 01 10 00 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 01 10 01 00 -- -- 447 - - - - -- 0447 TxDqBitDelay 00 01 10 02 00 -- -- 447 - - - - -- 0447 TxDqBitDelay 00 01 10 03 00 -- -- 399 - - - - -- 0399 TxDqBitDelay 00 01 11 00 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 01 11 01 00 -- -- 607 - - - - -- 0607 TxDqBitDelay 00 01 11 02 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 01 11 03 00 -- -- 431 - - - - -- 0431 TxDqBitDelay 00 01 12 00 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 01 12 01 00 -- -- 575 - - - - -- 0575 TxDqBitDelay 00 01 12 02 00 -- -- 415 - - - - -- 0415 TxDqBitDelay 00 01 12 03 00 -- -- 815 - - - - -- 0815 TxDqBitDelay 00 01 13 00 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 01 13 01 00 -- -- 511 - - - - -- 0511 TxDqBitDelay 00 01 13 02 00 -- -- 639 - - - - -- 0639 TxDqBitDelay 00 01 13 03 00 -- -- 639 - - - - -- 0639 TxDqBitDelay 00 01 14 00 00 -- -- 303 - - - - -- 0303 TxDqBitDelay 00 01 14 01 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 01 14 02 00 -- -- 319 - - - - -- 0319 TxDqBitDelay 00 01 14 03 00 -- -- 831 - - - - -- 0831 TxDqBitDelay 00 01 15 00 00 -- -- 399 - - - - -- 0399 TxDqBitDelay 00 01 15 01 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 01 15 02 00 -- -- 575 - - - - -- 0575 TxDqBitDelay 00 01 15 03 00 -- -- 399 - - - - -- 0399 TxDqBitDelay 00 01 16 00 00 -- -- 575 - - - - -- 0575 TxDqBitDelay 00 01 16 01 00 -- -- 383 - - - - -- 0383 TxDqBitDelay 00 01 16 02 00 -- -- 399 - - - - -- 0399 TxDqBitDelay 00 01 16 03 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 01 17 00 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 01 17 01 00 -- -- 527 - - - - -- 0527 TxDqBitDelay 00 01 17 02 00 -- -- 511 - - - - -- 0511 TxDqBitDelay 00 01 17 03 00 -- -- 687 - - - - -- 0687 S00 S01 S02 S03 S04 S05 S06 S07 S08 S09 S10 S11 S12 S13 S14 S15 S16 S17 R0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 elapsedTime: 29594612(us) CP 57 DnvNibbleTrainingExitHook CP 63 STOP_WriteTraining START_CommandClockTraining Setting CMD GRP = 340 at 3N Setting CMD GRP = 340 at 3N Setting CMD GRP = 324 at 3N Setting CMD GRP = 308 at 3N Setting CMD GRP = 292 at 3N Setting CMD GRP = 276 at 3N Setting CMD GRP = 260 at 3N Setting CMD GRP = 244 at 3N Setting CMD GRP = 228 at 3N Setting CMD GRP = 212 at 3N Setting CMD GRP = 196 at 3N Setting CMD GRP = 180 at 3N Setting CMD GRP = 356 at 3N Setting CMD GRP = 372 at 3N Setting CMD GRP = 388 at 3N Setting CMD GRP = 404 at 3N Setting CMD GRP = 420 at 3N Setting CMD GRP = 436 at 3N Setting CMD GRP = 452 at 3N Setting CMD GRP = 468 at 3N Setting CMD GRP = 484 at 3N Setting CMD GRP = 500 at 3N Setting CMD GRP = 340 at 3N **ReInitialize Setting CMD GRP = 332 at 3N **Result L: -160 H:144 New Value = 332 Setting CMD GRP = 332 at 1N Setting CMD GRP = 332 at 3N **ReInitialize Setting CMD GRP = 316 at 1N Setting CMD GRP = 332 at 3N **ReInitialize Setting CMD GRP = 300 at 1N Setting CMD GRP = 332 at 3N **ReInitialize Setting CMD GRP = 284 at 1N Setting CMD GRP = 332 at 3N **ReInitialize Setting CMD GRP = 268 at 1N Setting CMD GRP = 332 at 3N **ReInitialize Setting CMD GRP = 252 at 1N Setting CMD GRP = 332 at 3N **ReInitialize Setting CMD GRP = 236 at 1N Setting CMD GRP = 220 at 1N Setting CMD GRP = 204 at 1N Setting CMD GRP = 188 at 1N Setting CMD GRP = 172 at 1N Setting CMD GRP = 332 at 3N **ReInitialize Setting CMD GRP = 348 at 1N Setting CMD GRP = 332 at 3N **ReInitialize Setting CMD GRP = 364 at 1N Setting CMD GRP = 332 at 3N **ReInitialize Setting CMD GRP = 380 at 1N Setting CMD GRP = 332 at 3N **ReInitialize Setting CMD GRP = 396 at 1N Setting CMD GRP = 332 at 3N **ReInitialize Setting CMD GRP = 412 at 1N Setting CMD GRP = 332 at 3N **ReInitialize Setting CMD GRP = 428 at 1N Setting CMD GRP = 332 at 3N **ReInitialize Setting CMD GRP = 444 at 1N Setting CMD GRP = 332 at 3N **ReInitialize Setting CMD GRP = 460 at 1N Setting CMD GRP = 332 at 3N **ReInitialize Setting CMD GRP = 476 at 1N Setting CMD GRP = 332 at 3N **ReInitialize Setting CMD GRP = 492 at 1N Setting CMD GRP = 332 at 3N **ReInitialize Setting CMD GRP = 212 at 1N **Result L: -48 H:-1 New Value = 212 bSweepFlags = 0x01 aSweepFlags = 0x01 bSweepFlags = 0x09 aSweepFlags = 0x09 Ch 0, Dimm 0, Rank 0, MaxDq: 9 MaxBit: 8 Ch 0, Dimm 0, Rank 1, MaxDq: 9 MaxBit: 8 Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ------- -- -- -- -- -- --- --- --- - --- --- --- ---- ---- CmdGrp0 00 00 00 00 00 -- 02 16 - 1 - 2 0031 0208 CmdGrp0 00 01 00 00 00 -- 02 16 - 1 - 2 0031 0208 Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ------- -- -- -- -- -- --- --- --- - --- --- --- ---- ---- CmdGrp1 00 00 00 00 00 -- 02 16 - 1 - 2 0031 0208 CmdGrp1 00 01 00 00 00 -- 02 16 - 1 - 2 0031 0208 Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ------- -- -- -- -- -- --- --- --- - --- --- --- ---- ---- CmdGrp2 00 00 00 00 00 -- 02 16 - 1 - 2 0031 0208 CmdGrp2 00 01 00 00 00 -- 02 16 - 1 - 2 0031 0208 Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ------- -- -- -- -- -- --- --- --- - --- --- --- ---- ---- CmdGrp3 00 00 00 00 00 -- 02 16 - 1 - 2 0031 0208 CmdGrp3 00 01 00 00 00 -- 02 16 - 1 - 2 0031 0208 Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ------- -- -- -- -- -- --- --- --- - --- --- --- ---- ---- CmdGrp4 00 00 00 00 00 -- 02 16 - 1 - 2 0031 0208 CmdGrp4 00 01 00 00 00 -- 02 16 - 1 - 2 0031 0208 Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ------- -- -- -- -- -- --- --- --- - --- --- --- ---- ---- CmdGrp5 00 00 00 00 00 -- 02 16 - 1 - 2 0031 0208 CmdGrp5 00 01 00 00 00 -- 02 16 - 1 - 2 0031 0208 Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ------- -- -- -- -- -- --- --- --- - --- --- --- ---- ---- CmdGrp6 00 00 00 00 00 -- 02 16 - 1 - 2 0031 0208 CmdGrp6 00 01 00 00 00 -- 02 16 - 1 - 2 0031 0208 Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ------- -- -- -- -- -- --- --- --- - --- --- --- ---- ---- CmdGrp7 00 00 00 00 00 -- 02 16 - 1 - 2 0031 0208 CmdGrp7 00 01 00 00 00 -- 02 16 - 1 - 2 0031 0208 S00 S01 S02 S03 S04 S05 S06 S07 S08 R0 00 00 00 00 00 00 00 00 00 R1 00 00 00 00 00 00 00 00 00 elapsedTime: 19493102(us) CP 64 STOP_CommandClockTraining RxTxSkewCtl CP F5 FastBootChecker elapsedTime: 341031(us) CP 65 SearchRmtWrapper elapsedTime: 102(us) CP 65 CP 66 PhyViewTable elapsedTime: 3(us) CP 68 elapsedTime: 41(us) CP 69 VrefOverride elapsedTime: 8(us) CP 70 elapsedTime: 19(us) CP 71 elapsedTime: 225(us) CP 72 ProgSliceChannelHash CP 73 DUnitAftTrain Box Port Offset Mask Action Delay Value +DUNIT MEM 0xFED11158 0x0000000000FFFFFF SET 0x00000000 0x0000000000100043 +DUNIT_COMMON MEM 0xFED11408 0x0000000003000000 SET 0x00000000 0x0000000000000000 +DUNIT MEM 0xFED11174 0x00000000FFFFFFFF SET 0x00000000 0x000000003E161DAB +DUNIT MEM 0xFED110B4 0x00000000FFFFFFFF SET 0x00000000 0x000000000000003F +DUNIT MEM 0xFED110B4 0x00000000000000FF SET 0x00000000 0x000000000000003F +DUNIT MEM 0xFED11148 0x00000000FFFFFFFF SET 0x00000000 0x000000002307B949 +DUNIT MEM 0xFED1114C 0x00000000FFFFFFFF SET 0x00000000 0x000000002F6AD272 +DUNIT MEM 0xFED11150 0x00000000FFFFFFFF SET 0x00000000 0x000000003FFFEB38 +DUNIT MEM 0xFED11154 0x00000000FFFFFFFF SET 0x00000000 0x0000000006543210 elapsedTime: 391566(us) CP 76 elapsedTime: 145(us) CP 77 CP 78 elapsedTime: 15(us) CP 79 elapsedTime: 129(us) CP 80 PassGateTest Pass Gate Test Not Enabled elapsedTime: 11450(us) CP 81 DisplayInformation Slot[0] - DimmId {0x7A : Unknown } - DramId {0xCE : Samsung} Slot[1] - Not present R0 Mrs[0]: 0x00073008 Mrs[1]: 0x000C0318 Mrs[2]: 0x0004E028 Mrs[3]: 0x00020038 Mrs[4]: 0x00000048 Mrs[5]: 0x00018058 Mrs[6]: 0x00081168 Mrs[7]: 0x00000000 Mrs[8]: 0x00000000 Mrs[9]: 0x00089168 Mrs[10]: 0x00000000 Mrs[11]: 0x00000000 Mrs[12]: 0x00000000 Mrs[13]: 0x00000000 Mrs[14]: 0x00000000 Mrs[15]: 0x00000000 Mrs[16]: 0x00000000 Mrs[17]: 0x00000000 Mrs[18]: 0x00000000 Mrs[19]: 0x00000000 Mrs[20]: 0x00000000 Mrs[21]: 0x00000000 Mrs[22]: 0x00000000 Mrs[23]: 0x00000000 Mrs[24]: 0x00000000 Mrs[25]: 0x00000000 Mrs[26]: 0x00000000 Mrs[27]: 0x00000000 Mrs[28]: 0x00000000 Mrs[29]: 0x00000000 Mrs[30]: 0x00000000 Mrs[31]: 0x00000000 Mrs[32]: 0x00000000 Mrs[33]: 0x00000000 Mrs[34]: 0x00000000 R1 Mrs[0]: 0x0406C808 Mrs[1]: 0x04240328 Mrs[2]: 0x04056018 Mrs[3]: 0x04020038 Mrs[4]: 0x04000088 Mrs[5]: 0x040180A8 Mrs[6]: 0x04200998 Mrs[7]: 0x00000000 Mrs[8]: 0x00000000 Mrs[9]: 0x04210998 Mrs[10]: 0x00000000 Mrs[11]: 0x00000000 Mrs[12]: 0x00000000 Mrs[13]: 0x00000000 Mrs[14]: 0x00000000 Mrs[15]: 0x00000000 Mrs[16]: 0x00000000 Mrs[17]: 0x00000000 Mrs[18]: 0x00000000 Mrs[19]: 0x00000000 Mrs[20]: 0x00000000 Mrs[21]: 0x00000000 Mrs[22]: 0x00000000 Mrs[23]: 0x00000000 Mrs[24]: 0x00000000 Mrs[25]: 0x00000000 Mrs[26]: 0x00000000 Mrs[27]: 0x00000000 Mrs[28]: 0x00000000 Mrs[29]: 0x00000000 Mrs[30]: 0x00000000 Mrs[31]: 0x00000000 Mrs[32]: 0x00000000 Mrs[33]: 0x00000000 Mrs[34]: 0x00000000 elapsedTime: 664471(us) CP 82 PostPackageRepairEntry Ppr not running elapsedTime: 6702(us) CP 83 RaplSupport CP B0 CaParityEnable elapsedTime: 48(us) CP A0 elapsedTime: 24(us) CP B2 elapsedTime: 10(us) CP 84 MemoryTest CH0 Testing: 8192MB CH0 Test TOTAL_CACHE_LINES 0x07FFFFFF CH1 Test TOTAL_CACHE_LINES 0x00000000 elapsedTime: 10597336(us) CP 85 CP 86 ScrubMemory MrcData->MrcParameters.EccEnabled = 1 Memory Init executed (MemInitPerDimm) Scrubbing L: 0x0000000000000000 H: 0x0000000007FFFFFF ECC Enabled successfully elapsedTime: 1382523(us) CP B0 CP 87 elapsedTime: 32(us) CP 88 elapsedTime: 163(us) CP 35 CP 89 elapsedTime: 8(us) CP 90 elapsedTime: 108(us) CP 91 elapsedTime: 32(us) CP 92 CP 93 RestoreArmNvDimms CP 93 ProgramParityCheck ProgramParityCheck Parity Check Enabled MSR[0x0410] cR[0x410] = 0x0000000000000000 mR[0x410] = 0x0000000000000000 MSR[0x0410] Low: 0x00000180 High: 0x00000000 MSR[0x0410] vR[0x410] = 0x0000000000000180 MSR[0x0418] cR[0x418] = 0x0000000000000000 mR[0x418] = 0x0000000000000000 MSR[0x0418] Low: 0x001F0000 High: 0x00000000 MSR[0x0418] vR[0x418] = 0x00000000001F0000 CP A0 MciDunit elapsedTime: 9(us) CP 94 elapsedTime: 232(us) CP 95 CP 96 CP 97 CP 98 SignalPunitMemInitDone Install EFI Memory. MmioAllocation: 0x00000800 UpperTotalMemory: 0x0000000200000000 HostIOBoundary: 0x80000000 HostIOBoundaryHi: 0x0000000280000000 TSegBase: 0x7FE00000 TSegSize: 0x00200000 UpperTotalMemory after remap: 0x0000000280000000 RSVD memory region has been not power-of-two aligned. New RSVD Memory Base: 0x7FC00000 Length: 0x400000 PeiInstallPeiMemory MemoryBegin 0x7F7FE000, MemoryLength 0x400000 Low Memory Space Available =0x7FC00000 High Memory Space Available =0x180000000 -------------------Memory Mapping---------------- PeiMemory: 0x7F7FE000 -- 0x7FBFDFFF System Memory: 0x0 -- 0x9FFFF Reserved Memory: 0xA0000 -- 0xFFFFF System Memory: 0x100000 -- 0x7F7FDFFF Reserved Memory: 0x7F7FE000 -- 0x7FBFDFFF Iqat (RSVD) Mem: 0x7FD00000 -- 0x7FDFFFFF Reserved Memory: 0x7FC00000 -- 0x7FCFFFFF dTSeg: 0x7FE00000 -- 0x7FFFFFFF UpperMemory: 0x100000000 -- 0x27FFFFFFF Filling BDAT Memory Schema 2 Structure Max Data for a HOB = 65504 Bytes BDAT_MEMORY_DATA_2_STRUCTURE = 9053 Bytes BdatMemoryData2Hob = 0xFEF64248 MrcParamsSave Hob:FEF665E0 BufferSize:0x000079A4 MrcParamsHob:79A4 Save MRC params. MemoryInit Installed. ME UMA: UMA Enabled flag = 1 Send DRAM_INIT_DONE to ME (InitStart = 0x0). ME UMA: UMA Enabled flag = 1 ---------------------- MePlatformPolicyPpi Dump Begin ----------------- Revision : 0x3 MeConfig --- DidEnabled : 0x1 DidInitStat : 0x0 HeciCommunication1 : 0x1 HeciCommunication2 : 0x0 HeciCommunication3 : 0x0 SolEnabled : 0x0 IderEnabled : 0x0 WaitResetWarningAck : 0x0 EnableMePreDidReset : 0x0 ---------------------- MePlatformPolicyPpi Dump End ------------------- ME UMA: Entered ME DRAM Init Done procedure. ME UMA: MeUmaBase read: 0 ME UMA: InitStat: 0 Sending DID as MKHI message [HECI] Send msg: 80080007 000001F0 ... [HECI] Got msg: 80080007 000081F0 ... ME UMA: BiosAction = 7 ME UMA: Sending MemoryInitDoneSent Notification ... Install PPI: 12AA57CB-E6F0-40A3-BDF4-B0690C9CCF06 Notify: PPI Guid: 12AA57CB-E6F0-40A3-BDF4-B0690C9CCF06, Peim notify entry point: FFF6D8BE [SPS] SpsNonS3Path called [SPS] Waiting for ME firmware init complete [SPS] Sending ME-BIOS Interface Version request [HECI] Send msg: 80010020 00000001 [HECI] Got msg: 800B0020 06010181 ... [SPS] SPS ME-BIOS interface version is 1.1 Feature set is 0x9B8106 [SPS] HOB: features 0x9B8106, flow 0, boot mode 1, cores to disable 0 [SPS] (ICC) Send ICC Set Clock Settings command (SSC Setting 1) [SPS] (ICC) SpsSetCurrenClockingMode [HECI] Send msg: 80300008 00040000 ... [HECI] Got msg: 80300008 00040000 ... [SPS] (ICC) SpsSetCurrenClockingMode exit status = Success [SPS] SpsFspInitComplete Start [SPS] SpsFspInitComplete HOB: features 0x9B8106, flow 0, boot mode 1, cores to disable 0 [SPS] SiliconEnabling Mode Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B [SPS] SpsFspInitComplete End [0] ME UMA: Sent MemoryInitDoneSent Notification (Success) MeDramInitDone Complete. Checking for reset... ME UMA: UMA Enabled flag = 1 ME UMA: MeFwsts2 = 88110020. ME UMA: ME FW DID Ack requested to continue to POST. Temp Stack : BaseAddress=0xFEF88080 Length=0x27F80 Temp Heap : BaseAddress=0xFEF60100 Length=0xDED8 Total temporary memory: 327424 bytes. temporary memory stack ever used: 163712 bytes. temporary memory heap used: 57048 bytes. Old Stack size 163712, New stack size 262144 Stack Hob: BaseAddress=0x7F7FE000 Length=0x40000 Heap Offset = 0x7F722100 Stack Offset = 0x7F772000 Loading PEIM at 0x0007FBF3190 EntryPoint=0x0007FBF3270 Reinstall PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Reinstall PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A Reinstall PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Install PPI: F894643D-C449-42D1-8EA8-85BDD8C65BDE Loading PEIM at 0x0007FBE51A0 EntryPoint=0x0007FBE5270 FspInitPreMemEntryPoint() - Start Install PPI: 7408D748-FC8C-4EE6-9288-C4BEC092A410 Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE FspInitPreMemEntryPoint() - End Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: 7FBEBFF0 Memory Discovered Notify invoked ... Migrated MemoryInit UPD from 0xFEF0FCB0 to 0x7F853988 FspMemoryInitApi() - [Status: 0x00000000] - End CBMEM: IMD: root @ 7fbff000 254 entries. IMD: root @ 7fbfec00 62 entries. MTRR Range: Start=7ec00000 End=7f000000 (Size 400000) MTRR Range: Start=7f000000 End=7f800000 (Size 800000) MTRR Range: Start=7f800000 End=7fc00000 (Size 400000) MTRR Range: Start=ffe00000 End=0 (Size 200000) MTRR Range: Start=7fe00000 End=80000000 (Size 200000) CBFS: 'Master Header Locator' located CBFS at [20000:1fffc0) CBFS: Locating 'fallback/postcar' CBFS: Found @ offset 16500 size 3d54 Decompressing stage fallback/postcar @ 0x7f7cbfc0 (32304 bytes) Loading module at 7f7cc000 with entry 7f7cc000. filesize: 0x3b50 memsize: 0x7df0 Processing 106 relocs. Offset value of 0x7d7cc000 TempRamExitApi() - Begin MTRR programming: MSR_IA32_MTRR_FIX64K_00000 Msr 250 = 0606060606060606 MSR_IA32_MTRR_FIX16K_80000 Msr 258 = 0606060606060606 MSR_IA32_MTRR_FIX16K_A0000 Msr 259 = 0000000000000000 MSR_IA32_MTRR_FIX4K_C0000 Msr 268 = 0606060606060606 MSR_IA32_MTRR_FIX4K_C8000 Msr 269 = 0606060606060606 MSR_IA32_MTRR_FIX4K_D0000 Msr 26A = 0606060606060606 MSR_IA32_MTRR_FIX4K_D8000 Msr 26B = 0606060606060606 MSR_IA32_MTRR_FIX4K_E0000 Msr 26C = 0606060606060606 MSR_IA32_MTRR_FIX4K_E8000 Msr 26D = 0606060606060606 MSR_IA32_MTRR_FIX4K_F0000 Msr 26E = 0606060606060606 MSR_IA32_MTRR_FIX4K_F8000 Msr 26F = 0606060606060606 MSR_IA32_MTRR_PHYSBASE0 Msr 200 = 00000000FFE00005 MSR_IA32_MTRR_PHYSMASK0 Msr 201 = 0000007FFFE00800 MSR_IA32_MTRR_PHYSBASE1 Msr 202 = 0000000000000006 MSR_IA32_MTRR_PHYSMASK1 Msr 203 = 0000007F80000800 MSR_IA32_MTRR_PHYSBASE2 Msr 204 = 0000000100000006 MSR_IA32_MTRR_PHYSMASK2 Msr 205 = 0000007F00000800 MSR_IA32_MTRR_PHYSBASE3 Msr 206 = 0000000200000006 MSR_IA32_MTRR_PHYSMASK3 Msr 207 = 0000007F80000800 MSR_IA32_MTRR_PHYSBASE4 Msr 208 = 0000000000000000 MSR_IA32_MTRR_PHYSMASK4 Msr 209 = 0000000000000000 MSR_IA32_MTRR_PHYSBASE5 Msr 20A = 0000000000000000 MSR_IA32_MTRR_PHYSMASK5 Msr 20B = 0000000000000000 MSR_IA32_MTRR_PHYSBASE6 Msr 20C = 0000000000000000 MSR_IA32_MTRR_PHYSMASK6 Msr 20D = 0000000000000000 MSR_IA32_MTRR_PHYSBASE7 Msr 20E = 0000000000000000 MSR_IA32_MTRR_PHYSMASK7 Msr 20F = 0000000000000000 MSR_IA32_MTRR_PHYSBASE8 Msr 210 = 0000000000000000 MSR_IA32_MTRR_PHYSMASK8 Msr 211 = 0000000000000000 MSR_IA32_MTRR_PHYSBASE9 Msr 212 = 0000000000000000 MSR_IA32_MTRR_PHYSMASK9 Msr 213 = 0000000000000000 TempRamExitApi() - [Status: 0x00000000] - End coreboot-4.8.1-6794ce02d45273427c1c6675950c8468380c040a Wed Aug 15 07:13:10 UTC 2018 postcar starting... CBFS: 'Master Header Locator' located CBFS at [20000:1fffc0) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 7140 size eda4 Decompressing stage fallback/ramstage @ 0x7f789fc0 (231640 bytes) Loading module at 7f78a000 with entry 7f78a000. filesize: 0x1df18 memsize: 0x38898 Processing 2087 relocs. Offset value of 0x7f68a000 coreboot-4.8.1-6794ce02d45273427c1c6675950c8468380c040a Wed Aug 15 07:13:10 UTC 2018 ramstage starting... BS: BS_PRE_DEVICE times (us): entry 3 run 3 exit 0 CBFS: 'Master Header Locator' located CBFS at [20000:1fffc0) CBFS: Locating 'fsps.bin' CBFS: Found @ offset 1a2fc0 size 19000 CBFS: 'Master Header Locator' located CBFS at [20000:1fffc0) CBFS: Locating 'cpu_microcode_blob.bin' CBFS: Found @ offset fffc0 size 2800 FIA MUX Configuration in FSP HOB is: FiaMuxConfig.SkuNumLanesAllowed = 0xc FiaMuxConfig.FiaMuxConfig = 0xf800550000 FiaMuxConfig.FiaMuxConfig.SataLaneConfiguration = 0x51555555 FiaMuxConfig.FiaMuxConfig.PcieRootPortsConfiguration = 0x10 FiaMuxConfig.FiaMuxConfigRequest = 0xf800550000 FiaMuxConfig.FiaMuxConfigRequest.SataLaneConfiguration = 0x51555555 FiaMuxConfig.FiaMuxConfigRequest.PcieRootPortsConfiguration = 0x10 FiaMuxConfigStatus.FiaMuxConfigGetStatus = 0x0 FiaMuxConfigStatus.FiaMuxConfigSetStatus = 0x0 FiaMuxConfigStatus.FiaMuxConfigSetRequired = 0x0 SiliconInitApi() - Begin Installing FV at 0x7F737000-0x19000. Install PPI: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: FFF35B9C The 1th FV start address is 0x0007F737000, size is 0x00019000, handle is 0x7F737000 Memory Discovered Notify completed ... Loading PEIM at 0x0007FBE0198 EntryPoint=0x0007FBE0270 Install PPI: 0AE8CE5D-E448-4437-A8D7-EBF5F194F731 Install PPI: 1A36E4E7-FAB6-476A-8E75-695A0576FDD7 Loading PEIM at 0x0007FBD5000 EntryPoint=0x0007FBD5270 Updating Policies with Silicon Init UPD PCDs... UpdatePeiFiaMuxPolicy from PCD: SkuNumLanesAllowed: 0xC FiaMuxConfig.MuxConfiguration: 0xF800550000 FiaMuxConfig.SataLaneConfiguration: 0x51555555 FiaMuxConfig.PcieRootPortsConfiguration: 0x10 FiaMuxConfigRequest.MuxConfiguration: 0xF800550000 FiaMuxConfigRequest.SataLaneConfiguration: 0x51555555 FiaMuxConfigRequest.PcieRootPortsConfiguration: 0x10 Dump eMMC DLL registers: R_SCC_MEM_TX_CMD_DLL_CNTL, = 0x00000508 R_SCC_MEM_TX_DATA_DLL_CNTL1 = 0x00000C11 R_SCC_MEM_TX_DATA_DLL_CNTL2 = 0x1C2A2A2A R_SCC_MEM_RX_CMD_DATA_DLL_CNTL1 = 0x00191E27 R_SCC_MEM_RX_STROBE_DLL_CNTL = 0x00000A0A R_SCC_MEM_RX_CMD_DATA_DLL_CNTL2 = 0x00010013 R_SCC_MEM_MASTER_DLL_SW_CNTL = 0x00800001 Loading PEIM at 0x0007FBAE000 EntryPoint=0x0007FBAE270 SiInit () - Start Locate PcieIpGlobalPolicy Start PcieIpInit Phase0 PcieIpInit Start PcieIpInitCluster Start, Opcode <> Configure RC0 : bifurcation code 4 Cluster B4 Strap F hide E Configure RC1 : bifurcation code 3 Cluster B3 Strap 1 hide E PSF PcieIpBifurcationPSF 4 soc.psf.psf_1_rc_owner_rs0= 0x40101 PcieIpInitCluster End RPBase 0 -> 0xFFFFFFFF, port 0, type: 0, bus 0, device 9 RPBase 1 -> 0xFFFFFFFF, port 1, type: 0, bus 0, device 10 RPBase 2 -> 0xFFFFFFFF, port 2, type: 0, bus 0, device 11 RPBase 3 -> 0xFFFFFFFF, port 3, type: 0, bus 0, device 12 RPBase 4 -> 0xE0070000, port 4, type: 0, bus 0, device 14 RPBase 5 -> 0xFFFFFFFF, port 5, type: 0, bus 0, device 15 RPBase 6 -> 0xFFFFFFFF, port 6, type: 0, bus 0, device 16 RPBase 7 -> 0xFFFFFFFF, port 7, type: 0, bus 0, device 17 RPBase 8 -> 0xE0030000, port 8, type: 1, bus 0, device 6 RPBase 9 -> 0xE00B0000, port 9, type: 1, bus 0, device 22 RPBase 10 -> 0xE00B8000, port 10, type: 1, bus 0, device 23 PCIE GEN3 configuration sequence, - begin for rp 4 0x000BD0 0 R_PCIE_EQEVALCTL2 BA0 R_PCIE_EQEVALCTL3 33F00802 R_PCIE_EQEVALCTL4 4B30004 R_PCIE_EQEVALCTL5 3A801013 R_PCIE_EQEVALCTL6 4904623 R_PCIE_EQEVALCTL7 20 fomincctl 4FFFF bar FE600004 - command 7 device E, offset FE603A00 data B506 device E, offset FE603A04 data B448 device E, offset FE603A08 data B4CA device E, offset FE603A0C data B50C device E, offset FE603A10 data B44E device E, offset FE603A14 data 34C6 device E, offset FE603A18 data 34C6 device E, offset FE603A1C data 34C6 device E, offset FE603A20 data 34C6 device E, offset FE603A24 data 34C6 device E, offset FE603A28 data 34C6 device E, offset FE603A2C data 34C6 base extmem R_PCIE_GEN3FARTXCOEFFx: FE6035C0 data 0 base extmem R_PCIE_GEN3FARTXCOEFFx: FE6035C4 data 0 base extmem R_PCIE_GEN3FARTXCOEFFx: FE6035C8 data 0 base extmem R_PCIE_GEN3FARTXCOEFFx: FE6035CC data 0 base extmem R_PCIE_GEN3FARTXCOEFFx: FE6035D0 data 0 base extmem R_PCIE_GEN3FARTXCOEFFx: FE6035D4 data 0 base extmem R_PCIE_GEN3FARTXCOEFFx: FE6035D8 data 0 base extmem R_PCIE_GEN3FARTXCOEFFx: FE6035DC data 0 PCIE GEN3 configuration sequence - end PcieIpConfigureLinkSequence end PcieIpInit End FiaMuxConfigMessaging state: 1 PeiFiaMuxConfigInit Start PeiFiaMuxConfigInit End HsuartIpInit Start HsuartIpInit End PeiIqatIpInit Start Enabled IQAT device!! Register PPI Notify: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793 PeiIqatIpInit End SetActiveCores: ActiveCores:4 SetActiveCores: ExistingCores:4 SetActiveCores: Initial CoreDisableMask:0 ActiveCoresMask:1144 SetActiveCores: ActiveCores:4 Setup option 'Active Processor Cores' is 0. All existing cores are active Set PCH_PCR_CORE_DISABLE_MASK_MCHBAR = 0000EEBB SetActiveCores: New # of ActiveCores:4 ActiveCoresSetupValue:4 SetActiveCores: Requesting a Reset to make changes have effect SetActiveCores: Change detected! BYPASS ColdReset - ActiveCoresSetupValue:4 CoreDisableMask:EEBB PchInit - Start Install PPI: 61C68702-4D7E-4F43-8DEF-A74305CE74C5 Register PPI Notify: 9F685891-4E6F-445C-BB9E-E57A28FA53A0 GpioPad (Group=102, Pad=15) not owned by HOST, skip it. GpioPad (Group=102, Pad=16) not owned by HOST, skip it. GpioPad (Group=102, Pad=27) not owned by HOST, skip it. GpioPad (Group=102, Pad=28) not owned by HOST, skip it. GpioPad (Group=102, Pad=30) not owned by HOST, skip it. ------------------ IRQ Usage ------------------ IRQxxx USED IRQ000 0 IRQ001 0 IRQ002 0 IRQ003 0 IRQ004 0 IRQ005 0 IRQ006 0 IRQ007 0 IRQ008 0 IRQ009 0 IRQ010 0 IRQ011 0 IRQ012 0 IRQ013 0 IRQ014 0 IRQ015 0 IRQ016 1 IRQ017 1 IRQ018 1 IRQ019 1 IRQ020 1 IRQ021 1 IRQ022 1 IRQ023 1 IRQ024 0 IRQ025 0 IRQ026 0 IRQ027 0 IRQ028 0 IRQ029 0 IRQ030 0 IRQ031 0 IRQ032 0 IRQ033 0 IRQ034 0 IRQ035 0 IRQ036 0 IRQ037 0 IRQ038 0 IRQ039 0 IRQ040 0 IRQ041 0 IRQ042 0 IRQ043 0 IRQ044 0 IRQ045 0 IRQ046 0 IRQ047 0 IRQ048 0 IRQ049 0 IRQ050 0 IRQ051 0 IRQ052 0 IRQ053 0 IRQ054 0 IRQ055 0 IRQ056 0 IRQ057 0 IRQ058 0 IRQ059 0 IRQ060 0 IRQ061 0 IRQ062 0 IRQ063 0 IRQ064 0 IRQ065 0 IRQ066 0 IRQ067 0 IRQ068 0 IRQ069 0 IRQ070 0 IRQ071 0 IRQ072 0 IRQ073 0 IRQ074 0 IRQ075 0 IRQ076 0 IRQ077 0 IRQ078 0 IRQ079 0 IRQ080 0 IRQ081 0 IRQ082 0 IRQ083 0 IRQ084 0 IRQ085 0 IRQ086 0 IRQ087 0 IRQ088 0 IRQ089 0 IRQ090 0 IRQ091 0 IRQ092 0 IRQ093 0 IRQ094 0 IRQ095 0 IRQ096 0 IRQ097 0 IRQ098 0 IRQ099 0 IRQ100 0 IRQ101 0 IRQ102 0 IRQ103 0 IRQ104 0 IRQ105 0 IRQ106 0 IRQ107 0 IRQ108 0 IRQ109 0 IRQ110 0 IRQ111 0 IRQ112 0 IRQ113 0 IRQ114 0 IRQ115 0 IRQ116 0 IRQ117 0 IRQ118 0 IRQ119 0 IRQ120 0 IRQ121 0 IRQ122 0 IRQ123 0 IRQ124 0 IRQ125 0 IRQ126 0 ConfigureXhci () - Start PchUsbPei XHCI Capability Pointer = 0xFE608000 ConfigureXhci () - End PeiMiscIpInit Start Enabled EMMC device!! Enabled GbE0 device!! Enabled GbE1 device!! PeiMiscIpInit End PchPmInit : Entry PCH Revision ID: 0x11 PM_CFG = 0xFE000018 Value = 0x2180002C PchPmInit : Exit PchInit - End PcieIpInit Phase1 PcieIpInit Start PcieIpLaneEQPresetFeature bifurcation 4 RP 0 base memory: FFFFFFFF PcieIpLaneEQPresetFeature bifurcationt 3 RP 4 base memory: E0070000 offset 20C offset 20E offset 210 offset 212 RP 6 base memory: FFFFFFFF Enabling Clock Gating settings PcieIpInitSwzCtl start Before link trainning, Opcode <> Disable PCIE cluster 4!! First PCIE cluster was disabled!! Enabled PCIE cluster 5!! Second PCIE cluster was enabled!! FIA & PCIE are in sync Selected Gen speed 3 RP 4 : 0,14,0 Starting link training for PCie RP 4 : 0,14,0 PcieIpInitCluster End B RTRYCTL 0 A RTRYCTL 3 Root port replay timer 0 -> 3 B RTRYCTL 3 A RTRYCTL 3 Root port replay timer 4 -> 3 root port lock 4 -> 0 aspm value 2 B PCIE ASPM LINK CTL 0 A PCIE ASPM LINK CTL 2 B PCIE ASPM LINK CAP 800 A PCIE ASPM LINK CAP 800 PeiPcieDevCtlInit Start PCIE_DCTL = 0x5120 PeiPcieDevCtlInit End PeiPcieDevCtl2Init Start PCIE_DCTL2 = 0x0006 PeiPcieDevCtlInit End PEI PcieIp Link Ctl Start PCIE_LCTL.ExtSynch.Disabled :: PCIE_LCTL = 0x2 PEI PcieIpInit End No Link Reversal : Addr E0070A30 PCIE DeEmphasis = -6dB This root port 4 is not active with HotPlug PcieIpInit End VTd enabled VtdBase = FED90000 [ME] Disabling ME functions: 1 (HECI-2) 4 (HECI-3) 2 (IDE-R) 3 (KT) [ME] Enabling HECI0 [ME] Disabling HECI1 [ME] Disabling HECI4 [ME] Disabling HECI2 [ME] Disabling HECI3 PmcStPgConfig : Entry ST_PG_FDIS_PMC_1 = 0x00000014 PmcStPgConfig : Exit Register PPI Notify: 605EA650-C65C-42E1-BA80-91A52AB618C6 SiInit () - End Notify: PPI Guid: 9F685891-4E6F-445C-BB9E-E57A28FA53A0, Peim notify entry point: 7FBAFC0D PchHsioOnHeciPpi start (Hsio) ME Reported CRC=0x12FD (Hsio) BIOS Hsio CRC=0x12FD Loading PEIM at 0x0007FBA3000 EntryPoint=0x0007FBA3270 SaInitDxe Start ------------------------ DXE SA Platform Policy Dump Start ----------------- ------------------------ SA PLATFORM CONFIGURATION Begin--------------- SA Clock Gating : 0 MSI Redirection Algorithm : 0 ------------------------ SA PLATFORM CONFIGURATION End--------------- ------------------------ VTD PLATFORM CONFIGURATION Begin--------------- Vtd Enable : 1 Vtd BaseAddress : FED90000 Vtd RmrrUsbBaseAddress : 3E2E0000 Vtd RmrrUsbLimitAddress : 3E2FFFFF Vtd Interrupt remapping : 1 ------------------------ VTD PLATFORM CONFIGURATION End--------------- ------------------------ SA SV MEMORY CONFIGURATION Begin--------------- EnableTagec : 0 ReserveMem : 0 ReserveStartAddr : 0x00000000 ------------------------ SA SV MEMORY CONFIGURATION End--------------- ------------------------ DXE SA Platform Policy Dump End ----------------- Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B SaInitDxe End Loading PEIM at 0x0007FB94000 EntryPoint=0x0007FB94270 Fsp PchInitEntryPoint() Start Common PchInitEntryPoint() Start ConfigureWakeEvents : Entry Enable RTC wake GPE0_STS_127_96 = 0x0000188C Value = 0x00000080 PM1_EN_STS = 0x00001800 Value = 0x04008101 ROW: ROW was not enabled GPE0_EN_127_96 = 0x0000189C Value = 0x00002800 PM_CFG2 = 0xFE00003C Value = 0x00002000 ConfigureWakeEvents : Exit Common PchInitEntryPoint() End Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B Fsp PchInitEntryPoint() End Loading PEIM at 0x0007FB87000 EntryPoint=0x0007FB87270 Install PPI: 3FDDA605-A76E-4F46-AD29-12F4531B3D08 Microcode Base: 0xFFF20040 Microcode Size: 0xFF80 Detected 4 CPU threads Loading PEIM at 0x0007FB6C000 EntryPoint=0x0007FB6C270 The entry of FspNotificationPeim Reinstall PPI: 0AE8CE5D-E448-4437-A8D7-EBF5F194F731 DXE IPL Entry FSP HOB is located at 0x7F83E000 Install PPI: 605EA650-C65C-42E1-BA80-91A52AB618C6 Notify: PPI Guid: 605EA650-C65C-42E1-BA80-91A52AB618C6, Peim notify entry point: 7FBAE2A2 SiInitOnEndOfPei - Start PchOnEndOfPei after memory PEI module - Start UsbEndOfInit : Entry XHCC2 = 0xE00A8044 Value = 0x83CFC68F UsbEndOfInit : Exit (WDT) EndOfPeiCallback (WDT) BootMode 0, Hob, active 0, ToV 0 PchTraceHubOnEndOfPei : Entry TraceHub Device not present PchOnEndOfPei after memory PEI module - End PmcStPgLock : Entry ST_PG_FDIS_PMC_1 = 0x80000014 PmcStPgLock : Exit SiInitOnEndOfPei - End FSP is waiting for NOTIFY FspSiliconInitApi() - [Status: 0x00000000] - End CBMEM entry for DIMM info: 0x7fbfea00 WEAK: src/soc/intel/denverton_ns/hob_mem.c/mainboard_add_dimm_info called 1 DIMMs found BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 2712002 exit 0 Enumerating buses... CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/1980] enabled PCI: 00:04.0 [8086/19a1] enabled PCI: 00:05.0 [8086/19a2] enabled PCI: 00:06.0 subordinate bus PCI Express PCI: 00:06.0 [8086/19a3] enabled PCI: Static device PCI: 00:09.0 not found, disabling it. PCI: 00:0e.0 subordinate bus PCI Express PCI: 00:0e.0 [8086/19a8] enabled PCI: Static device PCI: 00:10.0 not found, disabling it. PCI: 00:12.0 [8086/19ac] enabled PCI: 00:14.0 [8086/19c2] enabled PCI: 00:15.0 subsystem <- 8086/19d0 PCI: 00:15.0 cmd <- 00 PCI: 00:15.0 [8086/19d0] enabled PCI: 00:16.0 subordinate bus PCI Express PCI: 00:16.0 [8086/19d1] enabled PCI: 00:17.0 subordinate bus PCI Express PCI: 00:17.0 [8086/19d2] enabled PCI: 00:18.0 [8086/19d3] enabled PCI: 00:1a.0 [8086/19d8] enabled PCI: 00:1a.1 [8086/19d8] enabled PCI: 00:1a.2 [8086/19d8] enabled PCI: 00:1c.0 [8086/19db] enabled PCI: 00:1f.0 [8086/19dc] enabled PCI: 00:1f.2 [8086/19de] enabled PCI: 00:1f.4 [8086/19df] enabled PCI: 00:1f.5 [8086/19e0] enabled PCI: pci_scan_bus for bus 01 PCI: 01:00.0 [8086/19e2] enabled Failed to enable LTR for dev = PCI: 01:00.0 scan_bus: scanning of bus PCI: 00:06.0 took 9943 usecs PCI: pci_scan_bus for bus 02 scan_bus: scanning of bus PCI: 00:0e.0 took 2775 usecs PCI: pci_scan_bus for bus 03 PCI: 03:00.0 [8086/15ce] enabled PCI: 03:00.1 [8086/15ce] enabled Failed to enable LTR for dev = PCI: 03:00.0 Failed to enable LTR for dev = PCI: 03:00.1 scan_bus: scanning of bus PCI: 00:16.0 took 17109 usecs PCI: pci_scan_bus for bus 04 PCI: 04:00.0 [8086/15c7] enabled PCI: 04:00.1 [8086/15c7] enabled scan_bus: scanning of bus PCI: 00:17.0 took 9030 usecs scan_bus: scanning of bus PCI: 00:1f.0 took 3 usecs scan_bus: scanning of bus DOMAIN: 0000 took 156538 usecs scan_bus: scanning of bus Root Device took 165998 usecs done FMAP: Found "FLASH" version 1.1 at 0. FMAP: base = ffe00000 size = 200000 #areas = 4 FMAP: area RW_MRC_CACHE found @ 10000 (65536 bytes) MRC: Checking cached data update for 'RW_MRC_CACHE'. SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000 SF size 0x1000000 does not correspond to CONFIG_ROM_SIZE 0x200000!! MRC: no data in 'RW_MRC_CACHE' MRC: cache data 'RW_MRC_CACHE' needs update. SPI Transaction Error at Flash Offset 10000 HSFSTS = 0x01046003 REGF metadata allocation failed: 1949 data blocks 4096 total blocks BS: BS_DEV_ENUMERATE times (us): entry 0 run 173833 exit 49899 Allocating resources... Reading resources... mc_add_fixed_mmio_resources: Adding PCIEXBAR @ 60 0xe0000000-0xefffffff. mc_add_fixed_mmio_resources: Adding MCHBAR @ 48 0xfed10000-0xfed17fff. MC MAP: TOUUD: 0x280000000 MC MAP: TOLUD: 0x80000000 MC MAP: TSEGMB: 0x7fe00000 SMM memory location: 0x7fe00000 SMM memory size: 0x200000 Adding P2SB PCR config space BAR 0xfd000000-0xfe000000. Adding PMC PWRM config space BAR 0xfe000000-0xfe010000. Done reading resources. Setting resources... PCI: 00:06.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:06.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:06.0 20 <- [0x00dfb00000 - 0x00dfbfffff] size 0x00100000 gran 0x14 bus 01 mem PCI: 01:00.0 18 <- [0x00dfb00000 - 0x00dfb3ffff] size 0x00040000 gran 0x12 mem64 PCI: 01:00.0 20 <- [0x00dfb40000 - 0x00dfb7ffff] size 0x00040000 gran 0x12 mem64 PCI: 00:0e.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io PCI: 00:0e.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:0e.0 20 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 02 mem PCI: 00:0e.0 10 <- [0x00dfe00000 - 0x00dfe1ffff] size 0x00020000 gran 0x11 mem64 PCI: 00:12.0 10 <- [0x00dfe3b000 - 0x00dfe3b3ff] size 0x00000400 gran 0x0a mem64 PCI: 00:14.0 10 <- [0x00dfe34000 - 0x00dfe35fff] size 0x00002000 gran 0x0d mem PCI: 00:14.0 14 <- [0x00dfe3c000 - 0x00dfe3c0ff] size 0x00000100 gran 0x08 mem PCI: 00:14.0 18 <- [0x0000001c40 - 0x0000001c47] size 0x00000008 gran 0x03 io PCI: 00:14.0 1c <- [0x0000001c48 - 0x0000001c4b] size 0x00000004 gran 0x02 io PCI: 00:14.0 20 <- [0x0000001c00 - 0x0000001c1f] size 0x00000020 gran 0x05 io PCI: 00:14.0 24 <- [0x00dfe3a000 - 0x00dfe3a7ff] size 0x00000800 gran 0x0b mem PCI: 00:15.0 10 <- [0x00dfe20000 - 0x00dfe2ffff] size 0x00010000 gran 0x10 mem64 PCI: 00:16.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io PCI: 00:16.0 24 <- [0x00df000000 - 0x00df4fffff] size 0x00500000 gran 0x14 bus 03 prefmem PCI: 00:16.0 20 <- [0x00dfc00000 - 0x00dfcfffff] size 0x00100000 gran 0x14 bus 03 mem PCI: 03:00.0 10 <- [0x00df000000 - 0x00df1fffff] size 0x00200000 gran 0x15 prefmem64 PCI: 03:00.0 20 <- [0x00df400000 - 0x00df403fff] size 0x00004000 gran 0x0e prefmem64 PCI: 03:00.0 30 <- [0x00dfc00000 - 0x00dfc7ffff] size 0x00080000 gran 0x13 romem PCI: 03:00.1 10 <- [0x00df200000 - 0x00df3fffff] size 0x00200000 gran 0x15 prefmem64 PCI: 03:00.1 20 <- [0x00df404000 - 0x00df407fff] size 0x00004000 gran 0x0e prefmem64 PCI: 03:00.1 30 <- [0x00dfc80000 - 0x00dfcfffff] size 0x00080000 gran 0x13 romem PCI: 00:17.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io PCI: 00:17.0 24 <- [0x00df600000 - 0x00dfafffff] size 0x00500000 gran 0x14 bus 04 prefmem PCI: 00:17.0 20 <- [0x00dfd00000 - 0x00dfdfffff] size 0x00100000 gran 0x14 bus 04 mem PCI: 04:00.0 10 <- [0x00df600000 - 0x00df7fffff] size 0x00200000 gran 0x15 prefmem64 PCI: 04:00.0 20 <- [0x00dfa00000 - 0x00dfa03fff] size 0x00004000 gran 0x0e prefmem64 PCI: 04:00.0 30 <- [0x00dfd00000 - 0x00dfd7ffff] size 0x00080000 gran 0x13 romem PCI: 04:00.1 10 <- [0x00df800000 - 0x00df9fffff] size 0x00200000 gran 0x15 prefmem64 PCI: 04:00.1 20 <- [0x00dfa04000 - 0x00dfa07fff] size 0x00004000 gran 0x0e prefmem64 PCI: 04:00.1 30 <- [0x00dfd80000 - 0x00dfdfffff] size 0x00080000 gran 0x13 romem PCI: 00:18.0 10 <- [0x00dfe36000 - 0x00dfe36fff] size 0x00001000 gran 0x0c mem64 PCI: 00:1c.0 10 <- [0x00dfe37000 - 0x00dfe37fff] size 0x00001000 gran 0x0c mem64 PCI: 00:1c.0 18 <- [0x00dfe38000 - 0x00dfe38fff] size 0x00001000 gran 0x0c mem64 PCI: 00:1f.2 10 <- [0x00dfe30000 - 0x00dfe33fff] size 0x00004000 gran 0x0e mem PCI: 00:1f.4 10 <- [0x00dfe3d000 - 0x00dfe3d0ff] size 0x00000100 gran 0x08 mem64 PCI: 00:1f.4 20 <- [0x0000001c20 - 0x0000001c3f] size 0x00000020 gran 0x05 io PCI: 00:1f.5 10 <- [0x00dfe39000 - 0x00dfe39fff] size 0x00001000 gran 0x0c mem Done setting resources. Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 0 run 363368 exit 0 NotifyPhaseApi() - Begin [Phase: 00000020] FSP Post PCI Enumeration ... Install PPI: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793 Notify: PPI Guid: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793, Peim notify entry point: 7FBB369C ConfigureIqatUncorrectableErrorWA () Start, boot mode 0x0.. QatBusNum: 0x1 QatMemBase: 0xE0100000 Vrp2MemBase: 0xE0030000 Vrp2PciCmd: 0x0 QatPciCmd: 0x0 R_IQAT_PFIEERRUNCSTSR: 0xC00 Now R_IQAT_PFIEERRUNCSTSR: 0x0 R_IQAT_PPAERUCS: 0x400000 Now R_IQAT_PPAERUCS: 0x0 R_IQAT_PPAERCS: 0x0 ConfigureIqatUncorrectableErrorWA() End ConfigureIqatSecureRam() Start SetupImrRegion called..(0x7FD00000, 0x80000) SetupImrRegion Low = 0x1FF400 High = 0x1FFFFE00.. MchBar: 0xFED10000 MchBar: LOW read [0xFED16870] = 0x0 MchBar: LOW write [0xFED16870] = 0x801FF400 MchBar: LOW read [0xFED16870] = 0x801FF400 MchBar: HIGH read [0xFED16874] = 0x0 MchBar: HIGH write [0xFED16874] = 0x1FFFFE00 MchBar: HIGH read [0xFED16874] = 0x1FFFFE00 Allowing nCPM to READ / WRITE only MchBar: RAC read [0xFED16880] = 0x0 MchBar: RAC write [0xFED16880] = 0x4000000 MchBar: RAC read [0xFED16880] = 0x4000000 MchBar: WAC read [0xFED16888] = 0x0 MchBar: WAC write [0xFED16888] = 0x4000000 MchBar: RAC read [0xFED16888] = 0x4000000 QatBusNum: 0x1 Vrp2PciCmd: 0x0 QatPmiscBar: 0xDFB00000 QatPciCmd: 0x0 RamBaseAddrHi: 0x20000 RamBaseAddrLo: 0x0 RamBaseAddrHi: 0x20000 RamBaseAddrLo: 0x7FD00000 ConfigureIqatSecureRam() End NotifyPhaseApi() - End [Status: 0x00000000] Enabling resources... PCI: 00:00.0 subsystem <- 8086/1980 PCI: 00:00.0 cmd <- 07 PCI: 00:04.0 subsystem <- 8086/19a1 PCI: 00:04.0 cmd <- 00 PCI: 00:05.0 subsystem <- 8086/19a2 PCI: 00:05.0 cmd <- 04 PCI: 00:06.0 bridge ctrl <- 0003 PCI: 00:06.0 cmd <- 06 PCI: 00:0e.0 bridge ctrl <- 0003 PCI: 00:0e.0 cmd <- 02 PCI: 00:12.0 subsystem <- 8086/19ac PCI: 00:12.0 cmd <- 06 PCI: 00:14.0 subsystem <- 8086/19c2 PCI: 00:14.0 cmd <- 43 PCI: 00:15.0 subsystem <- 8086/19d0 PCI: 00:15.0 cmd <- 02 PCI: 00:16.0 bridge ctrl <- 0003 PCI: 00:16.0 cmd <- 06 PCI: 00:17.0 bridge ctrl <- 0003 PCI: 00:17.0 cmd <- 06 PCI: 00:18.0 subsystem <- 8086/19d3 PCI: 00:18.0 cmd <- 06 PCI: 00:1a.0 cmd <- 05 PCI: 00:1a.1 cmd <- 05 PCI: 00:1a.2 cmd <- 05 PCI: 00:1c.0 subsystem <- 8086/19db PCI: 00:1c.0 cmd <- 06 PCI: 00:1f.0 subsystem <- 8086/19dc PCI: 00:1f.0 cmd <- 107 PCI: 00:1f.2 subsystem <- 8086/19de PCI: 00:1f.2 cmd <- 06 PCI: 00:1f.4 subsystem <- 8086/19df PCI: 00:1f.4 cmd <- 03 PCI: 00:1f.5 subsystem <- 8086/19e0 PCI: 00:1f.5 cmd <- 402 PCI: 01:00.0 cmd <- 02 PCI: 03:00.0 cmd <- 02 PCI: 03:00.1 cmd <- 02 PCI: 04:00.0 cmd <- 02 PCI: 04:00.1 cmd <- 02 done. BS: BS_DEV_ENABLE times (us): entry 341874 run 109375 exit 0 Initializing devices... Root Device init ... Root Device init finished in 2052 usecs CPU_CLUSTER: 0 init ... MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x000000007fc00000 size 0x7fb40000 type 6 0x000000007fc00000 - 0x000000007fe00000 size 0x00200000 type 0 0x000000007fe00000 - 0x0000000080000000 size 0x00200000 type 6 0x0000000080000000 - 0x0000000100000000 size 0x80000000 type 0 0x0000000100000000 - 0x0000000280000000 size 0x180000000 type 6 MTRR: Fixed MSR 0x250 0x0606060606060606 MTRR: Fixed MSR 0x258 0x0606060606060606 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 MTRR: Fixed MSR 0x26a 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 MTRR: Fixed MSR 0x26c 0x0606060606060606 MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 CPU physical address size: 39 bits MTRR: default type WB/UC MTRR counts: 2/12. MTRR: WB selected as default type. MTRR: 0 base 0x000000007fc00000 mask 0x0000007fffe00000 type 0 MTRR: 1 base 0x0000000080000000 mask 0x0000007f80000000 type 0 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Number of Active Cores: 4 of 4 total. Will perform SMM setup. CPU: Intel(R) Atom(TM) CPU C3538 @ 2.10GHz. Loading module at 00030000 with entry 00030000. filesize: 0x130 memsize: 0x130 Processing 16 relocs. Offset value of 0x00030000 Attempting to start 3 APs Waiting for 10ms after sending INIT. Waiting for 1st SIPI to complete...AP: slot 1 apic_id 18. done. AP: slot 2 apic_id c. AP: slot 3 apic_id 10. Waiting for 2nd SIPI to complete...done. Loading module at 00038000 with entry 00038000. filesize: 0x1b0 memsize: 0x1b0 Processing 12 relocs. Offset value of 0x00038000 SMM Module: stub loaded at 00038000. Will call 7f7996bf(00000000) Installing SMM handler to 0x7fe00000 Loading module at 7fe10000 with entry 7fe10046. filesize: 0x4c8 memsize: 0x44e0 Processing 22 relocs. Offset value of 0x7fe10000 Loading module at 7fe08000 with entry 7fe08000. filesize: 0x1b0 memsize: 0x1b0 Processing 12 relocs. Offset value of 0x7fe08000 SMM Module: placing jmp sequence at 7fe07c00 rel16 0x03fd SMM Module: placing jmp sequence at 7fe07800 rel16 0x07fd SMM Module: placing jmp sequence at 7fe07400 rel16 0x0bfd SMM Module: stub loaded at 7fe08000. Will call 7fe10046(00000000) Initializing Southbridge SMI...SMI_STS: PERIODIC PM1 WAK PWRBTN TMROF New SMBASE 0x7fe00000 Relocation complete. New SMBASE 0x7fdff800 Relocation complete. New SMBASE 0x7fdff400 Relocation complete. New SMBASE 0x7fdffc00 Relocation complete. Initializing CPU #0 CPU: vendor Intel device 506f1 CPU: family 06, model 5f, stepping 01 Init Denverton-NS SoC cores. Turbo is unavailable CPU #0 initialized Initializing CPU #2 Initializing CPU #3 CPU: vendor Intel device 506f1 CPU: family 06, model 5f, stepping 01 CPU: vendor Intel device 506f1 CPU: family 06, model 5f, stepping 01 Init Denverton-NS SoC cores. Init Denverton-NS SoC cores. CPU #2 initialized Initializing CPU #1 CPU #3 initialized CPU: vendor Intel device 506f1 CPU: family 06, model 5f, stepping 01 Init Denverton-NS SoC cores. CPU #1 initialized bsp_do_flight_plan done after 145 msecs. cpu: frequency set to 2100 Enabling SMIs. CPU_CLUSTER: 0 init finished in 324161 usecs PCI: 00:00.0 init ... Set BIOS_RESET_CPL PCI: 00:00.0 init finished in 4225 usecs PCI: 00:04.0 init ... PCI: 00:04.0 init finished in 2141 usecs PCI: 00:05.0 init ... PCI: 00:05.0 init finished in 2140 usecs PCI: 00:12.0 init ... PCI: 00:12.0 init finished in 2141 usecs PCI: 00:14.0 init ... SATA: Initializing... SATA: Controller in AHCI mode. ABAR: DFE3A000 PCI: 00:14.0 init finished in 8734 usecs PCI: 00:15.0 init ... pch: usb_xhci_init PCI: 00:15.0 init finished in 4021 usecs PCI: 00:18.0 init ... PCI: 00:18.0 init finished in 2139 usecs PCI: 00:1a.0 init ... PCI: 00:1a.0 init finished in 2140 usecs PCI: 00:1a.1 init ... PCI: 00:1a.1 init finished in 2140 usecs PCI: 00:1a.2 init ... PCI: 00:1a.2 init finished in 2140 usecs PCI: 00:1c.0 init ... PCI: 00:1c.0 init finished in 2141 usecs PCI: 00:1f.0 init ... pch: lpc_init IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x04 IOAPIC: ID = 0x01 PCI: 00:1f.0 init finished in 13539 usecs PCI: 00:1f.2 init ... pch: pmc_init Disabling ACPI via APMC: done. PCI: 00:1f.2 init finished in 6759 usecs PCI: 00:1f.4 init ... PCI: 00:1f.4 init finished in 2141 usecs PCI: 00:1f.5 init ... PCI: 00:1f.5 init finished in 2140 usecs PCI: 01:00.0 init ... PCI: 01:00.0 init finished in 2140 usecs PCI: 03:00.0 init ... PCI: 03:00.0 init finished in 2140 usecs PCI: 03:00.1 init ... PCI: 03:00.1 init finished in 2141 usecs PCI: 04:00.0 init ... PCI: 04:00.0 init finished in 2140 usecs PCI: 04:00.1 init ... PCI: 04:00.1 init finished in 2140 usecs Devices initialized BS: BS_DEV_INIT times (us): entry 0 run 483684 exit 0 Finalize devices... Devices finalized BS: BS_POST_DEVICE times (us): entry 0 run 3763 exit 0 BS: BS_OS_RESUME_CHECK times (us): entry 0 run 3 exit 0 CBFS: 'Master Header Locator' located CBFS at [20000:1fffc0) CBFS: Locating 'fallback/dsdt.aml' CBFS: Found @ offset 1a2c0 size 1f9f CBFS: 'Master Header Locator' located CBFS at [20000:1fffc0) CBFS: Locating 'fallback/slic' CBFS: 'fallback/slic' not found. ACPI: Writing ACPI tables at 7f6f2000. ACPI: * FACS ACPI: * DSDT ACPI: * FADT SCI is IRQ9 ACPI: added table 1/32, length now 40 ACPI: * SSDT Number of Active Cores: 4 of 4 total. ACPI: added table 2/32, length now 44 ACPI: * MCFG ACPI: added table 3/32, length now 48 ACPI: * TCPA TCPA log created at 7f6e2000 ACPI: added table 4/32, length now 52 ACPI: * MADT SCI is IRQ9 ACPI: added table 5/32, length now 56 current = 7f6f44f0 ACPI: * HPET ACPI: added table 6/32, length now 60 ACPI: * SSDT2 not generated. current = 7f6f4530 ACPI: done. ACPI tables: 9520 bytes. smbios_write_tables: 7f6e1000 Create SMBIOS type 17 Root Device (Intel Harcuvar CRB) CPU_CLUSTER: 0 (Intel Denverton-NS SOC) APIC: 00 (Intel Denverton-NS SOC) DOMAIN: 0000 (Intel Denverton-NS SOC) PCI: 00:00.0 (Intel Denverton-NS SOC) PCI: 00:04.0 (Intel Denverton-NS SOC) PCI: 00:05.0 (Intel Denverton-NS SOC) PCI: 00:06.0 (Intel Denverton-NS SOC) PCI: 00:09.0 (Intel Denverton-NS SOC) PCI: 00:0e.0 (Intel Denverton-NS SOC) PCI: 00:10.0 (Intel Denverton-NS SOC) PCI: 00:12.0 (Intel Denverton-NS SOC) PCI: 00:14.0 (Intel Denverton-NS SOC) PCI: 00:15.0 (Intel Denverton-NS SOC) PCI: 00:16.0 (Intel Denverton-NS SOC) PCI: 00:17.0 (Intel Denverton-NS SOC) PCI: 00:18.0 (Intel Denverton-NS SOC) PCI: 00:1a.0 (Intel Denverton-NS SOC) PCI: 00:1a.1 (Intel Denverton-NS SOC) PCI: 00:1a.2 (Intel Denverton-NS SOC) PCI: 00:1c.0 (Intel Denverton-NS SOC) PCI: 00:1f.0 (Intel Denverton-NS SOC) PCI: 00:1f.2 (Intel Denverton-NS SOC) PCI: 00:1f.4 (Intel Denverton-NS SOC) PCI: 00:1f.5 (Intel Denverton-NS SOC) PCI: 01:00.0 (unknown) PCI: 03:00.0 (unknown) PCI: 03:00.1 (unknown) PCI: 04:00.0 (unknown) PCI: 04:00.1 (unknown) APIC: 04 (unknown) APIC: 18 (unknown) APIC: 0c (unknown) APIC: 10 (unknown) SMBIOS tables: 479 bytes. Writing table forward entry at 0x00000500 Wrote coreboot table at: 00000500, 0x10 bytes, checksum 206d Writing coreboot table at 0x7f716000 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000a0000-00000000000fffff: RESERVED 3. 0000000000100000-000000007f6e0fff: RAM 4. 000000007f6e1000-000000007f789fff: CONFIGURATION TABLES 5. 000000007f78a000-000000007f7c2fff: RAMSTAGE 6. 000000007f7c3000-000000007fbfffff: CONFIGURATION TABLES 7. 000000007fc00000-000000007fffffff: RESERVED 8. 00000000e0000000-00000000efffffff: RESERVED 9. 00000000fed10000-00000000fed17fff: RESERVED 10. 0000000100000000-000000027fffffff: RAM Board ID: 82 CBFS: 'Master Header Locator' located CBFS at [20000:1fffc0) Wrote coreboot table at: 7f716000, 0x460 bytes, checksum 208d coreboot table: 1144 bytes. IMD ROOT 0. 7fbff000 00001000 IMD SMALL 1. 7fbfe000 00001000 FSP MEMORY 2. 7f7fe000 00400000 CONSOLE 3. 7f7de000 00020000 TIME STAMP 4. 7f7dd000 00000910 MRC DATA 5. 7f7d5000 000079d0 ROMSTG STCK 6. 7f7d4000 00000400 AFTER CAR 7. 7f7cb000 00009000 57a9e102 8. 7f7c3000 00007df0 RAMSTAGE 9. 7f789000 0003a000 57a9e100 10. 7f750000 00038898 REFCODE 11. 7f737000 00019000 57a9e101 12. 7f71e000 00019000 COREBOOT 13. 7f716000 00008000 ACPI 14. 7f6f2000 00024000 TCPA LOG 15. 7f6e2000 00010000 SMBIOS 16. 7f6e1000 00000800 IMD small region: IMD ROOT 0. 7fbfec00 00000400 FSP RUNTIME 1. 7fbfebe0 00000004 ROMSTAGE 2. 7fbfebc0 00000004 57a9e002 3. 7fbfeba0 00000018 57a9e000 4. 7fbfeb80 00000018 57a9e001 5. 7fbfeb60 00000018 MEM INFO 6. 7fbfea00 00000149 ACPI GNVS 7. 7fbfe900 00000100 GNVS PTR 8. 7fbfe8e0 00000004 COREBOOTFWD 9. 7fbfe8a0 00000028 BS: BS_WRITE_TABLES times (us): entry 0 run 375379 exit 0 CBFS: 'Master Header Locator' located CBFS at [20000:1fffc0) CBFS: Locating 'fallback/payload' CBFS: Found @ offset 1c2c0 size 65909 Loading segment from ROM address 0xffe3c2f8 code (compression=1) New segment dstaddr 0x9000 memsize 0x1b9c8 srcaddr 0xffe3c34c filesize 0x9a2c Loading segment from ROM address 0xffe3c314 code (compression=1) New segment dstaddr 0x100000 memsize 0x1297c4 srcaddr 0xffe45d78 filesize 0x5be89 Loading segment from ROM address 0xffe3c330 Entry Point 0x00009000 Loading Segment: addr: 0x0000000000009000 memsz: 0x000000000001b9c8 filesz: 0x0000000000009a2c Post relocation: addr: 0x0000000000009000 memsz: 0x000000000001b9c8 filesz: 0x0000000000009a2c using LZMA Clearing Segment: addr: 0x000000000001cf83 memsz: 0x0000000000007a45 dest 00009000, end 000249c8, bouncebuffer ffffffff Loading Segment: addr: 0x0000000000100000 memsz: 0x00000000001297c4 filesz: 0x000000000005be89 Post relocation: addr: 0x0000000000100000 memsz: 0x00000000001297c4 filesz: 0x000000000005be89 using LZMA dest 00100000, end 002297c4, bouncebuffer ffffffff NotifyPhaseApi() - Begin [Phase: 00000040] FSP Ready To Boot ... Install PPI: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: FFF6E433 [SPS] SpsFspReadyToBootEvent Start [SPS] Looking for SPS HOB info .. [SPS] HOB: flow 1, feature set 0x9B8106, pwr opt boot 0, cores2disable 0 [SPS] SpsFspSendHmrfpoLockRequest Start [SPS] Sending HMRFPO_LOCK to ME [HECI] Send msg: 80040007 00000205 [HECI] Got msg: 80180007 00008205 ... [SPS] SpsFspSendHmrfpoLockRequest End (Success) [SPS] SpsFspSendEndOfPost Start [SPS] Sending END_OF_POST to ME [HECI] Send msg: 80040007 00000CFF [HECI] Got msg: 80080007 00008CFF ... [SPS] SpsFspSendEndOfPost End [SPS] Disabling Global Reset capability [SPS] SpsFspReadyToBootEvent End Success Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7FBA3444 SaEndOfDxeCallback() Start SaEndOfDxeCallback() End Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7FB942FB Fsp PchFspOnEndOfDxe() Start Common PchOnEndOfDxe() Start GC = 0xFDCF000C Value = 0x00000002 Protected range 0: 0x80000000 Protected range 1: 0x80000000 Protected range 2: 0x80000000 Protected range 3: 0x80000000 Protected range 4: 0x80000000 Set LPC EISS Set SPI EISS Set LPC bios lock Set SPI bios lock PM_CFG = 0xFE000018 Value = 0x29C0002C ConfigureP2sbOnEndOfDxe() Start PCH Revision ID: 0x11 ConfigureP2sbOnEndOfDxe() End Common PchOnEndOfDxe() End Fsp PchFspOnEndOfDxe() End NotifyPhaseApi() - End [Status: 0x00000000] NotifyPhaseApi() - Begin [Phase: 000000F0] FSP End of Firmware ... Install PPI: BD44F629-EAE7-4198-87F1-39FAB0FD717E NotifyPhaseApi() - End [Status: 0x00000000] HIDING HSUARTs. Finalizing SMM. BS: BS_PAYLOAD_LOAD times (us): entry 0 run 350364 exit 500417 Jumping to boot code at 00009000(7f716000) Hello world! GNU GRUB version 2.03 Minimal BASH-like line editing is supported. For the first word, TAB lists possible command completions. Anywhere else TAB lists possible device or file completions. grub>