Author: rminnich Date: 2008-08-22 18:48:44 +0200 (Fri, 22 Aug 2008) New Revision: 804
Modified: coreboot-v3/mainboard/amd/serengeti/mainboard.h coreboot-v3/northbridge/amd/k8/common.c coreboot-v3/northbridge/amd/k8/domain.c coreboot-v3/northbridge/amd/k8/raminit.c Log: This is getting to the link phase. Still won't build as we don't have dqs timing file compiled in yet.
Per discussion with YingHai Lu, we are only going to support F2 and later CPUs. This will simplify more code.
I realize this code needs work, but it is in v2, and cleanup will get easier once we have the baseline.
Signed-off-by: Ronald G. Minnich rminnich@gmail.com Acked-by: Ronald G. Minnich rminnich@gmail.com
Modified: coreboot-v3/mainboard/amd/serengeti/mainboard.h =================================================================== --- coreboot-v3/mainboard/amd/serengeti/mainboard.h 2008-08-22 11:33:19 UTC (rev 803) +++ coreboot-v3/mainboard/amd/serengeti/mainboard.h 2008-08-22 16:48:44 UTC (rev 804) @@ -22,3 +22,4 @@ */
#define CPU_SOCKET_TYPE SOCKET_AM2 +#define MEM_TRAIN_SEQ 1 /* for now */
Modified: coreboot-v3/northbridge/amd/k8/common.c =================================================================== --- coreboot-v3/northbridge/amd/k8/common.c 2008-08-22 11:33:19 UTC (rev 803) +++ coreboot-v3/northbridge/amd/k8/common.c 2008-08-22 16:48:44 UTC (rev 804) @@ -121,7 +121,7 @@ int node_id; };
-static struct hw_mem_hole_info get_hw_mem_hole_info(void) +struct hw_mem_hole_info get_hw_mem_hole_info(void) { struct hw_mem_hole_info mem_hole; int i; @@ -172,7 +172,8 @@ return mem_hole; } -static void disable_hoist_memory(unsigned long hole_startk, int i) + +void disable_hoist_memory(unsigned long hole_startk, int i) { int ii; struct device * dev;
Modified: coreboot-v3/northbridge/amd/k8/domain.c =================================================================== --- coreboot-v3/northbridge/amd/k8/domain.c 2008-08-22 11:33:19 UTC (rev 803) +++ coreboot-v3/northbridge/amd/k8/domain.c 2008-08-22 16:48:44 UTC (rev 804) @@ -166,6 +166,8 @@
static void k8_pci_domain_set_resources(struct device * dev) { + struct hw_mem_hole_info get_hw_mem_hole_info(void); + void disable_hoist_memory(unsigned long hole_startk, int i); #if CONFIG_PCI_64BIT_PREF_MEM == 1 struct resource *io, *mem1, *mem2; struct resource *resource, *last; @@ -325,7 +327,7 @@ }
- printk(BIOS_DEBUG, "node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu + printk(BIOS_DEBUG, "node %d : mmio_basek=%08x, basek=%08lx, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu /* See if I need to split the region to accomodate pci memory space */ if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {
Modified: coreboot-v3/northbridge/amd/k8/raminit.c =================================================================== --- coreboot-v3/northbridge/amd/k8/raminit.c 2008-08-22 11:33:19 UTC (rev 803) +++ coreboot-v3/northbridge/amd/k8/raminit.c 2008-08-22 16:48:44 UTC (rev 804) @@ -27,6 +27,7 @@ */
#include <console.h> +#include <string.h> #include <mtrr.h> #include <macros.h> #include <spd.h> @@ -44,7 +45,9 @@
#warning where to we define supported DIMM types #define DIMM_SUPPORT 0x0104 -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 1 + +/* we won't support the buggy old chips */ +#undef K8_REV_F_SUPPORT_F0_F1_WORKAROUND inline void print_raminit(const char *strval, u32 val) { printk(BIOS_DEBUG, "%s%08x\n", strval, val); @@ -866,7 +869,7 @@ #if CPU_SOCKET_TYPE == SOCKET_L1 ClkDis0 = DTL_MemClkDis0; #else - #if CPU_SOCKET_TYPE SOCKET_AM2 + #if CPU_SOCKET_TYPE == SOCKET_AM2 ClkDis0 = DTL_MemClkDis0_AM2; #endif #endif @@ -1595,7 +1598,7 @@
value = pci_conf1_read_config32(ctrl->f3, NORTHBRIDGE_CAP); min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK]; - read_option(&max_mem_clock, "max_mem_clock"); + get_option(&max_mem_clock, "max_mem_clock"); bios_cycle_time = min_cycle_times[max_mem_clock]; if (bios_cycle_time > min_cycle_time) { min_cycle_time = bios_cycle_time; @@ -2379,15 +2382,15 @@ #endif
/* Program the Output Driver Compensation Control Registers (Function 2:Offset 0x9c, index 0, 0x20) */ - pci_conf1_write_config32_index_wait(ctrl->f2, 0x98, 0, dword); + pci_write_config32_index_wait(ctrl->f2, 0x98, 0, dword); if(meminfo->is_Width128) { - pci_conf1_write_config32_index_wait(ctrl->f2, 0x98, 0x20, dword); + pci_write_config32_index_wait(ctrl->f2, 0x98, 0x20, dword); }
/* Program the Address Timing Control Registers (Function 2:Offset 0x9c, index 4, 0x24) */ - pci_conf1_write_config32_index_wait(ctrl->f2, 0x98, 4, dwordx); + pci_write_config32_index_wait(ctrl->f2, 0x98, 4, dwordx); if(meminfo->is_Width128) { - pci_conf1_write_config32_index_wait(ctrl->f2, 0x98, 0x24, dwordx); + pci_write_config32_index_wait(ctrl->f2, 0x98, 0x24, dwordx); }
} @@ -2519,6 +2522,8 @@ struct mem_param paramx; struct mem_info *meminfo; long dimm_mask; + void activate_spd_rom(const struct mem_controller *ctrl); + void hard_reset(void); #if 1 if (!sysinfo->ctrl_present[ctrl->node_id]) { return; @@ -2526,7 +2531,7 @@ #endif meminfo = &sysinfo->meminfo[ctrl->node_id];
- print_debug_addr("sdram_set_spd_registers: paramx :", ¶mx); + printk(BIOS_DEBUG, "sdram_set_spd_registers: paramx :0x%x\n", paramx); activate_spd_rom(ctrl); dimm_mask = spd_detect_dimms(ctrl); @@ -2684,9 +2689,9 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo) { int i; - - -#if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 + void dqs_timing(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo); + void memreset(int controllers, const struct mem_controller *ctrl); +#ifdef K8_REV_F_SUPPORT_F0_F1_WORKAROUND unsigned cpu_f0_f1[8]; /* FIXME: How about 32 node machine later? */ tsc_t tsc, tsc0[8]; @@ -2755,7 +2760,7 @@ pci_conf1_write_config32(ctrl[i].f3, MCA_NB_CONFIG, mnc); }
-#if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 +#ifdef K8_REV_F_SUPPORT_F0_F1_WORKAROUND cpu_f0_f1[i] = is_cpu_pre_f2_in_bsp(i); if(cpu_f0_f1[i]) { //Rev F0/F1 workaround @@ -2808,7 +2813,7 @@ dcm = pci_conf1_read_config32(ctrl[i].f2, DRAM_CTRL_MISC); } while(((dcm & DCM_MemClrStatus) == 0) /* || ((dcm & DCM_DramEnabled) == 0)*/ );
-#if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 +#ifdef K8_REV_F_SUPPORT_F0_F1_WORKAROUND if(cpu_f0_f1[i]) { tsc= rdtsc();
@@ -2863,7 +2868,7 @@
#if MEM_TRAIN_SEQ == 0 - #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 + #ifdef dqs_timing(controllers, ctrl, tsc0, sysinfo); #else dqs_timing(controllers, ctrl, sysinfo); @@ -2880,7 +2885,7 @@ if(sysinfo->mem_trained[i]!=0x80) continue;
- dqs_timing(i, &ctrl[i], sysinfo, 1); + dqs_timing(i, &ctrl[i], sysinfo);
#if MEM_TRAIN_SEQ == 1 break; // only train the first node with ram