On Wed, May 20, 2015 at 1:13 PM, Michael Gerlach <n3ph@terminal21.de> wrote:
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I forgot to mention that somehow the ram frequency is not detected
correctly...

 PLL busy...done
PLL didn't lock. Retrying at lower frequency
 PLL busy...done
PLL didn't lock. Retrying at lower frequency
 PLL busy...done
PLL didn't lock. Retrying at lower frequency
 PLL busy...done
PLL didn't lock. Retrying at lower frequency
No lock frequency found

The SPD data should be read via SMBus long before PLL locking for the DRAM itself takes place.

If you're unable to successfully read the SPDs, then it makes sense that later init would fail.

--
David Hendricks (dhendrix)
Systems Software Engineer, Google Inc.