Please refer to Chapter 10 "Memory Cache Control" in the Intel manual you mentioned. Find the Table called "Cache Operating Modes" (Table 10-5 in current version). The way it works is described well in that table. For CD=1, "Read hits access the cache; read misses do not cause replacement." and "Write hits update the cache". So that means anything that is a "hit" acts just like RAM. Nothing too fancy. You just have to make sure that the area you want to "hit" gets pre-loaded before you turn the cache back off again.
On 10/26/06, Jiangbo W firstname.lastname@example.org wrote:
VIA C3, it is compatible with X86, but only have 128K L2 cache. In Intel Manual Volume 3, i can not find anything about cache as rom
On 10/26/06, yhlu email@example.com wrote:
what is your CPU?
On 10/26/06, Jiangbo W <firstname.lastname@example.org > wrote:
When using cache as ram how can i ensure that the data in cache can not
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