From 935058917fd61eda821d53beb1143dfdbdf231bf Mon Sep 17 00:00:00 2001
From: Yang Hamo Bai <hamo.by@gmail.com>
Date: Thu, 30 Jun 2011 19:31:25 +0800
Subject: [PATCH 10/12] ARM: added support for ARM926EJS core

added start code for ARM926EJS core, code borrowed
from U-boot and modified for coreboot to create the
bootblock.

Signed-off-by: Yang Hamo Bai <hamo.by@gmail.com>
---
 src/cpu/Kconfig                         |    7 ++
 src/cpu/Makefile.inc                    |    2 +
 src/cpu/arm/Kconfig                     |    7 ++
 src/cpu/arm/Makefile.inc                |    1 +
 src/cpu/arm/arm926ejs/Kconfig           |    8 ++
 src/cpu/arm/arm926ejs/Makefile.inc      |    8 ++
 src/cpu/arm/arm926ejs/start.S           |  175 +++++++++++++++++++++++++++++++
 7 files changed, 208 insertions(+), 0 deletions(-)
 create mode 100644 src/cpu/arm/Kconfig
 create mode 100644 src/cpu/arm/Makefile.inc
 create mode 100644 src/cpu/arm/arm926ejs/Kconfig
 create mode 100644 src/cpu/arm/arm926ejs/Makefile.inc
 create mode 100644 src/cpu/arm/arm926ejs/start.S
 create mode 100644 src/cpu/arm/arm926ejs/versatile/Kconfig

diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig
index 6e65186..f1282bf 100644
--- a/src/cpu/Kconfig
+++ b/src/cpu/Kconfig
@@ -61,3 +61,10 @@ config VAR_MTRR_HOLE
 		subtractive MTRRs
 
 endif # ARCH_X86
+
+if ARCH_ARM
+
+source src/cpu/arm/Kconfig
+
+endif # ARCH_ARM
+
diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index 57273cf..9aa8fb7 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -1,3 +1,5 @@
 subdirs-y += amd
 subdirs-y += intel
 subdirs-y += via
+
+subdirs-y += arm
diff --git a/src/cpu/arm/Kconfig b/src/cpu/arm/Kconfig
new file mode 100644
index 0000000..b9aae36
--- /dev/null
+++ b/src/cpu/arm/Kconfig
@@ -0,0 +1,7 @@
+# arm core
+source src/cpu/arm/arm926ejs/Kconfig
+
+config CPU_ARM926EJS
+       bool
+       default n
+
diff --git a/src/cpu/arm/Makefile.inc b/src/cpu/arm/Makefile.inc
new file mode 100644
index 0000000..d3deb0a
--- /dev/null
+++ b/src/cpu/arm/Makefile.inc
@@ -0,0 +1 @@
+subdirs-$(CONFIG_CPU_ARM926EJS) += arm926ejs
diff --git a/src/cpu/arm/arm926ejs/Kconfig b/src/cpu/arm/arm926ejs/Kconfig
new file mode 100644
index 0000000..50b3d42
--- /dev/null
+++ b/src/cpu/arm/arm926ejs/Kconfig
@@ -0,0 +1,8 @@
+config CPU_DIR
+       string
+       default arm926ejs
+
+config CPU_VERSATILE
+       bool
+       default n
+
diff --git a/src/cpu/arm/arm926ejs/Makefile.inc b/src/cpu/arm/arm926ejs/Makefile.inc
new file mode 100644
index 0000000..5495668
--- /dev/null
+++ b/src/cpu/arm/arm926ejs/Makefile.inc
@@ -0,0 +1,8 @@
+CPUDIR=$(call strip_quotes,$(CONFIG_CPU_DIR))
+export CPUDIR
+
+subdirs-$(CONFIG_CPU_VERSATILE) += versatile
+
+CC += -march=armv5te 
+CC += -mcpu=arm926ej-s 
+
diff --git a/src/cpu/arm/arm926ejs/start.S b/src/cpu/arm/arm926ejs/start.S
new file mode 100644
index 0000000..7c33136
--- /dev/null
+++ b/src/cpu/arm/arm926ejs/start.S
@@ -0,0 +1,175 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *  Copyright (c) 2003  Texas Instruments
+ *
+ *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
+ *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
+ *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
+ *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
+ *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
+ *
+ *  Copyright (C) 2011 Yang Bai <hamo.by@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+
+/*
+ *************************************************************************
+ *
+ * Jump vector table
+ *
+ *************************************************************************
+ */
+
+.globl _start
+_start:
+	b	reset
+
+	/*
+	 * we do not use interrupt during boot-up,
+	 * payload should set their own interrupt vectors.
+	 */
+	b 	hang
+	b	hang
+	b	hang
+	b	hang
+	b	hang
+	b	hang
+	b	hang
+
+HEADER:
+MAGIC:
+	.word 	0xFFFFFFFF
+VER:
+	.word 	0xFFFFFFFF
+ROMSIZE:
+	.word 	0xFFFFFFFF
+BOOTBLOCKSIZE:
+	.word 	0xFFFFFFFF
+ALIGN:
+	.word 	0xFFFFFFFF
+OFFSET:
+	.word 	0xFFFFFFFF
+ARCH:
+	.word 	0xFFFFFFFF
+PAD:
+	.word 	0xFFFFFFFF
+
+
+	.align	4,0xFF
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init
+ * setup Memory and board specific bits
+ * then jump to romstage
+ *
+ *************************************************************************
+ */
+
+/*
+ * the actual reset code
+ */
+
+reset:
+	/*
+	 * set the cpu to SVC32 mode
+	 */
+	mrs	r0,cpsr
+	bic	r0,r0,#0x1f
+	orr	r0,r0,#0xd3
+	msr	cpsr,r0
+
+	/*
+	 * do sys-critical inits
+	 */
+	bl	cpu_init_crit
+
+	/*
+	 * finish CPU init now,
+	 * find romstage and jump to it.
+	 */
+	ldr 	r0, =filename
+	bl 	walkcbfs_asm
+
+	/*
+	 * At here, r1 should hold the address of
+	 * romstage header or NULL.
+	 */
+	cmp	r1, #0
+	beq	hang
+
+	/*
+	 * struct cbfs_stage_restricted {
+ 	 *	 unsigned long compression;
+	 *       unsigned long entry;
+	 * }
+	 */
+	ldr	pc, [r1, #4]
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+	.align 4, 0xFF
+cpu_init_crit:
+	/*
+	 * flush v4 I/D caches
+	 */
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
+	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
+
+	/*
+	 * disable MMU stuff and caches
+	 */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, r0, #0x00002300	/* clear bits 13, 9:8 (--V- --RS) */
+	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
+	orr	r0, r0, #0x00000002	/* set bit 2 (A) Align */
+	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
+	mcr	p15, 0, r0, c1, c0, 0
+
+	/*
+	 * Go setup Memory and board specific bits.
+	 */
+	mov	ip, lr		/* perserve link reg across call */
+	bl	lowlevel_init	/* go setup pll,mux,memory */
+	mov	lr, ip		/* restore link */
+	mov	pc, lr		/* back to my caller */
+
+	/*
+	 * Hang here if any error happens.
+	 */
+hang:
+	b 	hang
+
+	/*
+	 * Name of romstage
+	 */
+.section ".rodata"	
+filename:
+	.ascii 	CONFIG_CBFS_PREFIX
+	.string "/romstage"
diff --git a/src/cpu/arm/arm926ejs/versatile/Kconfig b/src/cpu/arm/arm926ejs/versatile/Kconfig
new file mode 100644
index 0000000..e69de29
-- 
1.7.6

