System reset seems to occur between 2 and 3, both of those logs attached, along with arch/x86/via/stage1.o With HALT_AFTER=3, the post code keeps changing, as expected with the system rebooting, with HALT_AFTER=2 it was 0xc2.

Thanks,
Corey

On Sat, Nov 1, 2008 at 7:38 AM, Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> wrote:
On 01.11.2008 12:33, Carl-Daniel Hailfinger wrote:
> Thanks. I now understand where parts of the garbage come from. Can you
> try the attached patch? It should require no further fixups for COM2.
>
> It would be great if you could use various values between 0 and 13
> (inclusive) for the #define HALT_AFTER. The idea there is to
> decrease/increase the value up to the biggest value where it doesn't
> reboot automatically. The POST codes emitted by the diagnostic code
> should be between 0xC0 and 0xCD. The last expected POST code for a given
> HALT_AFTER is 0xC0+HALT_AFTER.
>
> I'm also increasingly convinced that RAM is not working right,
> especially for the area we use as stack. Can you enable ram_check() in
> mainboard/.../initram.c again?
>

My apologies. I had attached an older version of the patch. Please try
this one.
Oh, and I'd be very interested in your build/arch/x86/via/stage1.o file.

Regards,
Carl-Daniel

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