On 10/13/2010 01:24 AM, Warren Turkal wrote:
On Tuesday 12 October 2010 19:22:43 Joseph Smith wrote:
FC-PGA's support SSE2 while the PGA's do not. that is the difference. I created FC_PGA370 to make the CAR coversion simpler. Hope that helps.
I must be misunderstanding this entirely.
First, you say there is a difference in that the FC version support SSE2. Then, you say that the FC_PGA370 socket is simply a mechanism to make conversion to CAR easier.
Does that mean that FC_PGA370 is simply PGA370 + CAR, or do PGA370 sockets really not support SSE2 chips?
Researching it a little bit, I see that FC-PGA370 is a mechanically compatible socket, so I guess that the FC-PGA370 supports chips that the PGA370 does not. Is that correct? So FC-PGA is more than just an upgrade CAR?
Yes, socket wise they are backwars compatable in 99% of boards. The PGA's were 66MHz FSB Celerons with 128k L2 cache.
So I guess I would be satisfied if I knew that the minimum size l2 cache for a chip that fits in the PGA370 was 4K since that's what the patch says and since that's really what matters for the DCACHE_RAM_SIZE.
Also, are we sure that the DCACHE_RAM_BASE used will work? I.e. has it been tested on real hardware?
Also, if we have real hardware running that works with this. Would if be possible to get a the register output for a cpuid 0x80000006 call? I'd just like to know if it would work on that processor since that call can be used to dynamically determine the amount of l2 cache. I've been thinking about adding that to the intel/amd/via CAR implementations so that DCACHE_RAM_SIZE doesn't need to be set.
I'm sure CAR will work on the PGA's, although they may need Keith's L2 patch. More or less it was decided a while ago to split the model_6xx romcc clump-o-crap out into their own CAR model directories (starting with model_68x). I have a bunch of Socket 370 processors (FC-PGA and PGA) I plan on testing on my i810 board... I just have alot on my plate at this time.