--- src/southbridge/via/k8t890/early_car.c	(revision 6342)
+++ src/southbridge/via/k8t890/early_car.c	(working copy)
@@ -25,7 +25,7 @@
 #include <stdlib.h>
 #include <cbmem.h>
 #include <arch/io.h>
-#include "k8t890.h"
+#include "k8x8xx.h"
 
 /* The 256 bytes of NVRAM for S3 storage, 256B aligned */
 #define K8T890_NVRAM_IO_BASE	0xf00
--- src/southbridge/via/k8t890/host_ctrl.c	(revision 6342)
+++ src/southbridge/via/k8t890/host_ctrl.c	(working copy)
@@ -24,7 +24,7 @@
 #include <console/console.h>
 #include <cbmem.h>
 #include <arch/io.h>
-#include "k8t890.h"
+#include "k8x8xx.h"
 
 /* this may be later merged */
 
--- src/southbridge/via/k8t890/ctrl.c	(revision 6342)
+++ src/southbridge/via/k8t890/ctrl.c	(working copy)
@@ -22,7 +22,7 @@
 #include <device/pci_ops.h>
 #include <device/pci_ids.h>
 #include <console/console.h>
-#include "k8t890.h"
+#include "k8x8xx.h"
 
 /* We support here K8M890/K8T890 and VT8237R PCI1/Vlink which setup is not in separate
  * PCI device 0:11.7, but it is mapped to PCI 0:0.7 (0x70-0x7c for PCI1)
--- src/southbridge/via/k8t890/chrome.c	(revision 6342)
+++ src/southbridge/via/k8t890/chrome.c	(working copy)
@@ -23,7 +23,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <string.h> /* for memset */
-#include "k8t890.h"
+#include "k8x8xx.h"
 
 #if CONFIG_VGA
 #include <pc80/vga_io.h>
--- src/southbridge/via/k8t890/host.c	(revision 6342)
+++ src/southbridge/via/k8t890/host.c	(working copy)
@@ -22,7 +22,7 @@
 #include <device/pci_ops.h>
 #include <device/pci_ids.h>
 #include <console/console.h>
-#include "k8t890.h"
+#include "k8x8xx.h"
 
 static void host_enable(struct device *dev)
 {
--- src/southbridge/via/k8t890/dram.c	(revision 6342)
+++ src/southbridge/via/k8t890/dram.c	(working copy)
@@ -25,7 +25,7 @@
 #include <cpu/amd/mtrr.h>
 #include <pc80/mc146818rtc.h>
 #include <bitops.h>
-#include "k8t890.h"
+#include "k8x8xx.h"
 
 static void dram_enable(struct device *dev)
 {
--- src/southbridge/via/k8t890/error.c	(revision 6342)
+++ src/southbridge/via/k8t890/error.c	(working copy)
@@ -21,7 +21,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <console/console.h>
-#include "k8t890.h"
+#include "k8x8xx.h"
 
 static void error_enable(struct device *dev)
 {
--- src/southbridge/via/k8t890/bridge.c	(revision 6342)
+++ src/southbridge/via/k8t890/bridge.c	(working copy)
@@ -21,7 +21,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <console/console.h>
-#include "k8t890.h"
+#include "k8x8xx.h"
 
 static void bridge_enable(struct device *dev)
 {
--- src/southbridge/via/k8t890/k8x8xx.h	(revision 0)
+++ src/southbridge/via/k8t890/k8x8xx.h	(revision 0)
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ * 
+ * Copyright (C) 2011  Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef SOUTHBRIDGE_VIA_K8T890_K8X8XX_H
+#define SOUTHBRIDGE_VIA_K8T890_K8X8XX_H
+
+#include "k8t890.h"
+
+#endif//SOUTHBRIDGE_VIA_K8T890_K8X8XX_H
\ No newline at end of file