=~=~=~=~=~=~=~=~=~=~=~= PuTTY log 2013.10.09 15:20:32 =~=~=~=~=~=~=~=~=~=~=~= [snap] Loading image. CBFS: Looking for 'fallback/coreboot_ram' CBFS: found. CBFS: loading stage fallback/coreboot_ram @ 0x100000 (671744 bytes), entry @ 0x100000 Jumping to image. POST: 0x80 POST: 0x39 coreboot-unknown Wed Oct 9 14:22:55 CEST 2013 booting... POST: 0x40 Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 APIC: acac: enabled 0 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:04.0: enabled 1 PCI: 00:06.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.1: enabled 1 PCI: 00:16.2: enabled 0 PCI: 00:16.3: enabled 0 PCI: 00:19.0: enabled 1 PCI: 00:1a.0: enabled 1 PCI: 00:1b.0: enabled 1 PCI: 00:1c.0: enabled 0 PCI: 00:1c.1: enabled 0 PCI: 00:1c.2: enabled 0 PCI: 00:1c.3: enabled 0 PCI: 00:1c.4: enabled 0 PCI: 00:1c.5: enabled 0 PCI: 00:1c.6: enabled 0 PCI: 00:1c.7: enabled 0 PCI: 00:1d.0: enabled 1 PCI: 00:1f.0: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 1 PCI: 00:1f.5: enabled 0 PCI: 00:1f.6: enabled 0 Compare with tree... Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 APIC: acac: enabled 0 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:04.0: enabled 1 PCI: 00:06.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.1: enabled 1 PCI: 00:16.2: enabled 0 PCI: 00:16.3: enabled 0 PCI: 00:19.0: enabled 1 PCI: 00:1a.0: enabled 1 PCI: 00:1b.0: enabled 1 PCI: 00:1c.0: enabled 0 PCI: 00:1c.1: enabled 0 PCI: 00:1c.2: enabled 0 PCI: 00:1c.3: enabled 0 PCI: 00:1c.4: enabled 0 PCI: 00:1c.5: enabled 0 PCI: 00:1c.6: enabled 0 PCI: 00:1c.7: enabled 0 PCI: 00:1d.0: enabled 1 PCI: 00:1f.0: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 1 PCI: 00:1f.5: enabled 0 PCI: 00:1f.6: enabled 0 scan_static_bus for Root Device APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 POST: 0x24 PCI: 00:00.0 [8086/0154] ops PCI: 00:00.0 [8086/0154] enabled PCI: Static device PCI: 00:01.0 not found, disabling it. PCI: 00:02.0 [8086/0000] ops PCI: 00:02.0 [8086/0166] enabled PCI: Static device PCI: 00:04.0 not found, disabling it. PCI: Static device PCI: 00:06.0 not found, disabling it. PCI: 00:14.0 [8086/1e31] enabled PCI: 00:16.0 [8086/1e3a] enabled PCI: 00:16.1 [8086/1e3b] enabled PCI: 00:16.2: Disabling device PCI: 00:16.3: Disabling device PCI: 00:19.0 [8086/1502] enabled PCI: 00:1a.0 [8086/1e2d] enabled PCI: 00:1b.0 [8086/1e20] enabled PCH: PCIe Root Port coalescing is enabled PCI: 00:1c.0: Disabling device PCI: 00:1c.0: check set enabled PCI: 00:1c.1: Disabling device PCI: 00:1c.2: Disabling device PCI: 00:1c.3: Disabling device PCI: 00:1c.4: Disabling device PCI: 00:1c.4: check set enabled PCI: 00:1c.5: Disabling device PCI: 00:1c.6: Disabling device PCI: 00:1c.7: Disabling device PCH: RPFN 0x76543210 -> 0xfedcba98 PCI: 00:1d.0 [8086/1e26] enabled PCI: 00:1f.0 [8086/0000] bus ops PCI: 00:1f.0 [8086/1e57] enabled PCI: 00:1f.2 [8086/1e03] enabled PCI: 00:1f.3 [8086/1e22] enabled PCI: 00:1f.5: Disabling device PCI: 00:1f.6: Disabling device POST: 0x25 scan_static_bus for PCI: 00:1f.0 scan_static_bus for PCI: 00:1f.0 done PCI: pci_scan_bus returning with max=000 POST: 0x55 scan_static_bus for Root Device done done POST: 0x66 found VGA at PCI: 00:02.0 Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done memalign Enter, boundary 8, size 2560, free_mem_ptr 001a0000 memalign 001a0000 PCI_DOMAIN: 0000 read_resources bus 0 link: 0 Adding PCIe enhanced config space BAR 0xf8000000-0xfc000000. PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: acac PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf PCI: 00:01.0 PCI: 00:02.0 PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20 PCI: 00:04.0 PCI: 00:06.0 PCI: 00:14.0 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 PCI: 00:16.0 PCI: 00:16.0 resource base 0 size 10 align 4 gran 4 limit ffffffffffffffff flags 201 index 10 PCI: 00:16.1 PCI: 00:16.1 resource base 0 size 10 align 4 gran 4 limit ffffffffffffffff flags 201 index 10 PCI: 00:16.2 PCI: 00:16.3 PCI: 00:19.0 PCI: 00:19.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:19.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18 PCI: 00:1a.0 PCI: 00:1a.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10 PCI: 00:1b.0 PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:1c.0 PCI: 00:1c.1 PCI: 00:1c.2 PCI: 00:1c.3 PCI: 00:1c.4 PCI: 00:1c.5 PCI: 00:1c.6 PCI: 00:1c.7 PCI: 00:1d.0 PCI: 00:1d.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10 PCI: 00:1f.0 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:1f.2 PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:1f.2 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 24 PCI: 00:1f.3 PCI: 00:1f.3 resource base 0 size 100 align 8 gran 8 limit ffffffffffffffff flags 201 index 10 PCI: 00:1f.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:1f.5 PCI: 00:1f.6 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:02.0 20 * [0x0 - 0x3f] io PCI: 00:19.0 18 * [0x40 - 0x5f] io PCI: 00:1f.2 20 * [0x60 - 0x7f] io PCI: 00:1f.3 20 * [0x80 - 0x9f] io PCI: 00:1f.2 10 * [0xa0 - 0xa7] io PCI: 00:1f.2 18 * [0xa8 - 0xaf] io PCI: 00:1f.2 14 * [0xb0 - 0xb3] io PCI: 00:1f.2 1c * [0xb4 - 0xb7] io PCI_DOMAIN: 0000 compute_resources_io: base: b8 size: b8 align: 6 gran: 0 limit: ffff done PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem PCI: 00:02.0 10 * [0x10000000 - 0x103fffff] mem PCI: 00:19.0 10 * [0x10400000 - 0x1041ffff] mem PCI: 00:14.0 10 * [0x10420000 - 0x1042ffff] mem PCI: 00:1b.0 10 * [0x10430000 - 0x10433fff] mem PCI: 00:19.0 14 * [0x10434000 - 0x10434fff] mem PCI: 00:1f.2 24 * [0x10435000 - 0x104357ff] mem PCI: 00:1a.0 10 * [0x10435800 - 0x10435bff] mem PCI: 00:1d.0 10 * [0x10435c00 - 0x10435fff] mem PCI: 00:1f.3 10 * [0x10436000 - 0x104360ff] mem PCI: 00:16.0 10 * [0x10436100 - 0x1043610f] mem PCI: 00:16.1 10 * [0x10436110 - 0x1043611f] mem PCI_DOMAIN: 0000 compute_resources_mem: base: 10436120 size: 10436120 align: 28 gran: 0 limit: ffffffff done avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:02.0 constrain_resources: PCI: 00:14.0 constrain_resources: PCI: 00:16.0 constrain_resources: PCI: 00:16.1 constrain_resources: PCI: 00:19.0 constrain_resources: PCI: 00:1a.0 constrain_resources: PCI: 00:1b.0 constrain_resources: PCI: 00:1d.0 constrain_resources: PCI: 00:1f.0 constrain_resources: PCI: 00:1f.2 constrain_resources: PCI: 00:1f.3 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff lim->base 00001000 lim->limit 0000ffff avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff lim->base 00000000 lim->limit f7ffffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:b8 align:6 gran:0 limit:ffff Assigned: PCI: 00:02.0 20 * [0x1000 - 0x103f] io Assigned: PCI: 00:19.0 18 * [0x1040 - 0x105f] io Assigned: PCI: 00:1f.2 20 * [0x1060 - 0x107f] io Assigned: PCI: 00:1f.3 20 * [0x1080 - 0x109f] io Assigned: PCI: 00:1f.2 10 * [0x10a0 - 0x10a7] io Assigned: PCI: 00:1f.2 18 * [0x10a8 - 0x10af] io Assigned: PCI: 00:1f.2 14 * [0x10b0 - 0x10b3] io Assigned: PCI: 00:1f.2 1c * [0x10b4 - 0x10b7] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 10b8 size: b8 align: 6 gran: 0 done PCI_DOMAIN: 0000 allocate_resources_mem: base:e0000000 size:10436120 align:28 gran:0 limit:f7ffffff Assigned: PCI: 00:02.0 18 * [0xe0000000 - 0xefffffff] prefmem Assigned: PCI: 00:02.0 10 * [0xf0000000 - 0xf03fffff] mem Assigned: PCI: 00:19.0 10 * [0xf0400000 - 0xf041ffff] mem Assigned: PCI: 00:14.0 10 * [0xf0420000 - 0xf042ffff] mem Assigned: PCI: 00:1b.0 10 * [0xf0430000 - 0xf0433fff] mem Assigned: PCI: 00:19.0 14 * [0xf0434000 - 0xf0434fff] mem Assigned: PCI: 00:1f.2 24 * [0xf0435000 - 0xf04357ff] mem Assigned: PCI: 00:1a.0 10 * [0xf0435800 - 0xf0435bff] mem Assigned: PCI: 00:1d.0 10 * [0xf0435c00 - 0xf0435fff] mem Assigned: PCI: 00:1f.3 10 * [0xf0436000 - 0xf04360ff] mem Assigned: PCI: 00:16.0 10 * [0xf0436100 - 0xf043610f] mem Assigned: PCI: 00:16.1 10 * [0xf0436110 - 0xf043611f] mem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: f0436120 size: 10436120 align: 28 gran: 0 done Root Device assign_resources, bus 0 link: 0 TOUUD 0x240500000 TOLUD 0xbfa00000 TOM 0x200000000 MEBASE 0x1fff00000 IGD decoded, subtracting 64M UMA and 2M GTT TSEG base 0xbb000000 size 8M Available memory below 4GB: 2992M Available memory above 4GB: 5125M Adding PCIe config bar base=0xf8000000 size=0x4000000 PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:00.0 cf <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x00 mem PCI: 00:02.0 10 <- [0x00f0000000 - 0x00f03fffff] size 0x00400000 gran 0x16 mem64 PCI: 00:02.0 18 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem64 PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io PCI: 00:14.0 10 <- [0x00f0420000 - 0x00f042ffff] size 0x00010000 gran 0x10 mem64 PCI: 00:16.0 10 <- [0x00f0436100 - 0x00f043610f] size 0x00000010 gran 0x04 mem64 PCI: 00:16.1 10 <- [0x00f0436110 - 0x00f043611f] size 0x00000010 gran 0x04 mem64 PCI: 00:19.0 10 <- [0x00f0400000 - 0x00f041ffff] size 0x00020000 gran 0x11 mem PCI: 00:19.0 14 <- [0x00f0434000 - 0x00f0434fff] size 0x00001000 gran 0x0c mem PCI: 00:19.0 18 <- [0x0000001040 - 0x000000105f] size 0x00000020 gran 0x05 io PCI: 00:1a.0 10 <- [0x00f0435800 - 0x00f0435bff] size 0x00000400 gran 0x0a mem PCI: 00:1b.0 10 <- [0x00f0430000 - 0x00f0433fff] size 0x00004000 gran 0x0e mem64 PCI: 00:1d.0 10 <- [0x00f0435c00 - 0x00f0435fff] size 0x00000400 gran 0x0a mem PCI: 00:1f.2 10 <- [0x00000010a0 - 0x00000010a7] size 0x00000008 gran 0x03 io PCI: 00:1f.2 14 <- [0x00000010b0 - 0x00000010b3] size 0x00000004 gran 0x02 io PCI: 00:1f.2 18 <- [0x00000010a8 - 0x00000010af] size 0x00000008 gran 0x03 io PCI: 00:1f.2 1c <- [0x00000010b4 - 0x00000010b7] size 0x00000004 gran 0x02 io PCI: 00:1f.2 20 <- [0x0000001060 - 0x000000107f] size 0x00000020 gran 0x05 io PCI: 00:1f.2 24 <- [0x00f0435000 - 0x00f04357ff] size 0x00000800 gran 0x0b mem PCI: 00:1f.3 10 <- [0x00f0436000 - 0x00f04360ff] size 0x00000100 gran 0x08 mem64 PCI: 00:1f.3 20 <- [0x0000001080 - 0x000000109f] size 0x00000020 gran 0x05 io PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: acac PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0 PCI_DOMAIN: 0000 resource base 1000 size b8 align 6 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base e0000000 size 10436120 align 28 gran 0 limit f7ffffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3 PCI_DOMAIN: 0000 resource base 100000 size baf00000 align 0 gran 0 limit 0 flags e0004200 index 4 PCI_DOMAIN: 0000 resource base 100000000 size 140500000 align 0 gran 0 limit 0 flags e0004200 index 5 PCI_DOMAIN: 0000 resource base bb000000 size 4a00000 align 0 gran 0 limit 0 flags f0200200 index 6 PCI_DOMAIN: 0000 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 7 PCI_DOMAIN: 0000 resource base a0000 size 60000 align 0 gran 0 limit 0 flags f0200200 index 8 PCI: 00:00.0 PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf PCI: 00:01.0 PCI: 00:02.0 PCI: 00:02.0 resource base f0000000 size 400000 align 22 gran 22 limit f7ffffff flags 60000201 index 10 PCI: 00:02.0 resource base e0000000 size 10000000 align 28 gran 28 limit f7ffffff flags 60001201 index 18 PCI: 00:02.0 resource base 1000 size 40 align 6 gran 6 limit ffff flags 60000100 index 20 PCI: 00:04.0 PCI: 00:06.0 PCI: 00:14.0 PCI: 00:14.0 resource base f0420000 size 10000 align 16 gran 16 limit f7ffffff flags 60000201 index 10 PCI: 00:16.0 PCI: 00:16.0 resource base f0436100 size 10 align 4 gran 4 limit f7ffffff flags 60000201 index 10 PCI: 00:16.1 PCI: 00:16.1 resource base f0436110 size 10 align 4 gran 4 limit f7ffffff flags 60000201 index 10 PCI: 00:16.2 PCI: 00:16.3 PCI: 00:19.0 PCI: 00:19.0 resource base f0400000 size 20000 align 17 gran 17 limit f7ffffff flags 60000200 index 10 PCI: 00:19.0 resource base f0434000 size 1000 align 12 gran 12 limit f7ffffff flags 60000200 index 14 PCI: 00:19.0 resource base 1040 size 20 align 5 gran 5 limit ffff flags 60000100 index 18 PCI: 00:1a.0 PCI: 00:1a.0 resource base f0435800 size 400 align 10 gran 10 limit f7ffffff flags 60000200 index 10 PCI: 00:1b.0 PCI: 00:1b.0 resource base f0430000 size 4000 align 14 gran 14 limit f7ffffff flags 60000201 index 10 PCI: 00:1c.0 PCI: 00:1c.1 PCI: 00:1c.2 PCI: 00:1c.3 PCI: 00:1c.4 PCI: 00:1c.5 PCI: 00:1c.6 PCI: 00:1c.7 PCI: 00:1d.0 PCI: 00:1d.0 resource base f0435c00 size 400 align 10 gran 10 limit f7ffffff flags 60000200 index 10 PCI: 00:1f.0 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:1f.2 PCI: 00:1f.2 resource base 10a0 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 00:1f.2 resource base 10b0 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 PCI: 00:1f.2 resource base 10a8 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 PCI: 00:1f.2 resource base 10b4 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c PCI: 00:1f.2 resource base 1060 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 PCI: 00:1f.2 resource base f0435000 size 800 align 11 gran 11 limit f7ffffff flags 60000200 index 24 PCI: 00:1f.3 PCI: 00:1f.3 resource base f0436000 size 100 align 8 gran 8 limit f7ffffff flags 60000201 index 10 PCI: 00:1f.3 resource base 1080 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 PCI: 00:1f.5 PCI: 00:1f.6 Done allocating resources. POST: 0x88 Enabling resources... PCI: 00:00.0 subsystem <- 0000/0000 PCI: 00:00.0 cmd <- 06 PCI: 00:02.0 subsystem <- 0000/0000 PCI: 00:02.0 cmd <- 03 PCI: 00:14.0 subsystem <- 0000/0000 PCI: 00:14.0 cmd <- 102 PCI: 00:16.0 subsystem <- 0000/0000 PCI: 00:16.0 cmd <- 02 PCI: 00:16.1 subsystem <- 0000/0000 PCI: 00:16.1 cmd <- 02 PCI: 00:19.0 subsystem <- 0000/0000 PCI: 00:19.0 cmd <- 103 PCI: 00:1a.0 subsystem <- 0000/0000 PCI: 00:1a.0 cmd <- 102 PCI: 00:1b.0 subsystem <- 0000/0000 PCI: 00:1b.0 cmd <- 102 PCI: 00:1d.0 subsystem <- 0000/0000 PCI: 00:1d.0 cmd <- 102 pch_decode_init PCI: 00:1f.0 subsystem <- 0000/0000 PCI: 00:1f.0 cmd <- 107 PCI: 00:1f.2 subsystem <- 0000/0000 PCI: 00:1f.2 cmd <- 03 PCI: 00:1f.3 subsystem <- 0000/0000 PCI: 00:1f.3 cmd <- 103 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init start_eip=0x00001000, code_size=0x00000031 Initializing CPU #0 CPU: vendor Intel device 306a9 CPU: family 06, model 3a, stepping 09 POST: 0x60 Enabling cache CBFS: Looking for 'cpu_microcode_blob.bin' CBFS: found. microcode: sig=0x306a9 pf=0x10 revision=0x17 microcode: updated to revision 0x17 date=2013-01-09 CPU: Intel(R) Core(TM) i7-3720QM CPU @ 2.60GHz. Setting fixed MTRRs(0-88) Type: UC Setting fixed MTRRs(0-16) Type: WB DONE fixed MTRRs call enable_fixed_mtrr() Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB Setting variable MTRR 1, base: 2048MB, range: 512MB, type WB Setting variable MTRR 2, base: 2560MB, range: 256MB, type WB Setting variable MTRR 3, base: 2816MB, range: 128MB, type WB Setting variable MTRR 4, base: 2944MB, range: 64MB, type WB Adding hole at 2992MB-3008MB Setting variable MTRR 5, base: 2992MB, range: 16MB, type UC Zero-sized MTRR range @0KB Allocate an msr - basek = 00400000, sizek = 00501400, Setting variable MTRR 6, base: 4096MB, range: 4096MB, type WB Setting variable MTRR 7, base: 8192MB, range: 1024MB, type WB Running out of variable MTRRs! Adding hole at 9221MB-9280MB Warning: Out of MTRRs for base: 9221MB, range: 59MB, type UC Zero-sized MTRR range @0KB DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x00 done. POST: 0x9b model_x06ax: energy policy set to 6 model_x06ax: frequency set to 2600 Turbo is available but hidden Turbo has been enabled CPU: 0 has 8 cores 2 threads memalign Enter, boundary 8, size 148, free_mem_ptr 001a0a00 memalign 001a0a00 CPU: 0 has core 1 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 2. Sending STARTUP #1 to 1. After apic_write. Initializing CPU #1 Startup point 1. CPU: vendor Intel device 306a9 Waiting for send to finish... CPU: family 06, model 3a, stepping 09 +POST: 0xSending STARTUP #2 to 1. 60After apic_write. Enabling cache Startup point 1. Waiting for send to finish... +CBFS: Looking for 'cpu_microcode_blob.bin' After Startup. CBFS: found. memalign Enter, boundary 8, size 148, free_mem_ptr 001a0a94 memalign 001a0a98 microcode: sig=0x306a9 pf=0x10 revision=0x17 CPU: 0 has core 2 microcode: updated to revision 0x17 date=2013-01-09 Asserting INIT. CPU: Intel(R) Core(TM) i7-3720QM CPU @ 2.60GHz. Waiting for send to finish... + Setting fixed MTRRs(0-88) Type: UC Setting fixed MTRRs(0-16) Type: WB Deasserting INIT. DONE fixed MTRRs call enable_fixed_mtrr() Waiting for send to finish... +Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB #startup loops: 2. Sending STARTUP #1 to 2. Setting variable MTRR 1, base: 2048MB, range: 512MB, type WB After apic_write. Setting variable MTRR 2, base: 2560MB, range: 256MB, type WB Startup point 1. Waiting for send to finish... +Setting variable MTRR 3, base: 2816MB, range: 128MB, type WB Sending STARTUP #2 to 2. Setting variable MTRR 4, base: 2944MB, range: 64MB, type WB Adding hole at 2992MB-3008MB After apic_write. Setting variable MTRR 5, base: 2992MB, range: 16MB, type UC Startup point 1. Waiting for send to finish... +Zero-sized MTRR range @0KB Allocate an msr - basek = 00400000, sizek = 00501400, After Startup. Setting variable MTRR 6, base: 4096MB, range: 4096MB, type WB memalign Enter, boundary 8, size 148, free_mem_ptr 001a0b2c Setting variable MTRR 7, base: 8192MB, range: 1024MB, type WB Running out of variable MTRRs! memalign 001a0b30 Adding hole at 9221MB-9280MB Warning: Out of MTRRs for base: 9221MB, range: 59MB, type UC Zero-sized MTRR range @0KB DONE variable MTRRs Clear out the extra MTRR's Initializing CPU #2 call enable_var_mtrr() CPU: 0 has core 3 Asserting INIT. Leave x86_setup_var_mtrrs POST: 0x6a Waiting for send to finish... + MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 CPU: vendor Intel device 306a9 Setting up local apic...Deasserting INIT. apic_id: 0x01 done. POST: 0x9b CPU: family 06, model 3a, stepping 09 model_x06ax: energy policy set to 6 Waiting for send to finish... +model_x06ax: frequency set to 2600 #startup loops: 2. Sending STARTUP #1 to 3. CPU #1 initialized After apic_write. POST: 0xStartup point 1. Waiting for send to finish... +60Initializing CPU #3 Sending STARTUP #2 to 3. After apic_write. CPU: vendor Intel device 306a9 Startup point 1. Waiting for send to finish... +CPU: family 06, model 3a, stepping 09 After Startup. memalign Enter, boundary 8, size 148, free_mem_ptr 001a0bc4 memalign 001a0bc8 CPU: 0 has core 4 Asserting INIT. Waiting for send to finish... +POST: 0x 60Enabling cache CBFS: Looking for 'cpu_microcode_blob.bin' Enabling cache CBFS: found. CBFS: Looking for 'cpu_microcode_blob.bin' microcode: sig=0x306a9 pf=0x10 revision=0x17 CBFS: found. microcode: updated to revision 0x17 date=2013-01-09 microcode: sig=0x306a9 pf=0x10 revision=0x17 CPU: Intel(R) Core(TM) i7-3720QM CPU @ 2.60GHz. microcode: updated to revision 0x17 date=2013-01-09 Setting fixed MTRRs(0-88) Type: UC CPU: Intel(R) Core(TM) i7-3720QM CPU @ 2.60GHz. Setting fixed MTRRs(0-16) Type: WB Setting fixed MTRRs(0-88) Type: UC DONE fixed MTRRs Deasserting INIT. call enable_fixed_mtrr() Setting fixed MTRRs(0-16) Type: WB Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB DONE fixed MTRRs Setting variable MTRR 1, base: 2048MB, range: 512MB, type WB call enable_fixed_mtrr() Setting variable MTRR 2, base: 2560MB, range: 256MB, type WB Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB Setting variable MTRR 3, base: 2816MB, range: 128MB, type WB Setting variable MTRR 1, base: 2048MB, range: 512MB, type WB Setting variable MTRR 4, base: 2944MB, range: 64MB, type WB Setting variable MTRR 2, base: 2560MB, range: 256MB, type WB Adding hole at 2992MB-3008MB Setting variable MTRR 3, base: 2816MB, range: 128MB, type WB Setting variable MTRR 5, base: 2992MB, range: 16MB, type UC Setting variable MTRR 4, base: 2944MB, range: 64MB, type WB Zero-sized MTRR range @0KB Allocate an msr - basek = 00400000, sizek = 00501400, Adding hole at 2992MB-3008MB Setting variable MTRR 6, base: 4096MB, range: 4096MB, type WB Setting variable MTRR 5, base: 2992MB, range: 16MB, type UC Setting variable MTRR 7, base: 8192MB, range: 1024MB, type WB Zero-sized MTRR range @0KB Allocate an msr - basek = 00400000, sizek = 00501400, Running out of variable MTRRs! Setting variable MTRR 6, base: 4096MB, range: 4096MB, type WB Adding hole at 9221MB-9280MB Setting variable MTRR 7, base: 8192MB, range: 1024MB, type WB Running out of variable MTRRs! Adding hole at 9221MB-9280MB Warning: Out of MTRRs for base: 9221MB, range: 59MB, type UC Warning: Out of MTRRs for base: 9221MB, range: 59MB, type UC Zero-sized MTRR range @0KB DONE variable MTRRs Clear out the extra MTRR's Zero-sized MTRR range @0KB call enable_var_mtrr() DONE variable MTRRs Clear out the extra MTRR's Leave x86_setup_var_mtrrs call enable_var_mtrr() POST: 0x6a Leave x86_setup_var_mtrrs POST: 0x6a MTRR check MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic...Setting up local apic... apic_id: 0x02 done. POST: 0x9b apic_id: 0x03 done. POST: 0x9b model_x06ax: energy policy set to 6 model_x06ax: energy policy set to 6 model_x06ax: frequency set to 2600 model_x06ax: frequency set to 2600 CPU #2 initialized CPU #3 initialized Waiting for send to finish... +#startup loops: 2. Sending STARTUP #1 to 4. After apic_write. Initializing CPU #4 Startup point 1. Waiting for send to finish... +CPU: vendor Intel device 306a9 Sending STARTUP #2 to 4. After apic_write. CPU: family 06, model 3a, stepping 09 Startup point 1. Waiting for send to finish... +POST: 0xAfter Startup. memalign Enter, boundary 8, size 148, free_mem_ptr 001a0c5c memalign 001a0c60 CPU: 0 has core 5 Asserting INIT. Waiting for send to finish... +60 Enabling cache CBFS: Looking for 'cpu_microcode_blob.bin' CBFS: found. microcode: sig=0x306a9 pf=0x10 revision=0x17 Deasserting INIT. Waiting for send to finish... +#startup loops: 2. Sending STARTUP #1 to 5. After apic_write. microcode: updated to revision 0x17 date=2013-01-09 Startup point 1. Waiting for send to finish... +Initializing CPU #5 Sending STARTUP #2 to 5. After apic_write. CPU: vendor Intel device 306a9 Startup point 1. Waiting for send to finish... +CPU: Intel(R) Core(TM) i7-3720QM CPU @ 2.60GHz. After Startup. memalign Enter, boundary 8, size 148, free_mem_ptr 001a0cf4 memalign 001a0cf8 CPU: 0 has core 6 Asserting INIT. Waiting for send to finish... + CPU: family 06, model 3a, stepping 09 Setting fixed MTRRs(0-88) Type: UC POST: 0x60Deasserting INIT. Waiting for send to finish... +Setting fixed MTRRs(0-16) Type: WB #startup loops: 2. Sending STARTUP #1 to 6. After apic_write. DONE fixed MTRRs Startup point 1. Waiting for send to finish... +call enable_fixed_mtrr() Sending STARTUP #2 to 6. After apic_write. Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB Startup point 1. Waiting for send to finish... +Initializing CPU #6 After Startup. memalign Enter, boundary 8, size 148, free_mem_ptr 001a0d8c memalign 001a0d90 CPU: 0 has core 7 Asserting INIT. Waiting for send to finish... +CPU: vendor Intel device 306a9 CPU: family 06, model 3a, stepping 09 Setting variable MTRR 1, base: 2048MB, range: 512MB, type WB Deasserting INIT. Waiting for send to finish... +POST: 0x#startup loops: 2. Sending STARTUP #1 to 7. After apic_write. Enabling cache Startup point 1. Waiting for send to finish... +CBFS: Looking for 'cpu_microcode_blob.bin' Sending STARTUP #2 to 7. After apic_write. CBFS: found. Setting variable MTRR 2, base: 2560MB, range: 256MB, type WB microcode: sig=0x306a9 pf=0x10 revision=0x17 Startup point 1. Waiting for send to finish... +Initializing CPU #7 After Startup. CPU #0 initialized Waiting for 4 CPUS to stop Setting variable MTRR 3, base: 2816MB, range: 128MB, type WB microcode: updated to revision 0x17 date=2013-01-09 Setting variable MTRR 4, base: 2944MB, range: 64MB, type WB CPU: Intel(R) Core(TM) i7-3720QM CPU @ 2.60GHz. Setting fixed MTRRs(0-88) Type: UC Adding hole at 2992MB-3008MB 60CPU: vendor Intel device 306a9 Setting fixed MTRRs(0-16) Type: WB Setting variable MTRR 5, base: 2992MB, range: 16MB, type UC DONE fixed MTRRs call enable_fixed_mtrr() Zero-sized MTRR range @0KB Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB Allocate an msr - basek = 00400000, sizek = 00501400, Setting variable MTRR 1, base: 2048MB, range: 512MB, type WB Setting variable MTRR 6, base: 4096MB, range: 4096MB, type WB Setting variable MTRR 2, base: 2560MB, range: 256MB, type WB Setting variable MTRR 7, base: 8192MB, range: 1024MB, type WB Running out of variable MTRRs! Setting variable MTRR 3, base: 2816MB, range: 128MB, type WB Adding hole at 9221MB-9280MB Warning: Out of MTRRs for base: 9221MB, range: 59MB, type UC Zero-sized MTRR range @0KB DONE variable MTRRs Clear out the extra MTRR's Setting variable MTRR 4, base: 2944MB, range: 64MB, type WB call enable_var_mtrr() Adding hole at 2992MB-3008MB Leave x86_setup_var_mtrrs POST: 0x6a CPU: family 06, model 3a, stepping 09 Setting variable MTRR 5, base: 2992MB, range: 16MB, type UC MTRR check Fixed MTRRs : Zero-sized MTRR range @0KB Allocate an msr - basek = 00400000, sizek = 00501400, Enabled Setting variable MTRR 6, base: 4096MB, range: 4096MB, type WB Variable MTRRs: Setting variable MTRR 7, base: 8192MB, range: 1024MB, type WB Running out of variable MTRRs! Adding hole at 9221MB-9280MB Warning: Out of MTRRs for base: 9221MB, range: 59MB, type UC Zero-sized MTRR range @0KB Enabled POST: 0x93 DONE variable MTRRs Clear out the extra MTRR's Setting up local apic...call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a apic_id: 0x04 done. POST: 0x9b MTRR check Fixed MTRRs : model_x06ax: energy policy set to 6 Enabled Variable MTRRs: Enabled POST: 0x93 POST: 0xmodel_x06ax: frequency set to 2600 Setting up local apic...CPU #4 initialized apic_id: 0x05 done. POST: 0x9b Waiting for 3 CPUS to stop model_x06ax: energy policy set to 6 model_x06ax: frequency set to 2600 CPU #5 initialized 60Waiting for 2 CPUS to stop Enabling cache CBFS: Looking for 'cpu_microcode_blob.bin' Enabling cache CBFS: found. CBFS: Looking for 'cpu_microcode_blob.bin' microcode: sig=0x306a9 pf=0x10 revision=0x17 CBFS: found. microcode: updated to revision 0x17 date=2013-01-09 microcode: sig=0x306a9 pf=0x10 revision=0x17 CPU: Intel(R) Core(TM) i7-3720QM CPU @ 2.60GHz. microcode: updated to revision 0x17 date=2013-01-09 Setting fixed MTRRs(0-88) Type: UC CPU: Intel(R) Core(TM) i7-3720QM CPU @ 2.60GHz. Setting fixed MTRRs(0-16) Type: WB Setting fixed MTRRs(0-88) Type: UC DONE fixed MTRRs call enable_fixed_mtrr() Setting fixed MTRRs(0-16) Type: WB Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB DONE fixed MTRRs Setting variable MTRR 1, base: 2048MB, range: 512MB, type WB call enable_fixed_mtrr() Setting variable MTRR 2, base: 2560MB, range: 256MB, type WB Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB Setting variable MTRR 3, base: 2816MB, range: 128MB, type WB Setting variable MTRR 1, base: 2048MB, range: 512MB, type WB Setting variable MTRR 4, base: 2944MB, range: 64MB, type WB Setting variable MTRR 2, base: 2560MB, range: 256MB, type WB Adding hole at 2992MB-3008MB Setting variable MTRR 3, base: 2816MB, range: 128MB, type WB Setting variable MTRR 5, base: 2992MB, range: 16MB, type UC Setting variable MTRR 4, base: 2944MB, range: 64MB, type WB Zero-sized MTRR range @0KB Allocate an msr - basek = 00400000, sizek = 00501400, Adding hole at 2992MB-3008MB Setting variable MTRR 6, base: 4096MB, range: 4096MB, type WB Setting variable MTRR 5, base: 2992MB, range: 16MB, type UC Setting variable MTRR 7, base: 8192MB, range: 1024MB, type WB Zero-sized MTRR range @0KB Allocate an msr - basek = 00400000, sizek = 00501400, Running out of variable MTRRs! Setting variable MTRR 6, base: 4096MB, range: 4096MB, type WB Adding hole at 9221MB-9280MB Setting variable MTRR 7, base: 8192MB, range: 1024MB, type WB Running out of variable MTRRs! Adding hole at 9221MB-9280MB Warning: Out of MTRRs for base: 9221MB, range: 59MB, type UC Warning: Out of MTRRs for base: 9221MB, range: 59MB, type UC Zero-sized MTRR range @0KB DONE variable MTRRs Clear out the extra MTRR's Zero-sized MTRR range @0KB call enable_var_mtrr() DONE variable MTRRs Clear out the extra MTRR's Leave x86_setup_var_mtrrs call enable_var_mtrr() POST: 0x6a Leave x86_setup_var_mtrrs POST: 0x6a MTRR check MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic...Setting up local apic... apic_id: 0x06 done. POST: 0x9b apic_id: 0x07 done. POST: 0x9b model_x06ax: energy policy set to 6 model_x06ax: energy policy set to 6 model_x06ax: frequency set to 2600 model_x06ax: frequency set to 2600 CPU #6 initialized CPU #7 initialized Waiting for 1 CPUS to stop All AP CPUs stopped (46756 loops) PCI: 00:00.0 init PCI: 00:02.0 init GT Power Management Init IVB GT2 35W Power Meter Weights CBFS: Looking for 'pci8086,0166.rom' CBFS: found. In CBFS, ROM address for PCI: 00:02.0 = ff807978 PCI expansion ROM, signature 0xaa55, INIT size 0x10000, data ptr 0x0040 PCI ROM image, vendor ID 8086, device ID 0106, PCI ROM image, Class Code 030000, Code Type 00 Copying VGA ROM Image from ff807978 to 0xc0000, 0x10000 bytes Real mode stub @00000600: 867 bytes Calling Option ROM... oprom: INT# 0x15 oprom: eax: a0005f34 ebx: 00000190 ecx: 00000002 edx: e0000000 oprom: ebp: 0019fe9c esp: 00000fba edi: 00000080 esi: 00042000 oprom: ip: 5823 cs: c000 flags: 00000046 Unsupported software interrupt #0x15 eax 0xa0005f34 int15 call returned error. oprom: INT# 0x15 oprom: eax: a0005fac ebx: 00000190 ecx: 00000000 edx: e00000c0 oprom: ebp: 0019fe9c esp: 00000fba edi: 00000080 esi: 0004f053 oprom: ip: 5823 cs: c000 flags: 00000046 Unsupported software interrupt #0x15 eax 0xa0005fac int15 call returned error. oprom: INT# 0x15 oprom: eax: 00005f51 ebx: 0000c000 ecx: 00000000 edx: 000003da oprom: ebp: 0019fe9c esp: 00000fb8 edi: 00000cac esi: 00000c28 oprom: ip: 5823 cs: c000 flags: 00000046 Unsupported software interrupt #0x15 eax 0x5f51 int15 call returned error. oprom: INT# 0x15 oprom: eax: 00005f40 ebx: 00000000 ecx: 00000004 edx: 00000001 oprom: ebp: 0019fe9c esp: 00000fb2 edi: 00006953 esi: 000e1180 oprom: ip: 5823 cs: c000 flags: 00000046 Unsupported software interrupt #0x15 eax 0x5f40 int15 call returned error. oprom: INT# 0x15 oprom: eax: 00005f52 ebx: 00000000 ecx: 00000002 edx: 00000008 oprom: ebp: 0019fe9c esp: 00000f94 edi: 000069d7 esi: 000e0c28 oprom: ip: 5823 cs: c000 flags: 00000046 Unsupported software interrupt #0x15 eax 0x5f52 int15 call returned error. oprom: INT# 0x15 oprom: eax: 00005f49 ebx: 00001696 ecx: 00000000 edx: 0000fde8 oprom: ebp: 0019fe9c esp: 00000fa8 edi: 00001aec esi: 000e1aec oprom: ip: 5823 cs: c000 flags: 00000046 Unsupported software interrupt #0x15 eax 0x5f49 int15 call returned error. oprom: INT# 0x15 oprom: eax: 13125f49 ebx: 000000ff ecx: 13121300 edx: 00000068 oprom: ebp: 0019fe9c esp: 00000f8e edi: 00001aec esi: 000e1b42 oprom: ip: 5823 cs: c000 flags: 00000046 Unsupported software interrupt #0x15 eax 0x13125f49 int15 call returned error. oprom: INT# 0x15 oprom: eax: 00005f14 ebx: 0000078f ecx: 0000000a edx: 0000fde8 oprom: ebp: 0019fe9c esp: 00000faa edi: 00006953 esi: 000e1180 oprom: ip: 5823 cs: c000 flags: 00000046 Unsupported software interrupt #0x15 eax 0x5f14 int15 call returned error. oprom: INT# 0x15 oprom: eax: 00805f35 ebx: 0000c000 ecx: 00000002 edx: 000003da oprom: ebp: 0019fe9c esp: 00000fbc edi: 00000080 esi: 00000000 oprom: ip: 5823 cs: c000 flags: 00000046 Unsupported software interrupt #0x15 eax 0x805f35 int15 call returned error. ... Option ROM returned. GT Power Management Init (post VBIOS) PCI: 00:14.0 init CBFS: Looking for 'pci8086,1e31.rom' CBFS: Could not find file 'pci8086,1e31.rom'. PCI: 00:16.0 init CBFS: Looking for 'pci8086,1e3a.rom' CBFS: Could not find file 'pci8086,1e3a.rom'. PCI: 00:16.1 init CBFS: Looking for 'pci8086,1e3b.rom' CBFS: Could not find file 'pci8086,1e3b.rom'. PCI: 00:19.0 init CBFS: Looking for 'pci8086,1502.rom' CBFS: Could not find file 'pci8086,1502.rom'. PCI: 00:1a.0 init CBFS: Looking for 'pci8086,1e2d.rom' CBFS: Could not find file 'pci8086,1e2d.rom'. PCI: 00:1b.0 init CBFS: Looking for 'pci8086,1e20.rom' CBFS: Could not find file 'pci8086,1e20.rom'. PCI: 00:1d.0 init CBFS: Looking for 'pci8086,1e26.rom' CBFS: Could not find file 'pci8086,1e26.rom'. PCI: 00:1f.0 init pch: lpc_init Southbridge APIC ID = 2 Dumping IOAPIC registers reg 0x0000: 0x02000000 reg 0x0001: 0x00170020 reg 0x0002: 0x00170020 Set power off after power failure. NMI sources disabled. PantherPoint PM init rtc_failed = 0x0 RTC Init i8259_configure_irq_trigger: current interrupts are 0x0 i8259_configure_irq_trigger: try to set interrupts 0x200 Enabling BIOS updates outside of SMM... PCI: 00:1f.2 init CBFS: Looking for 'pci8086,1e03.rom' CBFS: Could not find file 'pci8086,1e03.rom'. PCI: 00:1f.3 init CBFS: Looking for 'pci8086,1e22.rom' CBFS: Could not find file 'pci8086,1e22.rom'. Devices initialized Show all devs...After init. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 APIC: acac: enabled 0 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 0 PCI: 00:02.0: enabled 1 PCI: 00:04.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:14.0: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.1: enabled 1 PCI: 00:16.2: enabled 0 PCI: 00:16.3: enabled 0 PCI: 00:19.0: enabled 1 PCI: 00:1a.0: enabled 1 PCI: 00:1b.0: enabled 1 PCI: 00:1c.0: enabled 0 PCI: 00:1c.1: enabled 0 PCI: 00:1c.2: enabled 0 PCI: 00:1c.3: enabled 0 PCI: 00:1c.4: enabled 0 PCI: 00:1c.5: enabled 0 PCI: 00:1c.6: enabled 0 PCI: 00:1c.7: enabled 0 PCI: 00:1d.0: enabled 1 PCI: 00:1f.0: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 1 PCI: 00:1f.5: enabled 0 PCI: 00:1f.6: enabled 0 APIC: 01: enabled 1 APIC: 02: enabled 1 APIC: 03: enabled 1 APIC: 04: enabled 1 APIC: 05: enabled 1 APIC: 06: enabled 1 APIC: 07: enabled 1 POST: 0x89 Re-Initializing CBMEM area to 0xbafe0000 Initializing CBMEM area to 0xbafe0000 (131072 bytes) Adding CBMEM entry as no. 1 Moving GDT to bafe0200...ok High Tables Base is bafe0000. POST: 0x9a Copying Interrupt Routing Table to 0x000f0000... done. Verifying copy of Interrupt Routing Table at 0x000f0000... done Checking Interrupt Routing Table consistency... Inconsistent Interrupt Routing Table size (0x140/0x110). check_pirq_routing_table(): Interrupt Routing Table located at 000f0000. Interrupt Routing Table checksum is: 0xf5 but should be: 0x5e. done. Adding CBMEM entry as no. 2 Copying Interrupt Routing Table to 0xbafe0400... done. Verifying copy of Interrupt Routing Table at 0xbafe0400... done Checking Interrupt Routing Table consistency... Inconsistent Interrupt Routing Table size (0x140/0x110). check_pirq_routing_table(): Interrupt Routing Table located at bafe0400. Interrupt Routing Table checksum is: 0xf5 but should be: 0x4d. done. PIRQ table: 272 bytes. POST: 0x9b Wrote the mp table end at: 000f0410 - 000f0634 Adding CBMEM entry as no. 3 Wrote the mp table end at: bafe1410 - bafe1634 MP table: 564 bytes. Adding CBMEM entry as no. 4 smbios_write_tables: bafe2400 Root Device (Intel Cougar Canyon 2 platform) APIC_CLUSTER: 0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge) APIC: 00 (Socket rPGA989 CPU) APIC: acac (Intel SandyBridge/IvyBridge CPU) PCI_DOMAIN: 0000 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge) PCI: 00:00.0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge) PCI: 00:01.0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge) PCI: 00:02.0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge) PCI: 00:04.0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge) PCI: 00:06.0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge) PCI: 00:14.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) PCI: 00:16.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) PCI: 00:16.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) PCI: 00:16.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) PCI: 00:16.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) PCI: 00:19.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) PCI: 00:1a.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) PCI: 00:1b.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) PCI: 00:1c.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) PCI: 00:1c.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) PCI: 00:1c.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) PCI: 00:1c.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) PCI: 00:1c.4 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) PCI: 00:1c.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) PCI: 00:1c.6 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) PCI: 00:1c.7 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) PCI: 00:1d.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) PCI: 00:1f.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) PCI: 00:1f.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) PCI: 00:1f.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) PCI: 00:1f.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) PCI: 00:1f.6 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge) APIC: 01 () APIC: 02 () APIC: 03 () APIC: 04 () APIC: 05 () APIC: 06 () APIC: 07 () SMBIOS tables: 300 bytes. POST: 0x9d Adding CBMEM entry as no. 5 Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500, 0x10 bytes, checksum 18e0 New low_table_end: 0x00000528 Now going to write high coreboot table at 0xbafe2c00 rom_table_end = 0xbafe2c00 Adjust low_table_end from 0x00000528 to 0x00001000 Adjust rom_table_end from 0xbafe2c00 to 0xbaff0000 Adding high table area coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000a0000-00000000000fffff: RESERVED 3. 0000000000100000-00000000bafdffff: RAM 4. 00000000bafe0000-00000000baffffff: CONFIGURATION TABLES 5. 00000000bb000000-00000000bf9fffff: RESERVED 6. 00000000f8000000-00000000fbffffff: RESERVED 7. 0000000100000000-00000002404fffff: RAM Wrote coreboot table at: bafe2c00, 0x218 bytes, checksum 31ae coreboot table: 560 bytes. POST: 0x9e POST: 0x9d Multiboot Information structure has been written. 0. FREE SPACE bafeac00 00015400 1. GDT bafe0200 00000200 2. IRQ TABLE bafe0400 00001000 3. SMP TABLE bafe1400 00001000 4. SMBIOS bafe2400 00000800 5. COREBOOT bafe2c00 00008000 CBFS: Looking for 'fallback/payload' CBFS: found. Got a payload CPU0: stack from 00198000 to 001a0000:Lowest stack address 0019fb68 Loading segment from rom address 0xff837cb8 code (compression=1) memalign Enter, boundary 8, size 28, free_mem_ptr 001a0e24 memalign 001a0e28 New segment dstaddr 0xdeebc memsize 0x21144 srcaddr 0xff837cf0 filesize 0x10aa8 (cleaned up) New segment addr 0xdeebc size 0x21144 offset 0xff837cf0 filesize 0x10aa8 Loading segment from rom address 0xff837cd4 Entry Point 0x00000000 Payload (probably SeaBIOS) loaded into a reserved area in the lower 1MB Loading Segment: addr: 0x00000000000deebc memsz: 0x0000000000021144 filesz: 0x0000000000010aa8 lb: [0x0000000000100000, 0x00000000001a4000) Post relocation: addr: 0x00000000000deebc memsz: 0x0000000000021144 filesz: 0x0000000000010aa8 using LZMA [ 0x000deebc, 00100000, 0x00100000) <- ff837cf0 dest 000deebc, end 00100000, bouncebuffer bae98000 Loaded segments Jumping to boot code at fd48e POST: 0xf8 entry = 0x000fd48e lb_start = 0x00100000 lb_size = 0x000a4000 adjust = 0xbae3c000 buffer = 0xbae98000 elf_boot_notes = 0x00118c48 adjusted_boot_notes = 0xbaf54c48 Start bios (version rel-1.7.3-74-g3061815-20131009_140943-localhost.localdomain) No Xen hypervisor found. Unable to unlock ram - bridge not found Ram Size=0xb0000000 (0x0000000000000000 high) Relocating init from 0x000e04e1 to 0xaffdf6f0 (size 67663) CPU Mhz=2596 === PCI bus & bridge init === PCI: pci_bios_init_bus_rec bus = 0x0 === PCI device probing === Found 12 PCI devices (max PCI bus is 00) === PCI new allocation pass #1 === PCI: check devices === PCI new allocation pass #2 === PCI: map device bdf=00:02.0 bar 4, addr 0000c000, size ffff0040 [io] PCI: map device bdf=00:1f.2 bar 4, addr ffffc040, size ffff0020 [io] PCI: map device bdf=00:1f.3 bar 4, addr 1fffec060, size ffff0020 [io] PCI: map device bdf=00:1f.2 bar 0, addr 2fffdc080, size ffff0008 [io] PCI: map device bdf=00:1f.2 bar 2, addr 3fffcc088, size ffff0008 [io] PCI: map device bdf=00:1f.2 bar 1, addr 4fffbc090, size ffff0004 [io] PCI: map device bdf=00:1f.2 bar 3, addr 5fffac094, size ffff0004 [io] PCI: map device bdf=00:19.0 bar 2, addr 6fff9c098, size 00000020 [io] PCI: map device bdf=00:02.0 bar 0, addr fe400000, size 00400000 [mem] PCI: map device bdf=00:19.0 bar 0, addr fe800000, size 00020000 [mem] PCI: map device bdf=00:14.0 bar 0, addr fe820000, size 00010000 [mem] PCI: map device bdf=00:1b.0 bar 0, addr fe830000, size 00004000 [mem] PCI: map device bdf=00:16.0 bar 0, addr fe834000, size 00001000 [mem] PCI: map device bdf=00:16.1 bar 0, addr fe835000, size 00001000 [mem] PCI: map device bdf=00:19.0 bar 1, addr fe836000, size 00001000 [mem] PCI: map device bdf=00:1a.0 bar 0, addr fe837000, size 00001000 [mem] PCI: map device bdf=00:1d.0 bar 0, addr fe838000, size 00001000 [mem] PCI: map device bdf=00:1f.2 bar 5, addr fe839000, size 00001000 [mem] PCI: map device bdf=00:1f.3 bar 0, addr fe83a000, size 00001000 [mem] PCI: map device bdf=00:02.0 bar 2, addr e0000000, size 10000000 [prefmem] PCI: init bdf=00:00.0 id=8086:0154 PCI: init bdf=00:02.0 id=8086:0166 pci_slot_get_irq called with unknown routing PCI: init bdf=00:14.0 id=8086:1e31 pci_slot_get_irq called with unknown routing PCI: init bdf=00:16.0 id=8086:1e3a pci_slot_get_irq called with unknown routing PCI: init bdf=00:16.1 id=8086:1e3b pci_slot_get_irq called with unknown routing PCI: init bdf=00:19.0 id=8086:1502 pci_slot_get_irq called with unknown routing PCI: init bdf=00:1a.0 id=8086:1e2d pci_slot_get_irq called with unknown routing PCI: init bdf=00:1b.0 id=8086:1e20 pci_slot_get_irq called with unknown routing PCI: init bdf=00:1d.0 id=8086:1e26 pci_slot_get_irq called with unknown routing PCI: init bdf=00:1f.0 id=8086:1e57 PCI: init bdf=00:1f.2 id=8086:1e03 pci_slot_get_irq called with unknown routing PCI: init bdf=00:1f.3 id=8086:1e22 pci_slot_get_irq called with unknown routing PCI: Using 00:02.0 for primary VGA WARNING - Unable to allocate resource at wrmsr_smp:31! WARNING - Unable to allocate resource at wrmsr_smp:31! WARNING - Unable to allocate resource at wrmsr_smp:31! Found 1 cpu(s) max supported 1 cpu(s) MP table addr=0x000f0c00 MPC table addr=0x000f0c10 size=280 SMBIOS ptr=0x000f0be0 table=0x000f0ad0 size=263 XHCI init on dev 00:14.0: regs @ 0xfe820000, 8 ports, 32 slots XHCI protocol USB 2.00, 4 ports (offset 1) XHCI protocol USB 3.00, 4 ports (offset 5) XHCI extcap 0xc1 @ fe828040 XHCI extcap 0xc0 @ fe828070 XHCI extcap 0x1 @ fe828330 EHCI init on dev 00:1a.0 (regs=0xfe837020) EHCI init on dev 00:1d.0 (regs=0xfe838020) Found 0 lpt ports Found 1 serial ports AHCI controller at 1f.2, iobase fe839000, irq 255 Scan for VGA option rom Scan for option roms Press F12 for boot menu. XHCI no devices found PS2 keyboard initialized USB keyboard initialized Initialized USB HUB (1 ports used) Initialized USB HUB (0 ports used) Searching bootorder for: /pci@i0cf8/*@1f,2/drive@0/disk@0 AHCI/0: registering: "AHCI/0: ST3400633AS ATA-7 Hard-Disk (372 GiBytes)" All threads complete. Searching bootorder for: HALT drive 0x000f0a60: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=781422768 Space available for UMB: c0000-ee000, f0000-f0a60 Returned 57344 bytes of ZoneHigh e820 map has 6 items: 0: 0000000000000000 - 000000000009fc00 = 1 RAM 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED 3: 0000000000100000 - 00000000afffe000 = 1 RAM 4: 00000000afffe000 - 00000000b0000000 = 2 RESERVED 5: 00000000fffc0000 - 0000000100000000 = 2 RESERVED Unable to lock ram - bridge not found enter handle_19: NULL Booting from Hard Disk... Booting from 0000:7c00