I found a dram
compatibility issue of coreboot.
My platform setup
is Atom+945GSE+ICH7M+IT8718.
I have two
SO-DIMMs. First one is PC2-5300, 512MB, and made by Apacer. Second one
is the PC2-4200, 512MB, and made by Nanya .
My coreboot with the
first SO-DIMM can boot until the payload stage. System will received a software
reset and reset itself repeat again.
My coreboot with the
second slow SO-DIMM can boot and load my payload
successfully.
So I think it
is a compatibility issue.
Is there anyone can
explain the issue in case same infinite reset loop happen
again.
Thanks.
Here are the partial
log:
First
SO-DIMM:
======================================
coreboot-2.0.0-r Thu
Dec 3 18:06:23 CST 2009 starting...
Mobile Intel(R)
82945GMS/GU Express Chipset
(G)MCH capable of up to FSB 667 MHz
(G)MCH
capable of up to DDR2-533
Setting up static southbridge registers... GPIOS...
done.
Disabling Watchdog reboot... done.
Setting up static northbridge
registers... done.
Waiting for MCHBAR to come up...ok
PM1_CNT:
00001c00
SMBus controller enabled.
dimm 50
00: 80 08
08 0e 0a 60 40 00 05 30 45 00 82 08 00 00
10: 0c 04 38 01 04 00 03 3d 50 50
60 3c 1e 3c 2d 80
20: 20 27 10 17 3c 1e 1e 00 00 3c 69 80 18 22 00 53
30: 78 4a 39 26 26 2b 1b 4a 20 22 00 00 00 00 12 df
40: 7f 7a 00 00 00
00 00 00 00 37 38 2e 39 32 47 36
50: 33 2e 41 46 32 ff ff ff ff ff ff 00 00
08 49 02
60: 30 84 95 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff
90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
b0: ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff
c0: ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff
d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e0: ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f0: ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff
dimm 51
00: bad
device: 01
dimm 52
00: bad device: 01
dimm 53
00: bad device: 01
SLP S4# Assertion Width Violation.
Setting up RAM
controller.
This mainboard supports Dual Channel Operation.
DDR II Channel
0 Socket 0: x8DS
DDR II Channel 1 Socket 0: N/A
lowest common cas =
3
Probing Speed 1
DIMM: 0
Current CAS mask:
0038; idx=2, tCLK=50, tAC=60: Not fast
enough!
Current CAS mask: 0030; idx=1, tCLK=3d,
tAC=50: OK
DIMM: 1
DIMM: 2
DIMM:
3
freq_cas_mask for speed 1: 0030
Memory will be driven at 533MHz
with CAS=4 clocks
tRAS = 12 cycles
tRP = 4 cycles
tRCD = 4
cycles
Refresh: 7.8us
tWR = 4 cycles
DIMM 0 side 0 = 512
MB
tRFC = 28 cycles
Setting Graphics Frequency...
FSB: 533 MHz Voltage: 1.05V Render: 166Mhz Display: 200MHz
Setting Memory
Frequency... CLKCFG=0x00010021, CLKCFG=0x00010031, ok
Setting mode of
operation for memory channels...Single Channel 0
only.
DCC=0x00000400
Programming Clock Crossing...MEM=533 FSB=533...
ok
Setting RAM size...
C0DRB = 0x10101010
C1DRB = 0x00000000
TOLUD
= 0x0020
Setting row attributes...
C0DRA = 0x0003
C1DRA =
0x0000
one dimm per channel config..
Initializing System Memory IO...
Programming Dual Channel RCOMP
Table Index: 9
Programming DLL
Timings...
Enabling System Memory IO...
jedec enable sequence: bank
0
Apply NOP
Sending RAM command
0x00010400...done
ram read: 00000000
All Banks
Precharge
Sending RAM command 0x00020400...done
ram read: 00000000
Extended Mode Register Set(2)
Sending RAM
command 0x00240400...done
ram read: 00000000
Extended Mode
Register Set(3)
Sending RAM command
0x00440400...done
ram read: 00000000
Extended Mode Register
Set
Sending RAM command 0x00040400...done
ram
read: 00000200
MRS: Reset DLLs
Sending RAM command
0x00030400...done
ram read: 00003a58
All Banks
Precharge
Sending RAM command 0x00020400...done
ram read: 00000000
CAS before RAS
Sending RAM command
0x00060400...done
ram read: 00000000
ram read:
00000000
MRS: Enable DLLs
Sending RAM command
0x00030400...done
ram read: 00003258
Extended Mode Register
Set: ODT/OCD
Sending RAM command
0x00040400...done
ram read: 00001e00
Extended Mode Register
Set: OCD Exit
Sending RAM command
0x00040400...done
ram read: 00000200
Normal
Operation
Sending RAM command
0x000f0400...done
receive_enable_autoconfig() for channel 0
find_strobes_low()
set_receive_enable() medium=0x3,
coarse=0x4
set_receive_enable() medium=0x1,
coarse=0x4
set_receive_enable() medium=0x1,
coarse=0x4
find_strobes_edge()
set_receive_enable() medium=0x1, coarse=0x4
add_quarter_clock()
mediumcoarse=11 fine=80
set_receive_enable() medium=0x3,
coarse=0x4
find_preamble()
set_receive_enable()
medium=0x3, coarse=0x3
set_receive_enable() medium=0x3,
coarse=0x2
add_quarter_clock() mediumcoarse=0b fine=00
normalize()
set_receive_enable() medium=0x0,
coarse=0x3
Weird. No C0WL0REOST
RAM initialization finished.
....
Jumping to boot code
at 100080
entry = 0x00100080
lb_start =
0x00100000
lb_size = 0x00042000
adjust =
0x1f5be000
buffer = 0x1f558090
elf_boot_notes = 0x0012fa48
adjusted_boot_notes =
0x1f6eda48
F
coreboot-2.0.0-r Thu
Dec 3 18:06:23 CST 2009 starting...
soft reset
detected.
======================================
Second SO-DIMM:
======================================
coreboot-2.0.0-r Thu
Dec 3 18:06:23 CST 2009 starting...
Mobile Intel(R)
82945GMS/GU Express Chipset
(G)MCH capable of up to FSB 667 MHz
(G)MCH
capable of up to DDR2-533
Setting up static southbridge registers... GPIOS...
done.
Disabling Watchdog reboot... done.
Setting up static northbridge
registers... done.
Waiting for MCHBAR to come up...ok
PM1_CNT:
00001c00
SMBus controller enabled.
dimm 50
00: 80 08
08 0d 0a 61 40 00 05 3d 50 00 82 10 00 00
10: 0c 04 38 01 04 00 01 3d 50 50
60 3c 28 3c 2d 40
20: 25 37 10 22 3c 1e 1e 00 00 3c 69 80 1e 28 00 50
30: 76 7b 2d 25 1f 24 16 4a 22 31 00 00 00 00 12 10
40: 7f 7f 7f 0b 00
00 00 00 0d 4e 54 35 31 32 54 36
50: 34 55 48 38 41 31 46 4e 2d 33 37 42 00
05 39 d2
60: 6e 2f 24 88 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 4d 4d 30
35 39 32 30 30 42
90: 43 00 00 00 00 00 00 44 4e 54 35 33 39 32 31 30
a0: 34 00 00 00 00 00 00 39 4e 54 44 32 00 32 2d 31
b0: 32 00 00 00 00
00 00 00 00 00 00 00 00 00 80 00
c0: 00 00 00 00 00 00 00 00 00 00 00 80 00
00 00 00
d0: 00 00 00 00 00 00 00 00 80 00 00 00 00 00 00 00
e0: 00 00
00 00 00 80 00 00 00 01 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 88
dimm 51
00: bad
device: 01
dimm 52
00: bad device: 01
dimm 53
00: bad device: 01
SLP S4# Assertion Width Violation.
Setting up RAM controller.
This
mainboard supports Dual Channel Operation.
DDR II Channel 0 Socket 0:
x16DS
DDR II Channel 1 Socket 0: N/A
lowest common cas = 3
Probing
Speed 1
DIMM: 0
Current CAS mask: 0038; idx=2,
tCLK=50, tAC=60: Not fast enough!
Current CAS mask: 0030; idx=1, tCLK=3d, tAC=50: OK
DIMM: 1
DIMM: 2
DIMM: 3
freq_cas_mask for speed 1:
0030
Memory will be driven at 533MHz with CAS=4 clocks
tRAS = 12
cycles
tRP = 4 cycles
tRCD = 4 cycles
Refresh: 7.8us
tWR = 4
cycles
DIMM 0 side 0 = 256 MB
DIMM 0 side 1 = 256 MB
tRFC = 28
cycles
Setting Graphics Frequency...
FSB: 533 MHz Voltage: 1.05V Render:
166Mhz Display: 200MHz
Setting Memory Frequency... CLKCFG=0x00010021,
CLKCFG=0x00010031, ok
Setting mode of operation for memory channels...Single
Channel 0 only.
DCC=0x00000400
Programming Clock Crossing...MEM=533
FSB=533... ok
Setting RAM size...
C0DRB = 0x10101008
C1DRB =
0x00000000
TOLUD = 0x0020
Setting row attributes...
C0DRA =
0x0033
C1DRA = 0x0000
one dimm per channel config..
Initializing
System Memory IO...
Programming Dual Channel RCOMP
Table Index:
4
Programming DLL Timings...
Enabling System Memory IO...
jedec
enable sequence: bank 0
Apply NOP
Sending RAM command
0x00010400...done
ram read: 00000000
All Banks
Precharge
Sending RAM command 0x00020400...done
ram read: 00000000
Extended Mode Register Set(2)
Sending RAM
command 0x00240400...done
ram read: 00000000
Extended Mode
Register Set(3)
Sending RAM command
0x00440400...done
ram read: 00000000
Extended Mode Register
Set
Sending RAM command 0x00040400...done
ram
read: 00000200
MRS: Reset DLLs
Sending RAM command
0x00030400...done
ram read: 00003a58
All Banks
Precharge
Sending RAM command 0x00020400...done
ram read: 00000000
CAS before RAS
Sending RAM command
0x00060400...done
ram read: 00000000
ram read:
00000000
MRS: Enable DLLs
Sending RAM command
0x00030400...done
ram read: 00003258
Extended Mode Register
Set: ODT/OCD
Sending RAM command
0x00040400...done
ram read: 00001e00
Extended Mode Register
Set: OCD Exit
Sending RAM command
0x00040400...done
ram read: 00000200
jedec enable sequence:
bank 1
bankaddr from bank size of rank 0
Apply NOP
Sending
RAM command 0x00010400...done
ram read: 10000000
All Banks
Precharge
Sending RAM command 0x00020400...done
ram read: 10000000
Extended Mode Register Set(2)
Sending RAM
command 0x00240400...done
ram read: 10000000
Extended Mode
Register Set(3)
Sending RAM command
0x00440400...done
ram read: 10000000
Extended Mode Register
Set
Sending RAM command 0x00040400...done
ram
read: 10000200
MRS: Reset DLLs
Sending RAM command
0x00030400...done
ram read: 10003a58
All Banks
Precharge
Sending RAM command 0x00020400...done
ram read: 10000000
CAS before RAS
Sending RAM command
0x00060400...done
ram read: 10000000
ram read:
10000000
MRS: Enable DLLs
Sending RAM command
0x00030400...done
ram read: 10003258
Extended Mode Register
Set: ODT/OCD
Sending RAM command
0x00040400...done
ram read: 10001e00
Extended Mode Register
Set: OCD Exit
Sending RAM command
0x00040400...done
ram read: 10000200
Normal
Operation
Sending RAM command
0x000f0400...done
receive_enable_autoconfig() for channel 0
find_strobes_low()
set_receive_enable() medium=0x3,
coarse=0x4
set_receive_enable() medium=0x1,
coarse=0x4
find_strobes_edge()
set_receive_enable() medium=0x1, coarse=0x4
add_quarter_clock()
mediumcoarse=11 fine=b1
set_receive_enable() medium=0x3,
coarse=0x4
find_preamble()
set_receive_enable()
medium=0x3, coarse=0x3
set_receive_enable() medium=0x3,
coarse=0x2
add_quarter_clock() mediumcoarse=0b fine=31
normalize()
set_receive_enable() medium=0x0,
coarse=0x3
RAM initialization finished.
....
Jumping to boot code
at 100080
entry = 0x00100080
lb_start =
0x00100000
lb_size = 0x00042000
adjust =
0x1f5be000
buffer = 0x1f558090
elf_boot_notes = 0x0012fa48
adjusted_boot_notes = 0x1f6eda48
FILO version
0.6.0 (scott@scott-laptop) Wed Oct 28
21:33:51 CST 2009
No USB stack in libpayload.
menu:
hda3:/boot/filo/menu.lst
======================================