From 28e8b7f510c5ae658447795092ad71d29a952c53 Mon Sep 17 00:00:00 2001
From: Abhinav Hardikar <ahardyx@gmail.com>
Date: Mon, 5 Sep 2011 20:04:52 +0530
Subject: [PATCH] Added Jetway J7BXAN to mainboard list Signed-off-by: Abhinav
 Hardikar <ahardyx@gmail.com>

---
 src/mainboard/jetway/Kconfig              |    3 +
 src/mainboard/jetway/j7bxan/Kconfig       |   44 +++++++++++++++++++++
 src/mainboard/jetway/j7bxan/chip.h        |   22 +++++++++++
 src/mainboard/jetway/j7bxan/devicetree.cb |   59 +++++++++++++++++++++++++++++
 src/mainboard/jetway/j7bxan/irq_tables.c  |   57 ++++++++++++++++++++++++++++
 src/mainboard/jetway/j7bxan/mainboard.c   |   26 +++++++++++++
 src/mainboard/jetway/j7bxan/romstage.c    |   58 ++++++++++++++++++++++++++++
 7 files changed, 269 insertions(+), 0 deletions(-)
 create mode 100644 src/mainboard/jetway/j7bxan/Kconfig
 create mode 100644 src/mainboard/jetway/j7bxan/chip.h
 create mode 100644 src/mainboard/jetway/j7bxan/devicetree.cb
 create mode 100755 src/mainboard/jetway/j7bxan/irq_tables.c
 create mode 100644 src/mainboard/jetway/j7bxan/mainboard.c
 create mode 100755 src/mainboard/jetway/j7bxan/romstage.c

diff --git a/src/mainboard/jetway/Kconfig b/src/mainboard/jetway/Kconfig
index 8023665..f7b2314 100644
--- a/src/mainboard/jetway/Kconfig
+++ b/src/mainboard/jetway/Kconfig
@@ -3,6 +3,8 @@ if VENDOR_JETWAY
 choice
 	prompt "Mainboard model"
 
+config BOARD_JETWAY_J7BXAN
+	bool "J7BXAN"
 config BOARD_JETWAY_J7F24
 	bool "J7F24"
 config BOARD_JETWAY_PA78VM5
@@ -10,6 +12,7 @@ config BOARD_JETWAY_PA78VM5
 
 endchoice
 
+source "src/mainboard/jetway/j7bxan/Kconfig"
 source "src/mainboard/jetway/j7f24/Kconfig"
 source "src/mainboard/jetway/pa78vm5/Kconfig"
 
diff --git a/src/mainboard/jetway/j7bxan/Kconfig b/src/mainboard/jetway/j7bxan/Kconfig
new file mode 100644
index 0000000..ff748b5
--- /dev/null
+++ b/src/mainboard/jetway/j7bxan/Kconfig
@@ -0,0 +1,44 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+if BOARD_JETWAY_J7BXAN
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_X86
+	select CPU_INTEL_SLOT_1
+	select NORTHBRIDGE_INTEL_I440BX
+	select SOUTHBRIDGE_INTEL_I82371EB
+	select SUPERIO_WINBOND_W83977TF
+	select HAVE_PIRQ_TABLE
+	select UDELAY_TSC
+	select BOARD_ROMSIZE_KB_128
+
+config MAINBOARD_DIR
+	string
+	default jetway/j7bxan
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "J7BXAN"
+
+config IRQ_SLOT_COUNT
+	int
+	default 7
+
+endif # BOARD_JETWAY_J7BXAN
diff --git a/src/mainboard/jetway/j7bxan/chip.h b/src/mainboard/jetway/j7bxan/chip.h
new file mode 100644
index 0000000..dc9bed3
--- /dev/null
+++ b/src/mainboard/jetway/j7bxan/chip.h
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+struct mainboard_config {};
diff --git a/src/mainboard/jetway/j7bxan/devicetree.cb b/src/mainboard/jetway/j7bxan/devicetree.cb
new file mode 100644
index 0000000..9c7cf56
--- /dev/null
+++ b/src/mainboard/jetway/j7bxan/devicetree.cb
@@ -0,0 +1,59 @@
+chip northbridge/intel/i440bx		# Northbridge
+  device lapic_cluster 0 on		# APIC cluster
+    chip cpu/intel/slot_1		# CPU
+      device lapic 0 on end		# APIC
+    end
+  end
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    device pci 1.0 on end		# PCI/AGP bridge
+    chip southbridge/intel/i82371eb	# Southbridge
+      device pci 7.0 on			# ISA bridge
+        chip superio/winbond/w83977tf	# Super I/O (FIXME: It's W83977EF!)
+          device pnp 3f0.0 on		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 3f0.1 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 3f0.2 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 3f0.3 on		# COM2 / IR
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 3f0.5 on		# PS/2 keyboard
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1		# PS/2 keyboard interrupt
+            irq 0x72 = 12		# PS/2 mouse interrupt
+          end
+          device pnp 3f0.6 on		# Consumer IR
+          end
+          device pnp 3f0.7 on		# GPIO 1
+          end
+          device pnp 3f0.8 on		# GPIO 2
+          end
+          device pnp 3f0.a on		# ACPI
+          end
+        end
+      end
+      device pci 7.1 on	end		# IDE, UDMA/33 (part of 82371EB)
+      device pci 7.2 on	end		# USB
+      device pci 7.3 on end		# ACPI
+      device pci 13.0 on end		# IDE, UDMA/66 (HPT366 controller)
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+      register "ide_legacy_enable" = "1"
+      register "ide0_drive0_udma33_enable" = "1"
+      register "ide0_drive1_udma33_enable" = "1"
+      register "ide1_drive0_udma33_enable" = "1"
+      register "ide1_drive1_udma33_enable" = "1"
+    end
+  end
+end
diff --git a/src/mainboard/jetway/j7bxan/irq_tables.c b/src/mainboard/jetway/j7bxan/irq_tables.c
new file mode 100755
index 0000000..8473c00
--- /dev/null
+++ b/src/mainboard/jetway/j7bxan/irq_tables.c
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 200x TODO <TODO@TODO>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifdef GETPIR			/* TODO: Drop this when copying to coreboot. */
+#include "pirq_routing.h"	/* TODO: Drop this when copying to coreboot. */
+#else				/* TODO: Drop this when copying to coreboot. */
+#include <arch/pirq_routing.h>
+#endif				/* TODO: Drop this when copying to coreboot. */
+
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,		/* u32 signature */
+	PIRQ_VERSION,		/* u16 version */
+	32 + 16 * 7,		/* Max. number of devices on the bus */
+	0x00,			/* Interrupt router bus */
+	(0x07 << 3) | 0x0,	/* Interrupt router dev */
+	0xc00,			/* IRQs devoted exclusively to PCI usage */
+	0x8086,			/* Vendor */
+	0x7000,			/* Device */
+	0,			/* Miniport */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0x3c,			/* Checksum (has to be set to some value that
+				 * would give 0 after the sum of all bytes
+				 * for this structure (including checksum).
+                                 */
+	{
+		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+		{0x00, (0x09 << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x1, 0x0},
+		{0x00, (0x0b << 3) | 0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}}, 0x2, 0x0},
+		{0x00, (0x0d << 3) | 0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}}, 0x3, 0x0},
+		{0x00, (0x11 << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x4, 0x0},
+		{0x00, (0x0f << 3) | 0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}}, 0x5, 0x0},
+		{0x00, (0x07 << 3) | 0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x0, 0x0},
+		{0x00, (0x01 << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x0, 0x0},
+	}
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	return copy_pirq_routing_table(addr);
+}
diff --git a/src/mainboard/jetway/j7bxan/mainboard.c b/src/mainboard/jetway/j7bxan/mainboard.c
new file mode 100644
index 0000000..466278c
--- /dev/null
+++ b/src/mainboard/jetway/j7bxan/mainboard.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations mainboard_ops = {
+	CHIP_NAME("Jetway J7BXAN Mainboard")
+};
diff --git a/src/mainboard/jetway/j7bxan/romstage.c b/src/mainboard/jetway/j7bxan/romstage.c
new file mode 100755
index 0000000..3135592
--- /dev/null
+++ b/src/mainboard/jetway/j7bxan/romstage.c
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <arch/hlt.h>
+#include <console/console.h>
+#include "southbridge/intel/i82371eb/i82371eb.h"
+#include "northbridge/intel/i440bx/raminit.h"
+#include "pc80/udelay_io.c"
+#include "lib/delay.c"
+#include "cpu/x86/bist.h"
+/* FIXME: It's a Winbond W83977EF, actually. */
+#include "superio/winbond/w83977tf/early_serial.c"
+#include <lib.h>
+
+/* FIXME: It's a Winbond W83977EF, actually. */
+#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
+
+int spd_read_byte(unsigned int device, unsigned int address)
+{
+	return smbus_read_byte(device, address);
+}
+
+void main(unsigned long bist)
+{
+	/* FIXME: It's a Winbond W83977EF, actually. */
+	w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	console_init();
+	report_bist_failure(bist);
+
+	enable_smbus();
+	dump_spd_registers();
+	sdram_set_registers();
+	sdram_set_spd_registers();
+	sdram_enable();
+}
-- 
1.7.5.4

