Index: src/cpu/intel/Kconfig
===================================================================
--- src/cpu/intel/Kconfig	(revision 5184)
+++ src/cpu/intel/Kconfig	(working copy)
@@ -8,6 +8,7 @@
 source src/cpu/intel/bga956/Kconfig
 source src/cpu/intel/ep80579/Kconfig
 source src/cpu/intel/slot_2/Kconfig
+source src/cpu/intel/slot_1/Kconfig
 source src/cpu/intel/socket_mFCPGA478/Kconfig
 source src/cpu/intel/socket_mPGA478/Kconfig
 source src/cpu/intel/socket_mPGA479M/Kconfig
Index: src/cpu/intel/Makefile.inc
===================================================================
--- src/cpu/intel/Makefile.inc	(revision 5184)
+++ src/cpu/intel/Makefile.inc	(working copy)
@@ -13,6 +13,7 @@
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_PGA370) += socket_PGA370
 subdirs-$(CONFIG_CPU_INTEL_SLOT_2) += slot_2
+subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1
 
 #socket_mPGA604_533Mhz
 #socket_mPGA604_800Mhz
Index: src/cpu/intel/slot_1/Kconfig
===================================================================
--- src/cpu/intel/slot_1/Kconfig	(revision 0)
+++ src/cpu/intel/slot_1/Kconfig	(revision 0)
@@ -0,0 +1,34 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+## Copyright (C) 2010 Keith Hui <buurin@gmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config CPU_INTEL_SLOT_1
+	bool
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xc0000
+	depends on CPU_INTEL_SLOT_1
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x01000
+	depends on CPU_INTEL_SLOT_1
+
Index: src/cpu/intel/slot_1/slot_1.c
===================================================================
--- src/cpu/intel/slot_1/slot_1.c	(revision 0)
+++ src/cpu/intel/slot_1/slot_1.c	(revision 0)
@@ -0,0 +1,7 @@
+#include <device/device.h>
+#include "chip.h"
+
+
+struct chip_operations cpu_intel_slot_1_ops = {
+	CHIP_NAME("Slot 1 CPU")
+};
Index: src/cpu/intel/slot_1/Makefile.inc
===================================================================
--- src/cpu/intel/slot_1/Makefile.inc	(revision 0)
+++ src/cpu/intel/slot_1/Makefile.inc	(revision 0)
@@ -0,0 +1,29 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+obj-y += slot_1.o
+subdirs-y += ../model_6xx
+subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/smm
+subdirs-y += ../microcode
+
Index: src/cpu/intel/slot_1/chip.h
===================================================================
--- src/cpu/intel/slot_1/chip.h	(revision 0)
+++ src/cpu/intel/slot_1/chip.h	(revision 0)
@@ -0,0 +1,4 @@
+extern struct chip_operations cpu_intel_slot_1_ops;
+
+struct cpu_intel_slot_1_config {
+};
Index: src/cpu/intel/model_6xx/microcode_MU06b11c.h
===================================================================
--- src/cpu/intel/model_6xx/microcode_MU06b11c.h	(revision 0)
+++ src/cpu/intel/model_6xx/microcode_MU06b11c.h	(revision 0)
@@ -0,0 +1,129 @@
+/*  MU06b11c.inc  */
+	0x00000001,	0x0000001c,	0x02152001,	0x000006b1,
+	0x6506e1cf,	0x00000001,	0x00000010,	0x00000000,
+	0x00000000,	0x00000000,	0x00000000,	0x00000000,
+	0x3ff8d1ac,	0x6ad5a5d7,	0x41bc1a2f,	0xc0cfcf98,
+	0xae80b685,	0x4e7fdba5,	0xee70aae6,	0x857f82df,
+	0x4c12ad1c,	0xc6eab058,	0x849e97b8,	0x4b425e5a,
+	0xe6819908,	0x8134a945,	0x601aea2a,	0xc633b991,
+	0x8f9e395f,	0x4699cb55,	0xcbc3795e,	0x85561846,
+	0xcf0cf38f,	0xac133e0c,	0x4bbe51fc,	0xc340f285,
+	0x8c63f67d,	0x45160027,	0xc85a74bb,	0xaeb95e32,
+	0x4f4fc61d,	0xe5033858,	0x8e4e090f,	0x4b5acb2a,
+	0xc75bc00c,	0x880daabb,	0x43d6f6af,	0xefd1d4e8,
+	0x87575a65,	0x6ef3afc2,	0xc8062d96,	0x8945ca80,
+	0x41c583c3,	0xcbb2f0a7,	0x8661bdce,	0x6d21f128,
+	0xc24acdc4,	0xaeaf43d5,	0x46dcbcd3,	0xcf544779,
+	0x82ea3983,	0x4b1656e2,	0xc3a0de21,	0xa14ded06,
+	0x4e779174,	0xe01de86d,	0x80c33ba8,	0x44762085,
+	0xc74f0d93,	0x85ca1cfa,	0x4dc7752f,	0xe0c2bfd0,
+	0x853e48b1,	0x67f42503,	0xcfed157c,	0x8d33cb2f,
+	0x43eb149b,	0xc71e279a,	0x82561424,	0x60cc4578,
+	0xce0d779d,	0xa6254192,	0x43e5a2cf,	0xcaee4715,
+	0x857afd44,	0x45ad93fa,	0xc6043ebf,	0xa98f3eee,
+	0x4f8e481c,	0xee5d3fe4,	0x84e30c80,	0x464de23b,
+	0xc76af7c3,	0x8155a3cb,	0x4a425a2f,	0xe3fd06a4,
+	0x8b51c2ec,	0x61bda6b9,	0xc71d76c2,	0x8bd436d3,
+	0x4e4a5c77,	0xc2cffcfd,	0x833c6a3c,	0x65d4f768,
+	0xcbfe0635,	0xa9bd7c0a,	0x49d3018a,	0xca646403,
+	0x8776d3d2,	0x426a93f7,	0xc03b8393,	0xa8e7690c,
+	0x46d7b40c,	0xe6a47d18,	0x8b927811,	0x4febdfe3,
+	0xc38a9d51,	0x8f76a603,	0x49d5cc1c,	0xe79861ed,
+	0x8d4c5baa,	0x6c7da6df,	0xc157063a,	0x87dbd994,
+	0x472dff09,	0xcc1742f2,	0x8de8e9c7,	0x641ab500,
+	0xc437013a,	0xaeaedc04,	0x492e9f4e,	0xc3de047e,
+	0x8dbd801d,	0x4cfd2f32,	0xcc34102c,	0xac06dbb4,
+	0x4ac3f30b,	0xe83b3458,	0x8634b95b,	0x444079d2,
+	0xc807d487,	0x8da4cd9e,	0x4760f318,	0xec62523f,
+	0x816240b9,	0x6cba09ce,	0xca86a264,	0x863f14ca,
+	0x49b9d4a1,	0xc6bd9715,	0x87edeb98,	0x6fa1a092,
+	0xcb36670f,	0xa2edb3a7,	0x43545378,	0xc3c35ad7,
+	0x8e2d1255,	0x4a06377c,	0xcd1b61d4,	0xa83a9bc7,
+	0x4c48d28d,	0xe8a27b8a,	0x8a47665c,	0x49a35371,
+	0xc8a8fb0a,	0x830dc900,	0x4c01d1bc,	0xee2ffff4,
+	0x83243d8d,	0x61ead599,	0xc82c0451,	0x8c19b0ec,
+	0x465ee1d4,	0xc52df943,	0x8490687c,	0x68474c0d,
+	0xcc495773,	0xa04396d5,	0x4824c02c,	0xceb15f4d,
+	0x80a78140,	0x4de85a0b,	0x8945e8c5,	0xc981ea75,
+	0x7ff89629,	0x4e4ce4e2,	0x6e9ceb88,	0x7f0b4dff,
+	0x165e46c8,	0xcf59bf6c,	0x9c430db4,	0xb55a941c,
+	0x277a73f1,	0x6dbffb22,	0xb3081fe8,	0xdebe60c6,
+	0x691d8c9e,	0x330333a2,	0x0b024599,	0xe358aa28,
+	0xe70334b3,	0xe48d7707,	0x16318df8,	0x0e34f491,
+	0x1c0d6223,	0x54315b5f,	0x040fcc96,	0x5557f1d2,
+	0x5ccf28f6,	0xc0004404,	0x2f7a5fef,	0x95b65ddd,
+	0xbaa1a873,	0x077783d4,	0x3f24b63b,	0x9ae679fe,
+	0xaf11d97e,	0x51391564,	0xb3247855,	0xcd10e6dc,
+	0x704e147c,	0xcc15de9d,	0xa5adf161,	0x0179c9a6,
+	0xa579d74c,	0x28704a4d,	0x3e7a2d92,	0x253437c4,
+	0x1162b521,	0x14a9c51d,	0x2129abbe,	0x3b2d07c4,
+	0x1d84f76a,	0x016cd356,	0x3fd03cad,	0x3f82ee67,
+	0x0275b51e,	0x5dd38dae,	0xdd022704,	0x6b6d2f56,
+	0xbdb25b55,	0xe4188d73,	0xc03a6c98,	0x8a303586,
+	0x4999d605,	0x82c9e7e8,	0x8169c654,	0x838ba96f,
+	0x4f0239d3,	0xf295395e,	0xb3c38631,	0x7ea7a143,
+	0x157a4e43,	0x46f8173f,	0xfbc18d4a,	0xc401e17a,
+	0xc4620358,	0xd2ab5437,	0xa01db06f,	0x58ce91fc,
+	0x850de1a3,	0x9b542dba,	0xee77f038,	0xddd3ced6,
+	0xc225d2ce,	0x63a3f765,	0x3342a06c,	0x6a780c2f,
+	0xfaa925b2,	0x366ebeec,	0xbcc9abea,	0xc7b3fa4e,
+	0xf4f1123d,	0x5198702c,	0x3e3458b7,	0x0b1ce9a1,
+	0x51b1bd7f,	0x711e791e,	0x927d8bed,	0x91dbaea9,
+	0x7eefbda9,	0x7a19edd9,	0xdf7b8dce,	0x5bb40613,
+	0x0b0c1e0f,	0x85b82c98,	0x18da4dc1,	0xc5fd78ac,
+	0x57c1e31d,	0x4c4001b5,	0xe31d2643,	0xa6afbf58,
+	0xad200e68,	0xf0114ba4,	0xd6a620f2,	0xc753a720,
+	0xac9022a0,	0x28a41f01,	0x22a4ba95,	0xc00b7531,
+	0x23d42795,	0xcd836a86,	0x90262708,	0x3292cad0,
+	0x40022e39,	0xc1581b0a,	0xe5101550,	0x6538096b,
+	0x208c549d,	0x3ce2bf88,	0xa71df38e,	0x3dec3685,
+	0xca3949f1,	0x79f3ad1b,	0x3ee8b300,	0x9d305fc6,
+	0x7a2e5288,	0xbe81a2f2,	0x7ada0c06,	0x191c7f01,
+	0x58dfcbd1,	0xc78dee72,	0x72364226,	0x1866de12,
+	0x8d22305c,	0x943a0f0e,	0xc81967ff,	0x4d55fb0f,
+	0xaf199be1,	0x90bbda61,	0x4e7c234f,	0x90cfec16,
+	0x9b4bcf26,	0x21622023,	0x0926f0fa,	0x1d504377,
+	0xa58db427,	0x8d93ce2b,	0x90bfe900,	0x29e67397,
+	0x2c1261ed,	0x4ace9474,	0xd5c60282,	0xe53fb300,
+	0x8a61a0ab,	0xa7aa0918,	0x4389d7c5,	0xd09d605c,
+	0x6c5bedb5,	0xd6d54c51,	0x433dea21,	0x7ad9e677,
+	0x813bff76,	0x5a162c75,	0x1ee0661f,	0x9b6c2030,
+	0x8e8dc989,	0xcd4bc9fc,	0x4454675b,	0x8d583c9c,
+	0xe3400094,	0x116ebb83,	0xe847bc9a,	0x2a4622dd,
+	0x2a901e6f,	0xd789b1c0,	0x094e2bbb,	0x056e563f,
+	0x9f17e606,	0x8bc79b8d,	0xd2c535c1,	0x06a45a27,
+	0x9dc56771,	0xa06649e2,	0x5ff25ac8,	0x6554961e,
+	0x98e583d9,	0x38ba93da,	0xdee1de18,	0x037cb9d5,
+	0x6b17f195,	0x3431faaf,	0x13860a0d,	0x28bca10d,
+	0x0a54c011,	0x9957cdb6,	0x3aa1f429,	0x9d41b7b3,
+	0x9aea5be2,	0x60c7ce6b,	0x4cd1c10b,	0x24ddddcd,
+	0xe28412ba,	0xa03a5466,	0xa1896879,	0x59edcb87,
+	0x1b241765,	0x157bf161,	0xf219f950,	0xe86ff526,
+	0x262005d9,	0x11769531,	0xbca15d95,	0x28f5ef17,
+	0x1f27e725,	0xc32631d2,	0x07249e61,	0x1ba851e3,
+	0x4f49b577,	0xe2a1df5e,	0x826fa7ff,	0xc34e1e2e,
+	0x7fe26024,	0xbc19800f,	0x0d368dc9,	0xe03da0c6,
+	0xadaa4f9c,	0x9ad1e43c,	0x96f84e44,	0x0b6cd695,
+	0x1bb46971,	0x942d6e5b,	0x6316170d,	0x3164509f,
+	0xc6659450,	0xb2a0370a,	0xabc208e8,	0x6d479811,
+	0x3684bc0e,	0x80b7b101,	0xa50b7bb5,	0x43d21233,
+	0xb423559d,	0xf41dcd16,	0xdfd3c276,	0x3e586469,
+	0xd9b7630a,	0xb88f9e44,	0x0cda6f4d,	0xe5bf5844,
+	0x8709f788,	0xdae37da6,	0x1fb41777,	0x1d903f69,
+	0x34383b69,	0xd409ae70,	0xd1c99758,	0xdedfd7a4,
+	0xa4bdf018,	0xf4058202,	0x8565d66f,	0x5365aed9,
+	0xfa69742e,	0x2cfbfbcf,	0x88a00b60,	0x506c0713,
+	0x2866475b,	0x3e1df573,	0xb86f7feb,	0x31d23a7f,
+	0xc6320e6a,	0x3ebbc2a5,	0x83a1d4ef,	0x15169f5f,
+	0x42a61753,	0x893e553e,	0x4ddbc66d,	0x7449ec1f,
+	0x76f65d22,	0x0622e13b,	0x32986f89,	0x21181b4b,
+	0x99a80c0a,	0xd6fe00b0,	0x282c0e81,	0x9fc1cf88,
+	0x919b855d,	0x618257d8,	0x82c448b8,	0xe22537a1,
+	0xa90de388,	0xba73b90c,	0xd765eeb0,	0x62b2727e,
+	0xa08dfe20,	0x70b3c8c5,	0x3ef04007,	0x9f73732b,
+	0x2201edd7,	0xb836219c,	0xf913af7c,	0xf50f64ca,
+	0x93ac107a,	0xf509f84a,	0x6f6026f6,	0xd9bb8eac,
+	0x4b268cfa,	0xa65a3fa6,	0x9837cb75,	0x784fb835,
+	0x2060576d,	0xb1604cae,	0xb9da4116,	0xab320cf2,
+	0x60a1b501,	0x0c73fa79,	0x8d5a6f1e,	0x57688086,
+	0x218e4005,	0xca054e3d,	0xc1a3c3ec,	0x6c667265,
Index: src/cpu/intel/model_6xx/microcode_MU06b401.h
===================================================================
--- src/cpu/intel/model_6xx/microcode_MU06b401.h	(revision 0)
+++ src/cpu/intel/model_6xx/microcode_MU06b401.h	(revision 0)
@@ -0,0 +1,129 @@
+/*  MU06b401.inc  */
+	0x00000001,	0x00000001,	0x01102002,	0x000006b4,
+	0x58213e6a,	0x00000001,	0x00000010,	0x00000000,
+	0x00000000,	0x00000000,	0x00000000,	0x00000000,
+	0x1016aa4c,	0xba6d2007,	0x139b094a,	0x8d5cd4f5,
+	0xece206e4,	0xfac0aa68,	0x26674533,	0x9464601b,
+	0x4b3f7f76,	0x64133194,	0x37c151ed,	0x3ee0e278,
+	0x7cffc9c4,	0x562be2dc,	0xd1067021,	0xaf8f1728,
+	0xbad0534c,	0xf7a67cca,	0xdd34e969,	0x774bb723,
+	0x5635256e,	0xd23cce15,	0x3c7c50ce,	0xa5faaecc,
+	0x1c717607,	0xcc1e6f3e,	0x16a4c6a7,	0x58bd5816,
+	0x0a2e73b3,	0xd65104e4,	0xb873ec1a,	0xe6cdd62e,
+	0xcd278f3c,	0x2e081c41,	0xf43f4439,	0xbcdfa892,
+	0xbb20c46f,	0xe0c8f8e1,	0xa619c4cc,	0x48eea22e,
+	0xcfdf4bc4,	0xefaf4494,	0xa7cac511,	0x783c367e,
+	0x6fc43ebc,	0x67e32786,	0xf0c1fbb1,	0xf93d5b0d,
+	0x36e9b7e8,	0xc3b4dc36,	0x4beec4fb,	0x88382c9d,
+	0x735dd739,	0xc5e23b67,	0x0d325dd4,	0xfe8bd98b,
+	0xa0f294f9,	0x1916bcd9,	0x7b73f066,	0x26758acb,
+	0xf10be125,	0x5aee77d0,	0xa005f65a,	0xd4d88c84,
+	0x02340625,	0x687da1c4,	0x29906f8c,	0x20ca4e9c,
+	0xcad37ebf,	0x15ae02ef,	0x06ac0241,	0x60c210b8,
+	0x07bb359b,	0x970ada27,	0xd15463c5,	0xb1df482a,
+	0x32c0386e,	0x72719013,	0xbe45b1da,	0xda807e08,
+	0xe1340a36,	0x9bbc789b,	0x71ae0eb2,	0xa7b0e639,
+	0x12948517,	0x8bd37587,	0x083273be,	0x1a73a3be,
+	0x2e0cf9a6,	0x3c401aa6,	0xc74c77f8,	0xe6ee9da6,
+	0x3188f408,	0xcdfe98ff,	0x71369d02,	0x032e20b7,
+	0xb9083418,	0xe5ef65a8,	0x3a9317d2,	0x23117ad6,
+	0x6c303cfc,	0xe6aed513,	0x97b7af1e,	0xe277f5aa,
+	0xd1f788a7,	0x72305569,	0x2a241259,	0x7f786fa4,
+	0xeba79f99,	0x740b14fa,	0x2a8e8a3c,	0x7824a0f2,
+	0xb1b4588e,	0xc775677d,	0xbc2372a6,	0xd485e398,
+	0x8a989d5d,	0x960199ba,	0xe5dca6a2,	0x818b5c9c,
+	0x655f760d,	0x8a75081a,	0x86a6d67a,	0x05e74583,
+	0x160d2e9b,	0xecf3f2b6,	0xb0e5f342,	0x162dcc4b,
+	0x95d05b92,	0xec736eb1,	0xad367c81,	0x6b98845e,
+	0xaea10969,	0x32a923cc,	0x0e20e511,	0x11f1d80d,
+	0xa80bff0c,	0xdee5c142,	0x5618820b,	0x9ab1530f,
+	0xeb2e5aad,	0x71986a78,	0x4b9f79ab,	0xdcb38492,
+	0x5d1df5ee,	0xa6947ea5,	0x4b81b7aa,	0x4fd1194a,
+	0x809256af,	0x2d7d2c85,	0xc3a3d15b,	0x4e4dde55,
+	0xa275c268,	0xe584005b,	0xe7975491,	0xed9d3d06,
+	0x6aaf4acf,	0xf4e3f967,	0x7c04ded2,	0x9fefbb0c,
+	0xff806dc8,	0xbe36d1ce,	0xdc9e4a45,	0xe54a5b71,
+	0xea53d6aa,	0xf0e13f21,	0x250f7e77,	0x09429ec2,
+	0xb34360be,	0xdf249256,	0x4b6b8d57,	0x6f3b9f7d,
+	0x1dd4d988,	0x6a68c719,	0x82d171e5,	0x04de6517,
+	0xd2628f0d,	0xfe6fd4e1,	0x8f3cbd0b,	0xd8517c88,
+	0x7993bb4f,	0x9487f25f,	0x493ad1f1,	0x781b2745,
+	0xd25de9ed,	0x63fe8ffa,	0x83be8468,	0x5955efd3,
+	0xd07886cb,	0x3cbbf313,	0x10255dcf,	0x4fe6e5df,
+	0x2afbe5ce,	0x2731cea5,	0x3ca3a0b4,	0x9a73e5b3,
+	0x7022f776,	0x43f0062b,	0xac060c7c,	0x89c88761,
+	0xdf86c5be,	0x0f705bcc,	0x811d31cd,	0x56e72be7,
+	0x473becc1,	0x74d511a7,	0x7f44e656,	0xc04d3763,
+	0x487e15a7,	0x851f93bd,	0xc0cfdff8,	0x11b62ba1,
+	0x45ebf606,	0x5ae10f89,	0xcfd063cf,	0x25b52d80,
+	0x03b35a1a,	0x7e5be251,	0x643e69b1,	0xe50e0a26,
+	0x73a3be25,	0x7bd17fb9,	0x72ac0b0e,	0x2f04ee8b,
+	0x8e614214,	0x73fbbb40,	0x6c87f572,	0xc2cca0b1,
+	0x3a575557,	0xe38b025c,	0x57d61954,	0x5a77769b,
+	0x123d2893,	0xd21f163e,	0xef617597,	0xbfd67b8c,
+	0x838ba96f,	0x4f0239d3,	0xf295395e,	0xb3c38631,
+	0x7ea7a143,	0x157a4e43,	0x46f8173f,	0xfbc18d4a,
+	0xc401e17a,	0xc4620358,	0xd2ab5437,	0xa01db06f,
+	0x58ce91fc,	0x850de1a3,	0x9b542dba,	0xee77f038,
+	0xddd3ced6,	0xc225d2ce,	0x63a3f765,	0x3342a06c,
+	0x6a780c2f,	0xfaa925b2,	0x366ebeec,	0xbcc9abea,
+	0xc7b3fa4e,	0xf4f1123d,	0x5198702c,	0x3e3458b7,
+	0x0b1ce9a1,	0x51b1bd7f,	0x711e791e,	0x927d8bed,
+	0x91dbaea9,	0x7eefbda9,	0x7a19edd9,	0xdf7b8dce,
+	0x5bb40613,	0x0b0c1e0f,	0x85b82c98,	0x18da4dc1,
+	0xc5fd78ac,	0x57c1e31d,	0x4c4001b5,	0xe31d2643,
+	0xa6afbf58,	0xad200e68,	0xf0114ba4,	0xd6a620f2,
+	0xc753a720,	0xac9022a0,	0x28a41f01,	0x22a4ba95,
+	0xc00b7531,	0x23d42795,	0xcd836a86,	0x90262708,
+	0x3292cad0,	0x40022e39,	0xc1581b0a,	0xe5101550,
+	0x6538096b,	0x208c549d,	0x3ce2bf88,	0xa71df38e,
+	0x3dec3685,	0xca3949f1,	0x79f3ad1b,	0x3ee8b300,
+	0x9d305fc6,	0x7a2e5288,	0xbe81a2f2,	0x7ada0c06,
+	0x191c7f01,	0x58dfcbd1,	0xc78dee72,	0x72364226,
+	0x1866de12,	0x8d22305c,	0x943a0f0e,	0xc81967ff,
+	0x4d55fb0f,	0xaf199be1,	0x90bbda61,	0x4e7c234f,
+	0x90cfec16,	0x9b4bcf26,	0x21622023,	0x0926f0fa,
+	0x1d504377,	0xa58db427,	0x8d93ce2b,	0x90bfe900,
+	0x29e67397,	0x2c1261ed,	0x4ace9474,	0xd5c60282,
+	0xe53fb300,	0x8a61a0ab,	0xa7aa0918,	0x4389d7c5,
+	0xd09d605c,	0x6c5bedb5,	0xd6d54c51,	0x433dea21,
+	0x7ad9e677,	0x813bff76,	0x5a162c75,	0x1ee0661f,
+	0x9b6c2030,	0x8e8dc989,	0xcd4bc9fc,	0x4454675b,
+	0x8d583c9c,	0xe3400094,	0x116ebb83,	0xe847bc9a,
+	0x2a4622dd,	0x2a901e6f,	0xd789b1c0,	0x094e2bbb,
+	0x056e563f,	0x9f17e606,	0x8bc79b8d,	0xd2c535c1,
+	0x06a45a27,	0x9dc56771,	0xa06649e2,	0x5ff25ac8,
+	0x6554961e,	0x98e583d9,	0x38ba93da,	0xdee1de18,
+	0x037cb9d5,	0x6b17f195,	0x3431faaf,	0x13860a0d,
+	0x28bca10d,	0x0a54c011,	0x9957cdb6,	0x3aa1f429,
+	0x9d41b7b3,	0x9aea5be2,	0x60c7ce6b,	0x4cd1c10b,
+	0x24ddddcd,	0xe28412ba,	0xa03a5466,	0xa1896879,
+	0x59edcb87,	0x1b241765,	0x157bf161,	0xf219f950,
+	0xe86ff526,	0x262005d9,	0x11769531,	0xbca15d95,
+	0x28f5ef17,	0x1f27e725,	0xc32631d2,	0x07249e61,
+	0x1ba851e3,	0x4f49b577,	0xe2a1df5e,	0x826fa7ff,
+	0xc34e1e2e,	0x7fe26024,	0xbc19800f,	0x0d368dc9,
+	0xe03da0c6,	0xadaa4f9c,	0x9ad1e43c,	0x96f84e44,
+	0x0b6cd695,	0x1bb46971,	0x942d6e5b,	0x6316170d,
+	0x3164509f,	0xc6659450,	0xb2a0370a,	0xabc208e8,
+	0x6d479811,	0x3684bc0e,	0x80b7b101,	0xa50b7bb5,
+	0x43d21233,	0xb423559d,	0xf41dcd16,	0xdfd3c276,
+	0x3e586469,	0xd9b7630a,	0xb88f9e44,	0x0cda6f4d,
+	0xe5bf5844,	0x8709f788,	0xdae37da6,	0x1fb41777,
+	0x1d903f69,	0x34383b69,	0xd409ae70,	0xd1c99758,
+	0xdedfd7a4,	0xa4bdf018,	0xf4058202,	0x8565d66f,
+	0x5365aed9,	0xfa69742e,	0x2cfbfbcf,	0x88a00b60,
+	0x506c0713,	0x2866475b,	0x3e1df573,	0xb86f7feb,
+	0x31d23a7f,	0xc6320e6a,	0x3ebbc2a5,	0x83a1d4ef,
+	0x15169f5f,	0x42a61753,	0x893e553e,	0x4ddbc66d,
+	0x7449ec1f,	0x76f65d22,	0x0622e13b,	0x32986f89,
+	0x21181b4b,	0x99a80c0a,	0xd6fe00b0,	0x282c0e81,
+	0x9fc1cf88,	0x919b855d,	0x618257d8,	0x82c448b8,
+	0xe22537a1,	0xa90de388,	0xba73b90c,	0xd765eeb0,
+	0x62b2727e,	0xa08dfe20,	0x70b3c8c5,	0x3ef04007,
+	0x9f73732b,	0x2201edd7,	0xb836219c,	0xf913af7c,
+	0xf50f64ca,	0x93ac107a,	0xf509f84a,	0x6f6026f6,
+	0xd9bb8eac,	0x4b268cfa,	0xa65a3fa6,	0x9837cb75,
+	0x784fb835,	0x2060576d,	0xb1604cae,	0xb9da4116,
+	0xab320cf2,	0x60a1b501,	0x0c73fa79,	0x8d5a6f1e,
+	0x57688086,	0x218e4005,	0xca054e3d,	0xc1a3c3ec,
Index: src/cpu/intel/model_6xx/model_6xx_init.c
===================================================================
--- src/cpu/intel/model_6xx/model_6xx_init.c	(revision 5184)
+++ src/cpu/intel/model_6xx/model_6xx_init.c	(working copy)
@@ -18,6 +18,8 @@
 	 */
 #include "microcode_MU16810d.h"	
 #include "microcode_MU16830c.h"
+#include "microcode_MU06b11c.h"
+#include "microcode_MU06b401.h"
 	/*  Dummy terminator  */
         0x0, 0x0, 0x0, 0x0,
         0x0, 0x0, 0x0, 0x0,
@@ -58,6 +60,7 @@
 	{ X86_VENDOR_INTEL, 0x06A1 },
 	{ X86_VENDOR_INTEL, 0x06A4 },
 	{ X86_VENDOR_INTEL, 0x06B0 }, /* Mobile Celeron FCBGA */
+	{ X86_VENDOR_INTEL, 0x06B1 }, /* Celeron (Tualatin) */
 	{ X86_VENDOR_INTEL, 0x06B4 },
 	{ 0, 0 },
 };
Index: src/northbridge/intel/i440bx/i440bx.h
===================================================================
--- src/northbridge/intel/i440bx/i440bx.h	(revision 5184)
+++ src/northbridge/intel/i440bx/i440bx.h	(working copy)
@@ -32,11 +32,39 @@
  * Any addresses between 0x00 and 0xff not listed below are either
  * Reserved or Intel Reserved and should not be touched.
  */
+/* These are for completeness only
+#define VID     0x00 // Vendor identification (0x8086)
+#define DID     0x02 // Device identification (0x7190/0x7192 depending on AGP setup)
+#define PCICMD  0x04 // PCI Command Register (0x0006)
+#define PCISTS  0x06 // PCI Status Register (0x0210/0x0200)
+#define RID     0x08 // Revision Identification (0x00/01/02) 
+#define SUBC    0x0A // Sub-Class Code (0x00) RO
+#define BCC     0x0B // Base Class Code (0x06)
+#define HDR     0x0E // Header Type (0x00)
+*/
+#define MLT     0x0d /* Master Latency Timer (0x00) */
+#define APBASE  0x10 /* Aperture Base (0x00000008) */
+#define CAPPTR  0x34 /* Capabilities POinter (0xa0/0x00) */
 #define NBXCFG  0x50 /* 440BX Configuration (0x0000:00S0_0000_000S_0S00b). */
 #define DRAMC   0x57 /* DRAM Control (00S0_0000b). */
 #define DRAMT   0x58 /* DRAM Timing (0x03). */
 #define PAM     0x59 /* Programmable Attribute Map, 7 registers (0x00). */
+#define PAM0    0x59
+#define PAM1    0x5a
+#define PAM2    0x5b
+#define PAM3    0x5c
+#define PAM4    0x5d
+#define PAM5    0x5e
+#define PAM6    0x5f
 #define DRB     0x60 /* DRAM Row Boundary, 8 registers (0x01). */
+#define DRB0    0x60
+#define DRB1    0x61
+#define DRB2    0x62
+#define DRB3    0x63
+#define DRB4    0x64
+#define DRB5    0x65
+#define DRB6    0x66
+#define DRB7    0x67
 #define FDHC    0x68 /* Fixed SDRAM Hole Control (0x00). */
 #define MBSC    0x69 /* Memory Buffer Strength Control (0x0000-0000-0000). */
 #define SMRAM   0x72 /* System Management RAM Control (0x02). */
@@ -50,27 +78,24 @@
 #define ERRCMD  0x90 /* Error Command Register (0x80). */
 #define ERRSTS  0x91 /* Error Status (0x0000). */
 // TODO: AGP stuff.
+#define ACAPID  0xa0 /* AGP Capability Identifier (0x00100002 or 0x00000000) */
+#define AGPSTAT 0xa4 /* AGP Status Register (0x1f000203, read only) */
+#define AGPCMD  0xa8 /* AGP Command Register (0x00000000) */
+#define AGPCTRL 0xb0 /* AGP Control Register (0x00000000) */
+#define APSIZE  0xb4 /* Aperture Size Control Register (0x00) */
+#define ATTBASE 0xb8 /* Aperture Translation Table (0x00000000) */
+ 
 #define MBFS    0xca /* Memory Buffer Frequency Select (0x000000). */
 #define BSPAD   0xd0 /* BIOS Scratch Pad (0x000..000). */
+#define BSPAD0  0xd0 /* These are free for our use */ 
+#define BSPAD1  0xd1
+#define BSPAD2  0xd2
+#define BSPAD3  0xd3
+#define BSPAD4  0xd4
+#define BSPAD5  0xd5
+#define BSPAD6  0xd6
+#define BSPAD7  0xd7
 #define DWTC    0xe0 /* DRAM Write Thermal Throttling Control (0x000..000). */
 #define DRTC    0xe8 /* DRAM Read Thermal Throttling Control (0x000..000). */
 #define BUFFC   0xf0 /* Buffer Control Register (0x0000). */
 
-/* For convenience: */
-#define DRB0    0x60
-#define DRB1    0x61
-#define DRB2    0x62
-#define DRB3    0x63
-#define DRB4    0x64
-#define DRB5    0x65
-#define DRB6    0x66
-#define DRB7    0x67
-
-#define PAM0    0x59
-#define PAM1    0x5a
-#define PAM2    0x5b
-#define PAM3    0x5c
-#define PAM4    0x5d
-#define PAM5    0x5e
-#define PAM6    0x5f
-
Index: src/northbridge/intel/i440bx/raminit.c
===================================================================
--- src/northbridge/intel/i440bx/raminit.c	(revision 5184)
+++ src/northbridge/intel/i440bx/raminit.c	(working copy)
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2007-2008 Uwe Hermann <uwe@hermann-uwe.de>
+ * Copyright (C) 2010 Keith Hui <buurin@gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -23,6 +24,7 @@
 #include <delay.h>
 #include <stdlib.h>
 #include "i440bx.h"
+#include "raminit.h"
 
 /*-----------------------------------------------------------------------------
 Macros and definitions.
@@ -65,12 +67,24 @@
  * [4] == Extended(4x)    62.5 us ->  62.4 us
  * [5] == Extended(8x)     125 us -> 124.8 us
  */
-static const uint32_t refresh_rate_map[] = {
-	1, 5, 5, 2, 3, 4
+static const unsigned int refresh_rate_map[] = {
+	1, 1, 1, 2, 3, 4
 };
 
 /* Table format: register, bitmask, value. */
 static const long register_values[] = {
+	/* MLT - Master Latency Timer Register
+	 * 0x0d
+	 *
+	 * [07:03] Master Latency Timer Count Value for PCI Bus Access. 
+	 *         MLT is an 8-bit register that controls the amount of 
+	 *		   time the 82443BX, as a PCI bus master, can burst data 
+	 *		   on the PCI Bus. The default value of MLT is 00h and 
+	 *		   disables this function. For example, if the MLT is 
+	 *		   programmed to 18h, then the value is 24 PCI clocks.
+	 * [02:00] Reserved
+	 */
+	MLT, 0x00, 0x40,
 	/* NBXCFG - NBX Configuration Register
 	 * 0x50 - 0x53
 	 *
@@ -188,14 +202,21 @@
 	 * 10 = Write Only (Writes to DRAM, reads to memory mapped I/O space)
 	 * 11 = Read/Write (all access goes to DRAM)
 	 */
-	// TODO
-	PAM0, 0x00, 0x00,
-	PAM1, 0x00, 0x00,
-	PAM2, 0x00, 0x00,
-	PAM3, 0x00, 0x00,
-	PAM4, 0x00, 0x00,
-	PAM5, 0x00, 0x00,
-	PAM6, 0x00, 0x00,
+	/* Map all legacy regions to RAM (read/write). This is required if
+	 * you want to use the RAM area from 768 KB - 1 MB. If the PAM
+	 * registers are not set here appropriately, the RAM in that region
+	 * will not be accessible, thus a RAM check of it will also fail.
+	 
+	 * TODO: This was set in sdram_set_spd_registers()
+	 * Test if it still works when set here 
+	 */
+	PAM0, 0x00, 0x30,
+	PAM1, 0x00, 0x33,
+	PAM2, 0x00, 0x33,
+	PAM3, 0x00, 0x33,
+	PAM4, 0x00, 0x33,
+	PAM5, 0x00, 0x33,
+	PAM6, 0x00, 0x33,
 
 	/* DRB[0:7] - DRAM Row Boundary Registers
 	 * 0x60 - 0x67
@@ -343,6 +364,8 @@
 	// PMCR, 0x00, 0x14,
 	// PMCR, 0x00, 0x10,
 	PMCR, 0x00, 0x00,
+	/* Enable SCRR.SRRAEN and let BX choose the SRR */
+	SCRR+1, 0x00, 0x10,
 };
 
 /*-----------------------------------------------------------------------------
@@ -396,7 +419,7 @@
 
 		dimm_end = pci_read_config8(NB, DRB + i);
 
-		addr = (dimm_start * 8 * 1024 * 1024) + addr_offset;
+		addr = (dimm_start * 8 * 1048576) + addr_offset;
 		if (dimm_end > dimm_start) {
 #if 0
 			PRINT_DEBUG("    Sending RAM command 0x");
@@ -414,6 +437,22 @@
 	}
 }
 
+static void set_dram_buffer_strength(void)
+{
+	/* TODO: This needs to be set according to the DRAM tech
+	 * (x8, x16, or x32). Argh, Intel provides no docs on this!
+	 * Currently, it needs to be pulled from the output of
+	 * lspci -xxx Rx92
+	   Relevant registers:
+	 * MBSC
+	 * MBFS, BUFFC
+	 */
+
+	pci_write_config8(NB, MBSC, 0x03);
+
+}
+
+
 /*-----------------------------------------------------------------------------
 DIMM-independant configuration functions.
 -----------------------------------------------------------------------------*/
@@ -461,71 +500,305 @@
 		reg &= register_values[i + 1];
 		reg |= register_values[i + 2] & ~(register_values[i + 1]);
 		pci_write_config8(NB, register_values[i], reg);
-
+#if 0
 		PRINT_DEBUG("    Set register 0x");
 		PRINT_DEBUG_HEX8(register_values[i]);
 		PRINT_DEBUG(" to 0x");
 		PRINT_DEBUG_HEX8(reg);
 		PRINT_DEBUG("\r\n");
+#endif
 	}
 }
 
-static void sdram_set_spd_registers(void)
+/* Copied from i82830 northbridge code */
+struct dimm_size {
+	unsigned long side1;
+	unsigned long side2;
+};
+
+static struct dimm_size spd_get_dimm_size(unsigned device)
 {
-	/* TODO: Don't hardcode the values here, get info via SPD. */
+	struct dimm_size sz;
+	int i, module_density, dimm_banks;
+	sz.side1 = 0;
+	module_density = spd_read_byte(device, SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
+	dimm_banks = spd_read_byte(device, SPD_NUM_DIMM_BANKS);
 
-	/* Map all legacy regions to RAM (read/write). This is required if
-	 * you want to use the RAM area from 768 KB - 1 MB. If the PAM
-	 * registers are not set here appropriately, the RAM in that region
-	 * will not be accessible, thus a RAM check of it will also fail.
+	/* Find the size of side1. */
+	/* Find the larger value. The larger value is always side1. */
+	for (i = 512; i >= 0; i >>= 1) {
+		if ((module_density & i) == i) {
+			sz.side1 = i;
+			break;
+		}
+	}
+
+	/* Set to 0 in case it's single sided. */
+	sz.side2 = 0;
+
+	/* Test if it's a dual-sided DIMM. */
+	if (dimm_banks > 1) {
+		/* Test to see if there's a second value, if so it's asymmetrical. */
+		if (module_density != i) {
+			/* Find the second value, picking up where we left off. */
+			/* i >>= 1 done initially to make sure we don't get the same value again. */
+			for (i >>= 1; i >= 0; i >>= 1) {
+				if (module_density == (sz.side1 | i)) {
+					sz.side2 = i;
+					break;
+				}
+			}
+			/* If not, it's symmetrical */
+		} else {
+			sz.side2 = sz.side1;
+		}
+	}
+
+	/* SPD byte 31 is the memory size divided by 4 so we
+	 * need to muliply by 4 to get the total size.
 	 */
-	pci_write_config8(NB, PAM0, 0x30);
-	pci_write_config8(NB, PAM1, 0x33);
-	pci_write_config8(NB, PAM2, 0x33);
-	pci_write_config8(NB, PAM3, 0x33);
-	pci_write_config8(NB, PAM4, 0x33);
-	pci_write_config8(NB, PAM5, 0x33);
-	pci_write_config8(NB, PAM6, 0x33);
+	sz.side1 *= 4;
+	sz.side2 *= 4;
+	return sz;
+}
+/*
+   Sets DRAM attributes one DIMM at a time, based on SPD data
+   Northbridge settings that got set here:
+   
+   NBXCFG[31:24]
+   DRB0-DRB7
+   RPS 
+   DRAMC
+ */
+static void set_dram_row_attributes(void)
+{
+	int i, dra, drb, col, width, value, rps, edosd, ecc, nbxecc;
+	u8 bpr; // Top 8 bits of PGPOL
+	
+	edosd = 0;
+	rps = 0;
+	drb = 0;
+	bpr = 0;
+	nbxecc=0xff;
+	
+	for (i = 0; i < DIMM_SOCKETS; i++) {
+		unsigned device;
+		device = DIMM_SPD_BASE + i;
+	   	bpr >>= 2;
 
-	/* TODO: Set DRB0-DRB7. */
-	/* Currently this is hardcoded to one 64 MB DIMM in slot 0. */
-	pci_write_config8(NB, DRB0, 0x08);
-	pci_write_config8(NB, DRB1, 0x08);
-	pci_write_config8(NB, DRB2, 0x08);
-	pci_write_config8(NB, DRB3, 0x08);
-	pci_write_config8(NB, DRB4, 0x08);
-	pci_write_config8(NB, DRB5, 0x08);
-	pci_write_config8(NB, DRB6, 0x08);
-	pci_write_config8(NB, DRB7, 0x08);
+		/* First check if a DIMM is actually present. */
+		value = spd_read_byte(device, SPD_MEMORY_TYPE);
+		/* This is BX! We do EDO too! */
+		if (value == SPD_MEMORY_TYPE_EDO || value == SPD_MEMORY_TYPE_SDRAM) {
 
-	/* TODO: Set DRAMC. Don't enable refresh for now. */
-	pci_write_config8(NB, DRAMC, 0x08);
+			PRINT_DEBUG("Found ");
+			if (value == SPD_MEMORY_TYPE_EDO) {
+				edosd |= 0x02; 
+			} else if (value == SPD_MEMORY_TYPE_SDRAM) { 
+				edosd = edosd | 0x04; 
+			}
+			PRINT_DEBUG("DIMM in slot ");
+			PRINT_DEBUG_HEX8(i);
+			PRINT_DEBUG("\r\n");
 
-	/* TODO: Set RPS. Needs to be fixed for multiple DIMM support. */
-	pci_write_config16(NB, RPS, 0x0001);
+			if (edosd == 0x06) { 
+				print_err("Mixing EDO/SDRAM not supported\r\n");
+				die("HALT\r\n");
+			}
+			
+			/* "DRA" is our RPS for the two rows on this DIMM */
+			dra = 0;
 
+			/* columns */
+			col = spd_read_byte(device, SPD_NUM_COLUMNS);
+
+			/* Is this an ECC DIMM? (Actually this will be a 2 if so) */
+			/* TODO: Other register than NBXCFG also needs this ECC information */
+			ecc = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE);
+			
+			/* data width */
+			width = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB);
+			
+			/* Exclude error checking data width from page size calculations */
+			if (ecc) {
+			   value = spd_read_byte(device, SPD_ERROR_CHECKING_SDRAM_WIDTH);
+			   width -= value;
+			   /* ### ECC */
+			   /* Top 2 bits are clear to help set up NBXCFG */
+			   ecc &= 0x3f;  
+			} else {
+			   /* Without ECC, these top 2 bits should be 11 */
+			   ecc |= 0xc0;
+			} 
+			
+			/* calculate page size in bits */
+			value = ((1 << col) * width);
+
+			/* convert to Kilobytes */
+			dra = (value >> 13);
+
+			/* # of banks of DIMM (single or double sided) */
+			value = spd_read_byte(device, SPD_NUM_DIMM_BANKS);
+			
+			/* Once we have dra, col is done and can be reused,
+			 * So it's reused for number of banks
+			 */
+			col = spd_read_byte(device, SPD_NUM_BANKS_PER_SDRAM);
+
+			if (value == 1) {
+			   	/* Second bank of 1-bank DIMMs "doesn't have ECC" - or anything */
+				ecc |=0x80;
+				if (dra == 2) {
+				    dra = 0x0; /* 2KB */
+				} else if (dra == 4) {
+					dra = 0x1; /* 4KB */
+				} else if (dra == 8) {
+					dra = 0x2; /* 8KB */
+				} else {
+					dra = -1;
+				}
+				/* Sets a flag in PGPOL[BPR] if this DIMM has 4 banks per row */
+				if (col == 4) {
+					bpr |= 0x40;
+				}
+			} else if (value == 2) {
+				if (dra == 2) {
+				    dra = 0x0; /* 2KB */
+				} else if (dra == 4) {
+					dra = 0x05; /* 4KB */
+				} else if (dra == 8) {
+					dra = 0x0a; /* 8KB */
+				} else {
+					dra = -1;
+				}
+				/* Ditto */
+				if (col == 4) {
+					bpr |= 0xc0;
+				}
+			} else {
+				print_err("# of banks of DIMM not supported\r\n");
+				die("HALT\r\n");
+			}
+			if (dra == -1) {
+				print_err("Page size not supported\r\n");
+				die("HALT\r\n");
+			}
+
+			/* The 440BX supports asymmetrical dual-sided dimms (I can't test though) 
+			 * but can't handle DIMMs smaller than 8MB per
+			 * side or larger than 128MB per side.
+			 */
+			struct dimm_size sz = spd_get_dimm_size(device);
+			if ((sz.side1 < 8)) {
+				print_err("DIMMs smaller than 8MB per side\r\nare not supported on this northbridge\r\n");
+				die("HALT\r\n");
+			}
+			if ((sz.side1 > 128)) {
+				print_err ("DIMMs larger than 128MB per side\r\nare not supported on this northbridge\r\n");
+				die("HALT\r\n");
+			}
+			/* - End Memory compatibility checks - */
+
+			/* We need to divide size by 8 to set up the
+			 * DRB registers.
+			 */
+			drb += (sz.side1 / 8);
+			/* Builds the DRB for the next row in MSB so it gets placed in DRB[n+1]
+			 * where it belongs when written as a 16-bit word.
+			 */
+			drb &= 0xff;
+			drb |= (drb + (sz.side2 / 8)) << 8;
+ 
+		} else {
+#if 0
+			PRINT_DEBUG("No DIMM found in slot ");
+			PRINT_DEBUG_HEX8(i);
+			PRINT_DEBUG("\r\n");
+#endif			
+
+			/* If there's no DIMM in the slot, set dra value to 0x00. */
+			dra = 0x00;
+			ecc = 0xc0;
+			/* Still have to propagate DRB over */
+			drb &= 0xff;
+			drb |= (drb << 8);
+		}
+
+		pci_write_config16(NB, DRB+(2*i), drb);
+#if 0
+		PRINT_DEBUG("DRB has been set to 0x");
+		PRINT_DEBUG_HEX16(drb);
+		PRINT_DEBUG("\r\n");
+#endif		
+			
+		/* Brings the upper DRB back down to be base for
+		 * DRB calculations for the next two rows.
+		 */
+		drb >>= 8;
+			
+		rps |= (dra & 0x0f) << (i*4);
+		nbxecc = (nbxecc >> 2) | (ecc & 0xc0); 
+	}
+	/* Set Paging Policy Register */
+	pci_write_config8(NB, PGPOL+1, bpr);
+	PRINT_DEBUG("PGPOL[BPR] has been set to 0x");
+	PRINT_DEBUG_HEX8(bpr);
+	PRINT_DEBUG("\r\n");
+	/* Set DRAM Row Page Size Register */
+	pci_write_config16(NB, RPS, rps);
+	PRINT_DEBUG("RPS has been set to 0x");
+	PRINT_DEBUG_HEX16(rps);
+	PRINT_DEBUG("\r\n");
+	/* ### ECC */
+	pci_write_config8(NB, NBXCFG+3, nbxecc);
+	PRINT_DEBUG("NBXECC[31:24] has been set to 0x");
+	PRINT_DEBUG_HEX8(nbxecc);
+	PRINT_DEBUG("\r\n");
+
+	/* Set DRAMC[4:3] to proper memory type (EDO/SDRAM)
+	 * TODO: Account for registered SDRAM
+	 */
+	edosd &= 0x07;
+	if (edosd & 0x02) {
+	   edosd |= 0x00;
+	} else if (edosd & 0x04) {
+	   edosd |= 0x08;
+	}
+	edosd &= 0x18; 
+	/* edosd by now has been transformed to the value needed for DRAMC[4:3] */
+	value = pci_read_config8(NB, DRAMC) & 0xe7;
+	value |= edosd;
+	pci_write_config8(NB, DRAMC, value);
+	PRINT_DEBUG("DRAMC has been set to 0x");
+	PRINT_DEBUG_HEX8(value);
+	PRINT_DEBUG("\r\n");
+	
+}
+
+static void sdram_set_spd_registers(void)
+{
+	/* Setup DRAM Row Boundary Registers and other attributes */
+	set_dram_row_attributes();
+
 	/* TODO: Set SDRAMC. */
 	pci_write_config16(NB, SDRAMC, 0x0010);	/* SDRAMPWR=1: 4 DIMM config */
 
-	/* TODO: Set PGPOL. */
-	// pci_write_config16(NB, PGPOL, 0x0107);
-	pci_write_config16(NB, PGPOL, 0x0123);
-
-	/* TODO: Set NBXCFG. */
-	// pci_write_config32(NB, NBXCFG, 0x0100220c); // FIXME?
-	pci_write_config32(NB, NBXCFG, 0xff00800c);
-
+	/* TODO */
+	set_dram_buffer_strength();
+	
 	/* TODO: Set PMCR? */
 	// pci_write_config8(NB, PMCR, 0x14);
 	pci_write_config8(NB, PMCR, 0x10);
 
 	/* TODO? */
-	pci_write_config8(NB, PCI_LATENCY_TIMER, 0x40);
 	pci_write_config8(NB, DRAMT, 0x03);
-	pci_write_config8(NB, MBSC, 0x03);
-	pci_write_config8(NB, SCRR, 0x38);
 }
 
+static void sdram_set_timing(unsigned int mhz) {
+	   /* TODO */
+
+} 
+
 static void sdram_enable(void)
 {
 	int i;
Index: src/mainboard/asus/p2b-ls/Kconfig
===================================================================
--- src/mainboard/asus/p2b-ls/Kconfig	(revision 0)
+++ src/mainboard/asus/p2b-ls/Kconfig	(revision 0)
@@ -0,0 +1,52 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Keith Hui <buurin@gmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config BOARD_ASUS_P2B_LS
+	bool "P2B-LS"
+	select ARCH_X86
+	select CPU_INTEL_SLOT_1
+	select NORTHBRIDGE_INTEL_I440BX
+	select SOUTHBRIDGE_INTEL_I82371EB
+	select SUPERIO_WINBOND_W83977TF
+	select ROMCC
+	select HAVE_PIRQ_TABLE
+	select UDELAY_TSC
+	select BOARD_ROMSIZE_KB_256
+
+config MAINBOARD_DIR
+	string
+	default asus/p2b-ls
+	depends on BOARD_ASUS_P2B_LS
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "P2B-LS"
+	depends on BOARD_ASUS_P2B_LS
+
+config HAVE_OPTION_TABLE
+	bool
+	default n
+	depends on BOARD_ASUS_P2B_LS
+
+config IRQ_SLOT_COUNT
+	int
+	default 8
+	depends on BOARD_ASUS_P2B_LS
+
Index: src/mainboard/asus/p2b-ls/romstage.c
===================================================================
--- src/mainboard/asus/p2b-ls/romstage.c	(revision 0)
+++ src/mainboard/asus/p2b-ls/romstage.c	(revision 0)
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+#define __PRE_RAM__
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <arch/hlt.h>
+#include <stdlib.h>
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
+#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "northbridge/intel/i440bx/raminit.h"
+#include "lib/debug.c"
+#include "pc80/udelay_io.c"
+#include "lib/delay.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "cpu/x86/bist.h"
+/* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */
+#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
+
+static inline int spd_read_byte(unsigned int device, unsigned int address)
+{
+	return smbus_read_byte(device, address);
+}
+
+#include "northbridge/intel/i440bx/raminit.c"
+#include "northbridge/intel/i440bx/debug.c"
+
+static void main(unsigned long bist)
+{
+	if (bist == 0)
+		early_mtrr_init();
+
+	/* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */
+	w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	uart_init();
+	console_init();
+	report_bist_failure(bist);
+
+	/* Enable access to the full ROM chip, needed very early by CBFS. */
+	i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
+
+	enable_smbus();
+	/* dump_spd_registers(); */
+	sdram_set_registers();
+	sdram_set_spd_registers();
+	sdram_enable();
+	/* ram_check(0, 655360); */
+}
Index: src/mainboard/asus/p2b-ls/devicetree.cb
===================================================================
--- src/mainboard/asus/p2b-ls/devicetree.cb	(revision 0)
+++ src/mainboard/asus/p2b-ls/devicetree.cb	(revision 0)
@@ -0,0 +1,59 @@
+chip northbridge/intel/i440bx		# Northbridge
+  device apic_cluster 0 on		# APIC cluster
+    chip cpu/intel/slot_1		# CPU
+      device apic 0 on end		# APIC
+    end
+  end
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    device pci 1.0 on end		# PCI/AGP bridge
+    chip southbridge/intel/i82371eb	# Southbridge
+      device pci 4.0 on			# ISA bridge
+        chip superio/winbond/w83977tf	# Super I/O (FIXME: It's W83977EF!)
+          device pnp 3f0.0 on		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 3f0.1 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 3f0.2 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 3f0.3 on		# COM2 / IR
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 3f0.5 on		# PS/2 keyboard
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1		# PS/2 keyboard interrupt
+            irq 0x72 = 12		# PS/2 mouse interrupt
+          end
+          device pnp 3f0.7 on		# GPIO 1
+          end
+          device pnp 3f0.8 on		# GPIO 2
+          end
+          device pnp 3f0.a on		# ACPI
+          end
+        end
+      end
+      device pci 4.1 on	end		# IDE
+      device pci 4.2 on	end		# USB
+      device pci 4.3 on end		# ACPI
+      device pci 6.0 on end             # Onboard SCSI
+      device pci 7.0 on end             # Onboard LAN
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+      register "ide_legacy_enable" = "1"
+      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+      register "ide0_drive0_udma33_enable" = "0"
+      register "ide0_drive1_udma33_enable" = "0"
+      register "ide1_drive0_udma33_enable" = "0"
+      register "ide1_drive1_udma33_enable" = "0"
+    end
+  end
+end
Index: src/mainboard/asus/p2b-ls/irq_tables.c
===================================================================
--- src/mainboard/asus/p2b-ls/irq_tables.c	(revision 0)
+++ src/mainboard/asus/p2b-ls/irq_tables.c	(revision 0)
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Keith Hui <buurin@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,
+	PIRQ_VERSION,
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+	0x00,			/* Interrupt router bus */
+	(0x04 << 3) | 0x0,	/* Interrupt router device */
+	0,			/* IRQs devoted exclusively to PCI usage */
+	0x8086,			/* Vendor */
+	0x122e,			/* Device */
+	0,			/* Miniport */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0x10,			/* Checksum (has to be set to some value that
+				 * would give 0 after the sum of all bytes
+				 * for this structure (including checksum).
+                                 */
+	{
+		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+		{0x00, (0x0c << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x1, 0x0},
+		{0x00, (0x0b << 3) | 0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}}, 0x2, 0x0},
+		{0x00, (0x0a << 3) | 0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}}, 0x3, 0x0},
+		{0x00, (0x09 << 3) | 0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x4, 0x0},
+		{0x00, (0x04 << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0},
+		{0x00, (0x01 << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0},
+		{0x00, (0x06 << 3) | 0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x0, 0x0},
+		{0x00, (0x07 << 3) | 0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}}, 0x0, 0x0},
+	}
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	return copy_pirq_routing_table(addr);
+}
Index: src/mainboard/asus/p2b-ls/chip.h
===================================================================
--- src/mainboard/asus/p2b-ls/chip.h	(revision 0)
+++ src/mainboard/asus/p2b-ls/chip.h	(revision 0)
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+struct mainboard_config {};
Index: src/mainboard/asus/p2b-ls/mainboard.c
===================================================================
--- src/mainboard/asus/p2b-ls/mainboard.c	(revision 0)
+++ src/mainboard/asus/p2b-ls/mainboard.c	(revision 0)
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations mainboard_ops = {
+	CHIP_NAME("ASUS P2B-LS Mainboard")
+};
Index: src/mainboard/asus/Kconfig
===================================================================
--- src/mainboard/asus/Kconfig	(revision 5184)
+++ src/mainboard/asus/Kconfig	(working copy)
@@ -27,6 +27,7 @@
 source "src/mainboard/asus/p2b/Kconfig"
 source "src/mainboard/asus/p2b-d/Kconfig"
 source "src/mainboard/asus/p2b-ds/Kconfig"
+source "src/mainboard/asus/p2b-ls/Kconfig"
 source "src/mainboard/asus/p2b-f/Kconfig"
 source "src/mainboard/asus/p3b-f/Kconfig"
 source "src/mainboard/asus/m2v-mx_se/Kconfig"
