Here is final Coreboot image info with debug FSP.
Performing operation on 'COREBOOT' region...
Name Offset Type Size
cbfs master header 0x0 cbfs header 32
fallback/romstage 0x80 stage 29996
config 0x7640 raw 515
revision 0x7880 raw 570
cmos_layout.bin 0x7b00 cmos_layout 1096
fallback/dsdt.aml 0x7f80 raw 12465
payload_config 0xb080 raw 1563
payload_revision 0xb700 raw 267
(empty) 0xb880 null 17944
mrc.cache 0xfec0 mrc_cache 65536
cpu_microcode_blob.bin 0x1ff00 microcode 208896
fallback/ramstage 0x52f80 stage 54702
fallback/payload 0x60580 payload 63348
pci8086,0f31.rom 0x6fd40 optionrom 65536
(empty) 0x7fdc0 null 1245400
fsp.bin 0x1afec0 fsp 294912
(empty) 0x1f7f00 null 31064
bootblock 0x1ff880 bootblock 1560
Built intel/bayleybay_fsp (Bayley Bay CRB (FSP))
Thanks,
Kathappan
From: Kathappan E
Sent: 09 May 2016 12:35
To: 'Aaron Durbin' <adurbin@google.com>; 'Zoran Stojsavljevic' <zoran.stojsavljevic@gmail.com>
Cc: coreboot@coreboot.org
Subject: RE: [coreboot] Unable to build coreboot with Intel FSP debug binary on BayleyBay
Hi Aaron/Zoran,
Thank you for your inputs.
After adjusting FSP_LOC Kconfig (Intel FSP Binary location in CBFS in
menuconfig) variable as it is configured in FSP binary, coreboot is getting build with debug FSP binary.
I see the base location of FSP binary using BCT tool as below.
Release FSP Binary (BAYTRAIL_FSP_GOLD_004_22-MAY-2015.fd) ==> 0xFFFC0000
Debug FSP Binary (BAYTRAIL_FSP_GOLD_004_22-MAY-2015_DEBUG.fd) ==> 0xFFFB0000
Thanks,
Kathappan
-----Original Message-----
From: Aaron Durbin [mailto:adurbin@google.com]
Sent: 06 May 2016 19:47
To: Kathappan E <Kathappan.E@LntTechservices.com>
Cc: coreboot@coreboot.org
Subject: Re: [coreboot] Unable to build coreboot with Intel FSP debug binary on BayleyBay
On Fri, May 6, 2016 at 12:39 AM, Kathappan E <Kathappan.E@lnttechservices.com> wrote:
> Hi all,
>
>
>
> I am able to build Coreboot with FSP Baytrail release
> binary(BAYTRAIL_FSP_GOLD_004_22-MAY-2015.fd).
>
>
>
> But I am unable to build with FSP Baytrail debug binary
> (BAYTRAIL_FSP_GOLD_004_22-MAY-2015_DEBUG.fd) and it throws the below
> error says that binary size is large and fails to add into image.
>
>
>
> The sections containing CBFSes are: COREBOOT
>
> Performing operation on 'COREBOOT' region...
>
> Created CBFS (capacity = 2096856 bytes)
>
> Performing operation on 'COREBOOT' region...
>
> Performing operation on 'COREBOOT' region...
>
> CBFS fsp.bin
>
> Performing operation on 'COREBOOT' region...
>
> E: Not enough space for content.
>
> E: Could not add [fsp, 294912 bytes (288 KB)@0x1bff00]; too big?
>
> E: Failed to add '../intel/fsp/baytrail/BAYTRAIL_FSP_D.fd' into ROM image.
>
> E: Failed while operating on 'COREBOOT' region!
>
> E: The image will be left unmodified.
>
> make: *** [build/coreboot.pre] Error 1
>
>
>
> Can you please anyone help me on this?
>
You likely need to adjust the FSP_LOC kconfig variable to match the debug FSP binary. Most likely the debug binary is large and not linked at the same address which in this case breaks building because there's not enough flash space.
>
>
> Thanks in advance,
>
> Kathappan
>
> L&T Technology Services Ltd
>
>
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