Index: cbv2/src/northbridge/intel/i440bx/northbridge.c
===================================================================
--- cbv2.orig/src/northbridge/intel/i440bx/northbridge.c
+++ cbv2/src/northbridge/intel/i440bx/northbridge.c
@@ -36,21 +36,6 @@ static const struct pci_driver northbrid
 
 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
 
-static void pci_domain_read_resources(device_t dev)
-{
-	struct resource *resource;
-
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
-	resource->limit = 0xffffUL;
-	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
-	/* Initialize the system wide memory resources constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
-	resource->limit = 0xffffffffULL;
-	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
 static void ram_resource(device_t dev, unsigned long index,
 	unsigned long basek, unsigned long sizek)
 {
@@ -95,7 +80,7 @@ static uint32_t find_pci_tolm(struct bus
 extern uint64_t high_tables_base, high_tables_size;
 #endif
 
-static void pci_domain_set_resources(device_t dev)
+static void i440bx_domain_set_resources(device_t dev)
 {
 	device_t mc_dev;
 	uint32_t pci_tolm;
@@ -140,15 +125,9 @@ static void pci_domain_set_resources(dev
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-	return max;
-}
-
 static struct device_operations pci_domain_ops = {
 	.read_resources		= pci_domain_read_resources,
-	.set_resources		= pci_domain_set_resources,
+	.set_resources		= i440bx_domain_set_resources,
 	.enable_resources	= enable_childrens_resources,
 	.init			= 0,
 	.scan_bus		= pci_domain_scan_bus,
Index: cbv2/src/cpu/emulation/qemu-x86/northbridge.c
===================================================================
--- cbv2.orig/src/cpu/emulation/qemu-x86/northbridge.c
+++ cbv2/src/cpu/emulation/qemu-x86/northbridge.c
@@ -11,21 +11,6 @@
 
 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
 
-static void pci_domain_read_resources(device_t dev)
-{
-	struct resource *resource;
-
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
-	resource->limit = 0xffffUL;
-	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
-	/* Initialize the system wide memory resources constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
-	resource->limit = 0xffffffffULL;
-	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
 static void ram_resource(device_t dev, unsigned long index,
 	unsigned long basek, unsigned long sizek)
 {
@@ -70,7 +55,7 @@ static uint32_t find_pci_tolm(struct bus
 extern uint64_t high_tables_base, high_tables_size;
 #endif
 
-static void pci_domain_set_resources(device_t dev)
+static void cpu_pci_domain_set_resources(device_t dev)
 {
 	static const uint8_t ramregs[] = {
 		0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57
@@ -127,15 +112,34 @@ static void pci_domain_set_resources(dev
 	assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
+static void cpu_pci_domain_read_resources(struct device *dev)
 {
-	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-	return max;
+	struct resource *res;
+
+	pci_domain_read_resources(dev);
+
+	/* Reserve space for the IOAPIC.  This should be in the Southbridge,
+	 * but I couldn't tell which device to put it in. */
+	res = new_resource(dev, 2);
+	res->base = 0xfec00000UL;
+	res->size = 0x100000UL;
+	res->limit = 0xffffffffUL;
+	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
+		     IORESOURCE_ASSIGNED;
+
+	/* Reserve space for the LAPIC.  There's one in every processor, but
+	 * the space only needs to be reserved once, so we do it here. */
+	res = new_resource(dev, 3);
+	res->base = 0xfee00000UL;
+	res->size = 0x10000UL;
+	res->limit = 0xffffffffUL;
+	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
+		     IORESOURCE_ASSIGNED;
 }
 
 static struct device_operations pci_domain_ops = {
-	.read_resources		= pci_domain_read_resources,
-	.set_resources		= pci_domain_set_resources,
+	.read_resources		= cpu_pci_domain_read_resources,
+	.set_resources		= cpu_pci_domain_set_resources,
 	.enable_resources	= enable_childrens_resources,
 	.init			= 0,
 	.scan_bus		= pci_domain_scan_bus,
Index: cbv2/src/devices/pci_device.c
===================================================================
--- cbv2.orig/src/devices/pci_device.c
+++ cbv2/src/devices/pci_device.c
@@ -355,11 +355,8 @@ static void pci_read_bases(struct device
 	compact_resources(dev);
 }
 
-static void pci_set_resource(struct device *dev, struct resource *resource);
-
 static void pci_record_bridge_resource(struct device *dev, resource_t moving,
-				       unsigned index, unsigned long mask,
-				       unsigned long type)
+				       unsigned index, unsigned long type)
 {
 	/* Initialize the constraints on the current bus. */
 	struct resource *resource;
@@ -379,21 +376,6 @@ static void pci_record_bridge_resource(s
 		resource->align = gran;
 		resource->limit = moving | (step - 1);
 		resource->flags = type | IORESOURCE_PCI_BRIDGE;
-		compute_allocate_resource(&dev->link[0], resource, mask, type);
-		/* If there is nothing behind the resource,
-		 * clear it and forget it.
-		 */
-		if (resource->size == 0) {
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
-			resource->base = moving;
-#else
-			resource->base = moving & 0xffffffff;
-#endif
-			resource->flags |= IORESOURCE_ASSIGNED;
-			resource->flags &= ~IORESOURCE_STORED;
-			pci_set_resource(dev, resource);
-			resource->flags = 0;
-		}
 	}
 	return;
 }
@@ -414,8 +396,7 @@ static void pci_bridge_read_bases(struct
 	moving = moving_base & moving_limit;
 
 	/* Initialize the I/O space constraints on the current bus. */
-	pci_record_bridge_resource(dev, moving, PCI_IO_BASE,
-				   IORESOURCE_IO, IORESOURCE_IO);
+	pci_record_bridge_resource(dev, moving, PCI_IO_BASE, IORESOURCE_IO);
 
 	/* See if the bridge prefmem resources are implemented. */
 	moving_base =
@@ -434,7 +415,6 @@ static void pci_bridge_read_bases(struct
 	moving = moving_base & moving_limit;
 	/* Initialize the prefetchable memory constraints on the current bus. */
 	pci_record_bridge_resource(dev, moving, PCI_PREF_MEMORY_BASE,
-				   IORESOURCE_MEM | IORESOURCE_PREFETCH,
 				   IORESOURCE_MEM | IORESOURCE_PREFETCH);
 
 	/* See if the bridge mem resources are implemented. */
@@ -445,7 +425,6 @@ static void pci_bridge_read_bases(struct
 
 	/* Initialize the memory resources on the current bus. */
 	pci_record_bridge_resource(dev, moving, PCI_MEMORY_BASE,
-				   IORESOURCE_MEM | IORESOURCE_PREFETCH,
 				   IORESOURCE_MEM);
 
 	compact_resources(dev);
@@ -462,6 +441,25 @@ void pci_bus_read_resources(struct devic
 	pci_bridge_read_bases(dev);
 	pci_read_bases(dev, 2);
 	pci_get_rom_resource(dev, PCI_ROM_ADDRESS1);
+	if (dev->links ==1)
+		read_resources(&dev->link[0]);
+}
+
+void pci_domain_read_resources(struct device *dev)
+{
+	struct resource *res;
+
+	/* Initialize the system-wide I/O space constraints. */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	res->limit = 0xffffUL;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED;
+
+	/* Initialize the system-wide memory resources constraints. */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	res->limit = 0xffffffffULL;
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED;
 }
 
 static void pci_set_resource(struct device *dev, struct resource *resource)
@@ -510,6 +508,17 @@ static void pci_set_resource(struct devi
 
 	/* Now store the resource. */
 	resource->flags |= IORESOURCE_STORED;
+
+	/* PCI Bridges have no enable bit.  They are disabled if the base of
+	 * the range is greater than the limit.  If the size is zero, disable
+	 * by setting the base = limit and end = limit - 2^gran.
+	 */
+	if (resource->size == 0 && (resource->flags & IORESOURCE_PCI_BRIDGE)) {
+		base = resource->limit;
+		end = resource->limit - (1 << resource->gran);
+		resource->base = base;
+	}
+
 	if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) {
 		unsigned long base_lo, base_hi;
 		/* Some chipsets allow us to set/clear the I/O bit
@@ -526,24 +535,16 @@ static void pci_set_resource(struct devi
 		}
 	} else if (resource->index == PCI_IO_BASE) {
 		/* Set the I/O ranges. */
-		compute_allocate_resource(&dev->link[0], resource,
-					  IORESOURCE_IO, IORESOURCE_IO);
 		pci_write_config8(dev, PCI_IO_BASE, base >> 8);
 		pci_write_config16(dev, PCI_IO_BASE_UPPER16, base >> 16);
 		pci_write_config8(dev, PCI_IO_LIMIT, end >> 8);
 		pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, end >> 16);
 	} else if (resource->index == PCI_MEMORY_BASE) {
 		/* Set the memory range. */
-		compute_allocate_resource(&dev->link[0], resource,
-					  IORESOURCE_MEM | IORESOURCE_PREFETCH,
-					  IORESOURCE_MEM);
 		pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
 		pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16);
 	} else if (resource->index == PCI_PREF_MEMORY_BASE) {
 		/* Set the prefetchable memory range. */
-		compute_allocate_resource(&dev->link[0], resource,
-					  IORESOURCE_MEM | IORESOURCE_PREFETCH,
-					  IORESOURCE_MEM | IORESOURCE_PREFETCH);
 		pci_write_config16(dev, PCI_PREF_MEMORY_BASE, base >> 16);
 		pci_write_config32(dev, PCI_PREF_BASE_UPPER32, base >> 32);
 		pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, end >> 16);
@@ -1179,6 +1180,22 @@ unsigned int pci_scan_bridge(struct devi
 }
 
 /**
+ * @brief Scan a PCI domain.
+ *
+ * This function is the default scan_bus() method for PCI domains.
+ *
+ * @param dev pointer to the domain
+ * @param max the highest bus number assgined up to now
+ *
+ * @return The maximum bus number found, after scanning all subordinate busses
+ */
+unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
+{
+	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
+	return max;
+}
+
+/**
  * Tell the EISA int controller this int must be level triggered.
  *
  * THIS IS A KLUDGE -- sorry, this needs to get cleaned up.
Index: cbv2/src/include/device/device.h
===================================================================
--- cbv2.orig/src/include/device/device.h
+++ cbv2/src/include/device/device.h
@@ -141,6 +141,10 @@ void show_all_devs_resources(int debug_l
 #define DEVICE_MEM_ALIGN 4096
 
 extern struct device_operations default_dev_ops_root;
+void pci_domain_read_resources(struct device *dev);
+void pci_domain_set_resources(struct device *dev);
+unsigned int pci_domain_scan_bus(struct device *dev, unsigned int max);
+void read_resources(struct bus *bus);
 void root_dev_read_resources(device_t dev);
 void root_dev_set_resources(device_t dev);
 unsigned int scan_static_bus(device_t bus, unsigned int max);
Index: cbv2/src/southbridge/intel/i82371eb/i82371eb_isa.c
===================================================================
--- cbv2.orig/src/southbridge/intel/i82371eb/i82371eb_isa.c
+++ cbv2/src/southbridge/intel/i82371eb/i82371eb_isa.c
@@ -55,8 +55,23 @@ static void isa_init(struct device *dev)
 	isa_dma_init();
 }
 
-static const struct device_operations isa_ops = {
-	.read_resources		= pci_dev_read_resources,
+static void sb_read_resources(struct device *dev)
+{
+	struct resource *res;
+
+	pci_dev_read_resources(dev);
+
+	res = new_resource(dev, 2);
+	res->base = 0x0UL;
+	res->size = 0x1000UL;
+	res->limit = 0xffffUL;
+	res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_STORED |
+		     IORESOURCE_ASSIGNED;
+
+}
+
+const struct device_operations isa_ops = {
+	.read_resources		= sb_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
 	.init			= isa_init,
Index: cbv2/src/devices/root_device.c
===================================================================
--- cbv2.orig/src/devices/root_device.c
+++ cbv2/src/devices/root_device.c
@@ -34,29 +34,7 @@
  */
 void root_dev_read_resources(device_t root)
 {
-	struct resource *resource;
-
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(root, 0);
-	resource->base  = 0x400;
-	resource->size  = 0;
-	resource->align = 0;
-	resource->gran  = 0;
-	resource->limit = 0xffffUL;
-	resource->flags = IORESOURCE_IO;
-	compute_allocate_resource(&root->link[0], resource, 
-		IORESOURCE_IO, IORESOURCE_IO);
-
-	/* Initialize the system wide memory resources constraints */
-	resource = new_resource(root, 1);
-	resource->base  = 0;
-	resource->size  = 0;
-	resource->align = 0;
-	resource->gran  = 0;
-	resource->limit = 0xffffffffUL;
-	resource->flags = IORESOURCE_MEM;
-	compute_allocate_resource(&root->link[0], resource,
-		IORESOURCE_MEM, IORESOURCE_MEM);
+	printk_err("%s should never be called.\n", __func__);
 }
 
 /**
@@ -68,14 +46,7 @@ void root_dev_read_resources(device_t ro
  */
 void root_dev_set_resources(device_t root)
 {
-	struct bus *bus;
-
-	bus = &root->link[0];
-	compute_allocate_resource(bus,
-		&root->resource[0], IORESOURCE_IO, IORESOURCE_IO);
-	compute_allocate_resource(bus, 
-		&root->resource[1], IORESOURCE_MEM, IORESOURCE_MEM);
-	assign_resources(bus);
+	printk_err("%s should never be called.\n", __func__);
 }
 
 /**
Index: cbv2/src/northbridge/amd/amdk8/northbridge.c
===================================================================
--- cbv2.orig/src/northbridge/amd/amdk8/northbridge.c
+++ cbv2/src/northbridge/amd/amdk8/northbridge.c
@@ -297,7 +297,7 @@ static int reg_useable(unsigned reg,
 		if (!dev)
 			continue;
 		for(link = 0; !res && (link < 3); link++) {
-			res = probe_resource(dev, 0x100 + (reg | link));
+			res = probe_resource(dev, IOINDEX(0x100 + reg, link));
 		}
 	}
 	result = 2;
@@ -335,7 +335,7 @@ static struct resource *amdk8_find_iopai
 		reg = free_reg;
 	}
 	if (reg > 0) {
-		resource = new_resource(dev, 0x100 + (reg | link));
+		resource = new_resource(dev, IOINDEX(0x100 + reg, link));
 	}
 	return resource;
 }
@@ -362,7 +362,7 @@ static struct resource *amdk8_find_mempa
 		reg = free_reg;
 	}
 	if (reg > 0) {
-		resource = new_resource(dev, 0x100 + (reg | link));
+		resource = new_resource(dev, IOINDEX(0x100 + reg, link));
 	}
 	return resource;
 }
@@ -380,8 +380,6 @@ static void amdk8_link_read_bases(device
 		resource->gran  = log2(HT_IO_HOST_ALIGN);
 		resource->limit = 0xffffUL;
 		resource->flags = IORESOURCE_IO;
-		compute_allocate_resource(&dev->link[link], resource,
-			IORESOURCE_IO, IORESOURCE_IO);
 	}
 
 	/* Initialize the prefetchable memory constraints on the current bus */
@@ -393,9 +391,6 @@ static void amdk8_link_read_bases(device
 		resource->gran  = log2(HT_MEM_HOST_ALIGN);
 		resource->limit = 0xffffffffffULL;
 		resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
-		compute_allocate_resource(&dev->link[link], resource,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH);
 	}
 
 	/* Initialize the memory constraints on the current bus */
@@ -407,9 +402,6 @@ static void amdk8_link_read_bases(device
 		resource->gran  = log2(HT_MEM_HOST_ALIGN);
 		resource->limit = 0xffffffffffULL;
 		resource->flags = IORESOURCE_MEM;
-		compute_allocate_resource(&dev->link[link], resource,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH,
-			IORESOURCE_MEM);
 	}
 }
 
@@ -420,6 +412,7 @@ static void amdk8_read_resources(device_
 	for(link = 0; link < dev->links; link++) {
 		if (dev->link[link].children) {
 			amdk8_link_read_bases(dev, nodeid, link);
+			read_resources(&dev->link[link]);
 		}
 	}
 }
@@ -432,11 +425,15 @@ static void amdk8_set_resource(device_t 
 
 	/* Make certain the resource has actually been set */
 	if (!(resource->flags & IORESOURCE_ASSIGNED)) {
+		printk_err("%s: can't set unassigned resource @%lx %lx\n",
+			   __func__, resource->index, resource->flags);
 		return;
 	}
 
 	/* If I have already stored this resource don't worry about it */
 	if (resource->flags & IORESOURCE_STORED) {
+		printk_err("%s: can't set stored resource @%lx %lx\n", __func__,
+			   resource->index, resource->flags);
 		return;
 	}
 
@@ -448,6 +445,10 @@ static void amdk8_set_resource(device_t 
 	if (resource->index < 0x100) {
 		return;
 	}
+
+	if (resource->size == 0)
+		return;
+
 	/* Get the base address */
 	rbase = resource->base;
 
@@ -456,12 +457,10 @@ static void amdk8_set_resource(device_t 
 
 	/* Get the register and link */
 	reg  = resource->index & 0xfc;
-	link = resource->index & 3;
+	link = IOINDEX_LINK(resource->index);
 
 	if (resource->flags & IORESOURCE_IO) {
 		uint32_t base, limit;
-		compute_allocate_resource(&dev->link[link], resource,
-			IORESOURCE_IO, IORESOURCE_IO);
 		base  = f1_read_config32(reg);
 		limit = f1_read_config32(reg + 0x4);
 		base  &= 0xfe000fcc;
@@ -486,9 +485,6 @@ static void amdk8_set_resource(device_t 
 	}
 	else if (resource->flags & IORESOURCE_MEM) {
 		uint32_t base, limit;
-		compute_allocate_resource(&dev->link[link], resource,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH,
-			resource->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH));
 		base  = f1_read_config32(reg);
 		limit = f1_read_config32(reg + 0x4);
 		base  &= 0x000000f0;
@@ -634,7 +630,7 @@ struct chip_operations northbridge_amd_a
 	.enable_dev = 0,
 };
 
-static void pci_domain_read_resources(device_t dev)
+static void amdk8_domain_read_resources(device_t dev)
 {
 	struct resource *resource;
 	unsigned reg;
@@ -655,48 +651,21 @@ static void pci_domain_read_resources(de
 			if (reg_dev) {
 				/* Reserve the resource  */
 				struct resource *reg_resource;
-				reg_resource = new_resource(reg_dev, 0x100 + (reg | link));
+				reg_resource = new_resource(reg_dev, IOINDEX(0x100 + reg, link));
 				if (reg_resource) {
 					reg_resource->flags = 1;
 				}
 			}
 		}
 	}
-#if CONFIG_PCI_64BIT_PREF_MEM == 0
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	resource->base  = 0x400;
-	resource->limit = 0xffffUL;
-	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 
-	/* Initialize the system wide memory resources constraints */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	resource->limit = 0xfcffffffffULL;
-	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-#else
-	/* Initialize the system wide io space constraints */
-	resource = new_resource(dev, 0);
-	resource->base  = 0x400;
-	resource->limit = 0xffffUL;
-	resource->flags = IORESOURCE_IO;
-	compute_allocate_resource(&dev->link[0], resource,
-		IORESOURCE_IO, IORESOURCE_IO);
+	pci_domain_read_resources(dev);
 
+#if CONFIG_PCI_64BIT_PREF_MEM == 1
 	/* Initialize the system wide prefetchable memory resources constraints */
-	resource = new_resource(dev, 1);
-	resource->limit = 0xfcffffffffULL;
-	resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
-	compute_allocate_resource(&dev->link[0], resource,
-		IORESOURCE_MEM | IORESOURCE_PREFETCH,
-		IORESOURCE_MEM | IORESOURCE_PREFETCH);
-
-	/* Initialize the system wide memory resources constraints */
 	resource = new_resource(dev, 2);
 	resource->limit = 0xfcffffffffULL;
-	resource->flags = IORESOURCE_MEM;
-	compute_allocate_resource(&dev->link[0], resource,
-		IORESOURCE_MEM | IORESOURCE_PREFETCH,
-		IORESOURCE_MEM);
+	resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
 #endif
 }
 
@@ -898,7 +867,7 @@ static uint32_t hoist_memory(unsigned lo
 extern uint64_t high_tables_base, high_tables_size;
 #endif
 
-static void pci_domain_set_resources(device_t dev)
+static void amdk8_domain_set_resources(device_t dev)
 {
 #if CONFIG_PCI_64BIT_PREF_MEM == 1
 	struct resource *io, *mem1, *mem2;
@@ -964,13 +933,7 @@ static void pci_domain_set_resources(dev
 	last = &dev->resource[dev->resources];
 	for(resource = &dev->resource[0]; resource < last; resource++)
 	{
-#if 1
 		resource->flags |= IORESOURCE_ASSIGNED;
-		resource->flags &= ~IORESOURCE_STORED;
-#endif
-		compute_allocate_resource(&dev->link[0], resource,
-			BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
-
 		resource->flags |= IORESOURCE_STORED;
 		report_resource_stored(dev, resource, "");
 
@@ -1125,7 +1088,7 @@ static void pci_domain_set_resources(dev
 
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
+static unsigned int amdk8_domain_scan_bus(device_t dev, unsigned int max)
 {
 	unsigned reg;
 	int i;
@@ -1160,11 +1123,11 @@ static unsigned int pci_domain_scan_bus(
 }
 
 static struct device_operations pci_domain_ops = {
-	.read_resources   = pci_domain_read_resources,
-	.set_resources    = pci_domain_set_resources,
+	.read_resources   = amdk8_domain_read_resources,
+	.set_resources    = amdk8_domain_set_resources,
 	.enable_resources = enable_childrens_resources,
 	.init             = 0,
-	.scan_bus         = pci_domain_scan_bus,
+	.scan_bus         = amdk8_domain_scan_bus,
 	.ops_pci_bus      = &pci_cf8_conf1,
 };
 
Index: cbv2/src/devices/cardbus_device.c
===================================================================
--- cbv2.orig/src/devices/cardbus_device.c
+++ cbv2/src/devices/cardbus_device.c
@@ -77,8 +77,6 @@ static void cardbus_size_bridge_resource
 	resource = find_resource(dev, index);
 	if (resource) {
 		min_size = resource->size;
-		compute_allocate_resource(&dev->link[0], resource, 
-			resource->flags, resource->flags);
 		/* Allways allocate at least the miniumum size to a
 		 * cardbus bridge in case a new card is plugged in.
 		 */
Index: cbv2/src/southbridge/amd/amd8111/amd8111_lpc.c
===================================================================
--- cbv2.orig/src/southbridge/amd/amd8111/amd8111_lpc.c
+++ cbv2/src/southbridge/amd/amd8111/amd8111_lpc.c
@@ -162,15 +162,26 @@ static void amd8111_lpc_read_resources(d
 {
 	struct resource *res;
 
-	/* Get the normal pci resources of this device */
+	/* Get the normal PCI resources of this device. */
 	pci_dev_read_resources(dev);
 
-	/* Add an extra subtractive resource for both memory and I/O */
+	/* Add an extra subtractive resource for both memory and I/O. */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-	
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
 static void amd8111_lpc_enable_resources(device_t dev)
Index: cbv2/src/southbridge/intel/i82801gx/i82801gx_lpc.c
===================================================================
--- cbv2.orig/src/southbridge/intel/i82801gx/i82801gx_lpc.c
+++ cbv2/src/southbridge/intel/i82801gx/i82801gx_lpc.c
@@ -419,12 +419,21 @@ static void i82801gx_lpc_read_resources(
 
 	/* Add an extra subtractive resource for both memory and I/O. */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->flags =
-	    IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->flags =
-	    IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
 static void i82801gx_lpc_enable_resources(device_t dev)
Index: cbv2/src/southbridge/nvidia/ck804/ck804_lpc.c
===================================================================
--- cbv2.orig/src/southbridge/nvidia/ck804/ck804_lpc.c
+++ cbv2/src/southbridge/nvidia/ck804/ck804_lpc.c
@@ -275,12 +275,21 @@ static void ck804_lpc_read_resources(dev
 
 	/* Add an extra subtractive resource for both memory and I/O. */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->flags =
-	    IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->flags =
-	    IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
 /**
Index: cbv2/src/southbridge/nvidia/mcp55/mcp55_lpc.c
===================================================================
--- cbv2.orig/src/southbridge/nvidia/mcp55/mcp55_lpc.c
+++ cbv2/src/southbridge/nvidia/mcp55/mcp55_lpc.c
@@ -250,16 +250,27 @@ static void mcp55_lpc_read_resources(dev
 {
 	struct resource *res;
 
-	/* Get the normal pci resources of this device */
-	pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP
+	/* Get the normal PCI resources of this device. */
+	/* We got one for APIC, or one more for TRAP. */
+	pci_dev_read_resources(dev);
 
-	/* Add an extra subtractive resource for both memory and I/O */
+	/* Add an extra subtractive resource for both memory and I/O. */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
 /**
@@ -267,7 +278,7 @@ static void mcp55_lpc_read_resources(dev
  *
  * @param dev the device whos children's resources are to be enabled
  *
- * This function is call by the global enable_resources() indirectly via the
+ * This function is called by the global enable_resources() indirectly via the
  * device_operation::enable_resources() method of devices.
  *
  * Indirect mutual recursion:
Index: cbv2/src/northbridge/amd/amdk8/misc_control.c
===================================================================
--- cbv2.orig/src/northbridge/amd/amdk8/misc_control.c
+++ cbv2/src/northbridge/amd/amdk8/misc_control.c
@@ -53,7 +53,7 @@ static void mcf3_read_resources(device_t
 	if (iommu) {
 		/* Add a Gart apeture resource */
 		resource = new_resource(dev, 0x94);
-		resource->size = iommu?AGP_APERTURE_SIZE:1;
+		resource->size = AGP_APERTURE_SIZE;
 		resource->align = log2(resource->size);
 		resource->gran  = log2(resource->size);
 		resource->limit = 0xffffffff; /* 4G */
Index: cbv2/src/include/device/resource.h
===================================================================
--- cbv2.orig/src/include/device/resource.h
+++ cbv2/src/include/device/resource.h
@@ -74,10 +74,14 @@ struct resource {
 	/* Alignment must be >= the granularity of the resource */
 };
 
-/* Macros to generate index values for subtractive resources */
+/* Macros to generate index values for resources */
 #define IOINDEX_SUBTRACTIVE(IDX,LINK) (0x10000000 + ((IDX) << 8) + LINK)
 #define IOINDEX_SUBTRACTIVE_LINK(IDX) (IDX & 0xff)
 
+#define IOINDEX(IDX,LINK) (((LINK) << 24) + IDX)
+#define IOINDEX_LINK(IDX) (( IDX & 0x7000000) >> 24)
+#define IOINDEX_IDX(IDX) (IDX & 0xffffff)
+
 /* Generic resource helper functions */
 struct device;
 struct bus;
Index: cbv2/src/southbridge/nvidia/ck804/ck804_pci.c
===================================================================
--- cbv2.orig/src/southbridge/nvidia/ck804/ck804_pci.c
+++ cbv2/src/southbridge/nvidia/ck804/ck804_pci.c
@@ -5,6 +5,7 @@
 
 #include <console/console.h>
 #include <device/device.h>
+#include <device/resource.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
@@ -13,10 +14,8 @@
 static void pci_init(struct device *dev)
 {
 	uint32_t dword;
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
 	device_t pci_domain_dev;
-	struct resource *mem1, *mem2;
-#endif
+	struct resource *mem, *pref;
 
 	dword = pci_read_config32(dev, 0x04);
 	dword |= (1 << 8);	/* System error enable */
@@ -36,7 +35,6 @@ static void pci_init(struct device *dev)
 	pci_write_config32(dev, 0x4c, dword);
 #endif
 
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
 	pci_domain_dev = dev->bus->dev;
 	while (pci_domain_dev) {
 		if (pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN)
@@ -47,21 +45,19 @@ static void pci_init(struct device *dev)
 	if (!pci_domain_dev)
 		return;		/* Impossible */
 
-	mem1 = find_resource(pci_domain_dev, 1);	// prefmem, it could be 64bit
-	mem2 = find_resource(pci_domain_dev, 2);	// mem
-	if (mem1->base > mem2->base) {
-		dword = mem2->base & (0xffff0000UL);
-		printk_debug("PCI DOMAIN mem2 base = 0x%010Lx\n", mem2->base);
+	pref = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(2,0));
+	mem = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(1,0));
+
+	if (!mem)
+		return;		/* Impossible */
+
+	if (!pref || pref->base > mem->base) {
+		dword = mem->base & (0xffff0000UL);
+		printk_debug("PCI DOMAIN mem base = 0x%010Lx\n", mem->base);
 	} else {
-		dword = mem1->base & (0xffff0000UL);
-		printk_debug("PCI DOMAIN mem1 (prefmem) base = 0x%010Lx\n",
-			     mem1->base);
+		dword = pref->base & (0xffff0000UL);
+		printk_debug("PCI DOMAIN pref base = 0x%010Lx\n", pref->base);
 	}
-#else
-	dword = dev_root.resource[1].base & (0xffff0000UL);
-	printk_debug("dev_root mem base = 0x%010Lx\n",
-		     dev_root.resource[1].base);
-#endif
 
 	printk_debug("[0x50] <-- 0x%08x\n", dword);
 	pci_write_config32(dev, 0x50, dword);	/* TOM */
Index: cbv2/src/southbridge/nvidia/mcp55/mcp55_pci.c
===================================================================
--- cbv2.orig/src/southbridge/nvidia/mcp55/mcp55_pci.c
+++ cbv2/src/southbridge/nvidia/mcp55/mcp55_pci.c
@@ -23,6 +23,7 @@
 
 #include <console/console.h>
 #include <device/device.h>
+#include <device/resource.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
@@ -33,10 +34,8 @@ static void pci_init(struct device *dev)
 
 	uint32_t dword;
 	uint16_t word;
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
 	device_t pci_domain_dev;
-	struct resource *mem1, *mem2;
-#endif
+	struct resource *mem, *pref;
 
 	/* System error enable */
 	dword = pci_read_config32(dev, 0x04);
@@ -58,30 +57,32 @@ static void pci_init(struct device *dev)
 	pci_write_config32(dev, 0x4c, dword);
 #endif
 
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
 	pci_domain_dev = dev->bus->dev;
-	while(pci_domain_dev) {
-		if(pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN) break;
+	while (pci_domain_dev) {
+		if (pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN)
+			break;
 		pci_domain_dev = pci_domain_dev->bus->dev;
 	}
 
-	if(!pci_domain_dev) return; // impossiable
-	mem1 = find_resource(pci_domain_dev, 1); // prefmem, it could be 64bit
-	mem2 = find_resource(pci_domain_dev, 2); // mem
-	if(mem1->base > mem2->base) {
-		dword = mem2->base  & (0xffff0000UL);
-		printk_debug("PCI DOMAIN mem2 base = 0x%010Lx\n", mem2->base);
+	if (!pci_domain_dev)
+		return;		/* Impossible */
+
+	pref = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(2,0));
+	mem = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(1,0));
+
+	if (!mem)
+		return;		/* Impossible */
+
+	if (!pref || pref->base > mem->base) {
+		dword = mem->base & (0xffff0000UL);
+		printk_debug("PCI DOMAIN mem base = 0x%010Lx\n", mem->base);
 	} else {
-		dword = mem1->base  & (0xffff0000UL);
-		printk_debug("PCI DOMAIN mem1 (prefmem) base = 0x%010Lx\n", mem1->base);
+		dword = pref->base & (0xffff0000UL);
+		printk_debug("PCI DOMAIN pref base = 0x%010Lx\n", pref->base);
 	}
-#else
-	dword = dev_root.resource[1].base & (0xffff0000UL);
-	printk_debug("dev_root mem base = 0x%010Lx\n", dev_root.resource[1].base);
-#endif
-	printk_debug("[0x50] <-- 0x%08x\n", dword);
-	pci_write_config32(dev, 0x50, dword); //TOM
 
+	printk_debug("[0x50] <-- 0x%08x\n", dword);
+	pci_write_config32(dev, 0x50, dword);	/* TOM */
 }
 
 static struct pci_operations lops_pci = {
