Not sure about other ways for getting post code. May be EC can provide that. Not sure to what extent DbC can help.

For now as Angel pointed out, along with SPD, dq_map, dqs_map, Rcomp_resistor, Rcomp_Target.

I guess you have a CNL platform. Then for LPDDR4 memory, you can use

dq_map from

https://github.com/coreboot/coreboot/blob/master/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c#L8

rcomp_resistor(Please verify in schematic the resistor value for DRAM_RCOMP[0..2]. I guess they should be 100 ohm resistor)

https://github.com/coreboot/coreboot/blob/master/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c#L56

rcomp_target(for LPDDR4)

https://github.com/coreboot/coreboot/blob/master/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c#L63

For DQS_map, you need to first find the connection between SDRAM DQS pin to CPU DQS pin map. Can you check that in schematic ?

With this setting + correct SPD, FSPM should run successfully.

On Fri, Nov 20, 2020 at 4:01 PM Andy Pont <andy.pont@sdcsystems.com> wrote:

Naresh wrote...

To understand the exact failure cause in FSPM, you need to get post code from FSP. What is printed in log is Coreboot post code only.
Is it possible to get the post code from FSPM without a hardware POST code indicator?

The hardware I am using only has an M.2 slot (used for an SSD) and it is the only format that I don’t have a POST code indicator board for!

-Andy.