Hello Vincenzo,
It is theoretically possible. But, there are few modes and few situations (I envision) where this could be achieved, IMHO.
HW requirements: you should make your flash to be in the socket (not just soldered on the mobo). Then flash's VCC pin (1.8V or 3.3V) should be connected to mobo's power supply rail via switch, so, after bringing platform to OS, you can switch flash's power OFF.
Also, this: Or maybe Coreboot should be programmed to switch electrically off the chip before tear out it from its case? is a very good test to be performed! My take on this, the only requirement Coreboot should have is as payload to have Tiano Core. Other payloads will not work (since all setup will behave as legacy BIOS)... I'll bet on it as heuristics theory (NOT as theorem oriented one).
SW requirements:
[1] ONLY UEFI, legacy BIOS will not work at all;
[2] While in CMOS, you should set CPU power states to be ONLY: C0 and C1 states, other states are NOT allowed. In other words, Power Management is OFF (PC is always ON).
I have no idea how ACPI tables will work, but they should be copied into main memory controlled by the OS, as well as UEFI's VBT (Video BIOS table). Also not sure about UEFI's Run Time Services (do they use parts of UEFI or not). But I'll find out (CIA always finds the right info, despite they after all alter the truth/real facts as a half-hacked reality, to serve in their own straight/direct interests). ;-)
This theme is very worth exploring (in depth).
Please, stay tuned, it'll take a time!
Zoran Stojsavljevic