0000:00:00.0 0500: 10de:0369 (rev a1)
	Subsystem: 1458:2b80
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0
	Capabilities: <available only to root>
00: de 10 69 03 06 01 b0 00 a1 00 00 05 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 58 14 80 2b
30: 00 00 00 00 44 00 00 00 00 00 00 00 00 00 00 00

0000:00:01.0 0601: 10de:0360 (rev a2)
	Subsystem: 1458:2b80
	Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0
	Region 1: Memory at f6144000 (32-bit, non-prefetchable) [size=4K]
00: de 10 60 03 0f 00 a0 00 a2 00 01 06 00 00 80 00
10: 00 00 00 00 00 40 14 f6 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 58 14 80 2b
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

0000:00:01.1 0c05: 10de:0368 (rev a2)
	Subsystem: 1458:2b80
	Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Interrupt: pin A routed to IRQ 10
	Region 0: I/O ports at 2c00 [size=64]
	Region 4: I/O ports at 2c40 [size=64]
	Region 5: I/O ports at 2c80 [size=64]
	Capabilities: <available only to root>
00: de 10 68 03 01 00 b0 00 a2 00 05 0c 00 00 80 00
10: 01 2c 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 41 2c 00 00 81 2c 00 00 00 00 00 00 58 14 80 2b
30: 00 00 00 00 44 00 00 00 00 00 00 00 00 01 00 00

0000:00:01.2 0500: 10de:036a (rev a2)
	Subsystem: 1458:2b80
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
00: de 10 6a 03 00 04 a0 00 a2 00 00 05 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 58 14 80 2b
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

0000:00:01.3 0b40: 10de:036b (rev a2)
	Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Interrupt: pin B routed to IRQ 10
	Region 0: Memory at f6100000 (32-bit, non-prefetchable) [size=256K]
00: de 10 6b 03 02 00 a0 00 a2 00 40 0b 00 00 80 00
10: 00 00 10 f6 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 02 03 01

0000:00:02.0 0c03: 10de:036c (rev a1) (prog-if 10)
	Subsystem: 1458:2b80
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0 (750ns min, 250ns max)
	Interrupt: pin A routed to IRQ 22
	Region 0: Memory at f6145000 (32-bit, non-prefetchable) [size=4K]
	Capabilities: <available only to root>
00: de 10 6c 03 06 00 b0 00 a1 10 03 0c 00 00 80 00
10: 00 50 14 f6 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 58 14 80 2b
30: 00 00 00 00 44 00 00 00 00 00 00 00 00 01 03 01

0000:00:02.1 0c03: 10de:036d (rev a2) (prog-if 20)
	Subsystem: 1458:2b80
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0 (750ns min, 250ns max)
	Interrupt: pin B routed to IRQ 23
	Region 0: Memory at f614a000 (32-bit, non-prefetchable) [size=256]
	Capabilities: <available only to root>
00: de 10 6d 03 06 00 b0 00 a2 20 03 0c 00 00 80 00
10: 00 a0 14 f6 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 58 14 80 2b
30: 00 00 00 00 44 00 00 00 00 00 00 00 00 02 03 01

0000:00:04.0 0101: 10de:036e (rev a1) (prog-if 8a [Master SecP PriP])
	Subsystem: 1458:2b80
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0 (750ns min, 250ns max)
	Region 0: [virtual] Memory at 000001f0 (32-bit, non-prefetchable) [disabled] [size=8]
	Region 1: [virtual] Memory at 000003f0 (type 3, non-prefetchable) [disabled] [size=1]
	Region 2: [virtual] Memory at 00000170 (32-bit, non-prefetchable) [disabled] [size=8]
	Region 3: [virtual] Memory at 00000370 (type 3, non-prefetchable) [disabled] [size=1]
	Region 4: I/O ports at 2cc0 [size=16]
	Capabilities: <available only to root>
00: de 10 6e 03 05 00 b0 00 a1 8a 01 01 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: c1 2c 00 00 00 00 00 00 00 00 00 00 58 14 80 2b
30: 00 00 00 00 44 00 00 00 00 00 00 00 00 00 03 01

0000:00:05.0 0101: 10de:037f (rev a2) (prog-if 85 [Master SecO PriO])
	Subsystem: 1458:2b80
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0 (750ns min, 250ns max)
	Interrupt: pin A routed to IRQ 20
	Region 0: I/O ports at 3000 [size=8]
	Region 1: I/O ports at 3070 [size=4]
	Region 2: I/O ports at 3010 [size=8]
	Region 3: I/O ports at 3080 [size=4]
	Region 4: I/O ports at 2cd0 [size=16]
	Region 5: Memory at f6146000 (32-bit, non-prefetchable) [size=4K]
	Capabilities: <available only to root>
00: de 10 7f 03 07 00 b0 00 a2 85 01 01 00 00 80 00
10: 01 30 00 00 71 30 00 00 11 30 00 00 81 30 00 00
20: d1 2c 00 00 00 60 14 f6 00 00 00 00 58 14 80 2b
30: 00 00 00 00 44 00 00 00 00 00 00 00 00 01 03 01

0000:00:05.1 0101: 10de:037f (rev a2) (prog-if 85 [Master SecO PriO])
	Subsystem: 1458:2b80
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0 (750ns min, 250ns max)
	Interrupt: pin B routed to IRQ 23
	Region 0: I/O ports at 3020 [size=8]
	Region 1: I/O ports at 3090 [size=4]
	Region 2: I/O ports at 3030 [size=8]
	Region 3: I/O ports at 30a0 [size=4]
	Region 4: I/O ports at 2ce0 [size=16]
	Region 5: Memory at f6147000 (32-bit, non-prefetchable) [size=4K]
	Capabilities: <available only to root>
00: de 10 7f 03 07 00 b0 00 a2 85 01 01 00 00 80 00
10: 21 30 00 00 91 30 00 00 31 30 00 00 a1 30 00 00
20: e1 2c 00 00 00 70 14 f6 00 00 00 00 58 14 80 2b
30: 00 00 00 00 44 00 00 00 00 00 00 00 00 02 03 01

0000:00:05.2 0101: 10de:037f (rev a2) (prog-if 85 [Master SecO PriO])
	Subsystem: 1458:2b80
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0 (750ns min, 250ns max)
	Interrupt: pin C routed to IRQ 21
	Region 0: I/O ports at 3040 [size=8]
	Region 1: I/O ports at 30b0 [size=4]
	Region 2: I/O ports at 3050 [size=8]
	Region 3: I/O ports at 30c0 [size=4]
	Region 4: I/O ports at 2cf0 [size=16]
	Region 5: Memory at f6148000 (32-bit, non-prefetchable) [size=4K]
	Capabilities: <available only to root>
00: de 10 7f 03 07 00 b0 00 a2 85 01 01 00 00 80 00
10: 41 30 00 00 b1 30 00 00 51 30 00 00 c1 30 00 00
20: f1 2c 00 00 00 80 14 f6 00 00 00 00 58 14 80 2b
30: 00 00 00 00 44 00 00 00 00 00 00 00 00 03 03 01

0000:00:06.0 0604: 10de:0370 (rev a2)
	Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0
	Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
	I/O behind bridge: 0000f000-00000fff
	Memory behind bridge: fff00000-000fffff
	Prefetchable memory behind bridge: fff00000-000fffff
	BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
	Capabilities: <available only to root>
00: de 10 70 03 04 01 b0 00 a2 00 04 06 00 00 81 00
10: 00 00 00 00 00 00 00 00 00 01 01 00 f0 00 80 02
20: f0 ff 00 00 f0 ff 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 b8 00 00 00 00 00 00 00 00 00 03 0a

0000:00:06.1 0403: 10de:0371 (rev a2)
	Subsystem: 1458:2b80
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0 (500ns min, 1250ns max)
	Interrupt: pin B routed to IRQ 23
	Region 0: Memory at f6140000 (32-bit, non-prefetchable) [size=16K]
	Capabilities: <available only to root>
00: de 10 71 03 06 00 b0 00 a2 00 03 04 00 00 80 00
10: 00 00 14 f6 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 58 14 80 2b
30: 00 00 00 00 44 00 00 00 00 00 00 00 00 02 02 05

0000:00:08.0 0680: 10de:0373 (rev a2)
	Subsystem: 1458:2b80
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0 (250ns min, 5000ns max)
	Interrupt: pin A routed to IRQ 22
	Region 0: Memory at f6149000 (32-bit, non-prefetchable) [size=4K]
	Region 1: I/O ports at 3060 [size=8]
	Region 2: Memory at f614b000 (32-bit, non-prefetchable) [size=256]
	Region 3: Memory at f614c000 (32-bit, non-prefetchable) [size=16]
	Capabilities: <available only to root>
00: de 10 73 03 07 04 b0 00 a2 00 80 06 00 00 00 00
10: 00 90 14 f6 61 30 00 00 00 b0 14 f6 00 c0 14 f6
20: 00 00 00 00 00 00 00 00 00 00 00 00 58 14 80 2b
30: 00 00 00 00 44 00 00 00 00 00 00 00 00 01 01 14

0000:00:0a.0 0604: 10de:0376 (rev a2)
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0, Cache Line Size: 0x10 (64 bytes)
	Bus: primary=00, secondary=02, subordinate=02, sec-latency=0
	I/O behind bridge: 00001000-00001fff
	Memory behind bridge: f4000000-f60fffff
	Prefetchable memory behind bridge: 00000000e0000000-00000000eff00000
	BridgeCtl: Parity+ SERR+ NoISA- VGA+ MAbort- >Reset- FastB2B-
	Capabilities: <available only to root>
00: de 10 76 03 47 05 10 00 a2 00 04 06 10 00 01 00
10: 00 00 00 00 00 00 00 00 00 02 02 00 11 11 00 00
20: 00 f4 00 f6 01 e0 f1 ef 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 0b 00

0000:00:0b.0 0604: 10de:0374 (rev a2)
	Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0
	Bus: primary=00, secondary=03, subordinate=03, sec-latency=0
	I/O behind bridge: 0000f000-00000fff
	Memory behind bridge: fff00000-000fffff
	Prefetchable memory behind bridge: 00000000fff00000-0000000000000000
	BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
	Capabilities: <available only to root>
00: de 10 74 03 44 05 10 00 a2 00 04 06 00 00 01 00
10: 00 00 00 00 00 00 00 00 00 03 03 00 f1 01 00 00
20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 03 00

0000:00:0c.0 0604: 10de:0374 (rev a2)
	Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0
	Bus: primary=00, secondary=04, subordinate=04, sec-latency=0
	I/O behind bridge: 0000f000-00000fff
	Memory behind bridge: fff00000-000fffff
	Prefetchable memory behind bridge: 00000000fff00000-0000000000000000
	BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
	Capabilities: <available only to root>
00: de 10 74 03 44 05 10 00 a2 00 04 06 00 00 01 00
10: 00 00 00 00 00 00 00 00 00 04 04 00 f1 01 00 00
20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 03 00

0000:00:0d.0 0604: 10de:0378 (rev a2)
	Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0
	Bus: primary=00, secondary=05, subordinate=05, sec-latency=0
	I/O behind bridge: 0000f000-00000fff
	Memory behind bridge: fff00000-000fffff
	Prefetchable memory behind bridge: 00000000fff00000-0000000000000000
	BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
	Capabilities: <available only to root>
00: de 10 78 03 44 05 10 00 a2 00 04 06 00 00 01 00
10: 00 00 00 00 00 00 00 00 00 05 05 00 f1 01 00 00
20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 03 00

0000:00:0e.0 0604: 10de:0375 (rev a2)
	Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0
	Bus: primary=00, secondary=06, subordinate=06, sec-latency=0
	I/O behind bridge: 0000f000-00000fff
	Memory behind bridge: fff00000-000fffff
	Prefetchable memory behind bridge: 00000000fff00000-0000000000000000
	BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
	Capabilities: <available only to root>
00: de 10 75 03 44 05 10 00 a2 00 04 06 00 00 01 00
10: 00 00 00 00 00 00 00 00 00 06 06 00 f1 01 00 00
20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 03 00

0000:00:0f.0 0604: 10de:0377 (rev a2)
	Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0
	Bus: primary=00, secondary=07, subordinate=07, sec-latency=0
	I/O behind bridge: 0000f000-00000fff
	Memory behind bridge: fff00000-000fffff
	Prefetchable memory behind bridge: 00000000fff00000-0000000000000000
	BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
	Capabilities: <available only to root>
00: de 10 77 03 44 05 10 00 a2 00 04 06 00 00 01 00
10: 00 00 00 00 00 00 00 00 00 07 07 00 f1 01 00 00
20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 03 00

0000:00:18.0 0600: 1022:1100
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Capabilities: <available only to root>
00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00

0000:00:18.1 0600: 1022:1101
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

0000:00:18.2 0600: 1022:1102
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
00: 22 10 02 11 00 00 00 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

0000:00:18.3 0600: 1022:1103
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Capabilities: <available only to root>
00: 22 10 03 11 00 00 10 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 f0 00 00 00 00 00 00 00 00 00 00 00

0000:02:00.0 0300: 10de:0392 (rev a1)
	Subsystem: 1682:2221
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0, Cache Line Size: 0x10 (64 bytes)
	Interrupt: pin A routed to IRQ 16
	Region 0: Memory at f4000000 (32-bit, non-prefetchable) [size=16M]
	Region 1: Memory at e0000000 (64-bit, prefetchable) [size=256M]
	Region 3: Memory at f5000000 (64-bit, non-prefetchable) [size=16M]
	Region 5: I/O ports at 1000 [size=128]
	Expansion ROM at f6000000 [disabled] [size=128K]
	Capabilities: <available only to root>
00: de 10 92 03 47 01 10 00 a1 00 00 03 10 00 00 00
10: 00 00 00 f4 0c 00 00 e0 00 00 00 00 04 00 00 f5
20: 00 00 00 00 01 10 00 00 00 00 00 00 82 16 21 22
30: 00 00 00 f6 60 00 00 00 00 00 00 00 00 01 00 00