Dear coreboot community,
I have encountered problem with silicon init on Tiger Lake RVP
platform. I managed to resolve previous issues with memory
initialization and now hitting an error with TCSS init. The FSP
asserts on IOM ready check, which is 0. The configuration has
selected CONFIG_USE_INTEL_FSP_MP_INIT (without MP PPI service).
When the CONFIG_USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI is
selected, then the FSP-S returns smoothly (at least from one of
the phases I guess) and resets after clearing MCEs in coreboot's
CPU init:
CPU: vendor
Intel device 806c0
CPU: family
06, model 8c, stepping 00
Clearing out
pending MCEs
Setting up
local APIC...
apic_id: 0x00
done.
Turbo is
available but hidden
Turbo is
available and visible
CPU #0
initialized
Initializing
CPU #2
Initializing
CPU #6
Initializing
CPU #7
CPU: vendor
Intel device 806c0
CPU: family
06, model 8c, stepping 00
CPU: vendor
Intel device 806c0
CPU: family
06, model 8c, stepping 00
Clearing out
pending MCEs
Cl (tutaj
następuje reset)
Any ideas what may cause these issues? When I clean this up, I
will upstream the DDR4 variant of TGL UP3 RVP.
-- Michał Żygowski Firmware Engineer https://3mdeb.com | @3mdeb_com