[coreboot] Patch merged into coreboot/master: 9114cfc Fixes several issues with amd k8 SSDT P-state generation

the following patch was just integrated into master:
commit 9114cfc332720cedb487c140913a45cb65b9e5e1
Author: Oskar Enoksson 
Date:   Thu Oct 6 18:43:43 2011 +0200

Fixes several issues with amd k8 SSDT P-state generation

First issue fixed:
    For multi-socket CPU the current implementation emitted
    Processor objects for cores in the first CPU only. This
    commit fixes the bug by really emitting one Processor
    object for each core. However, the unlikely case of mixed
    CPU models is still not handled correctly.

Second issue fixed:
    One loop was wrong in case a processor in the table declares
    no P-states at all. The rewritten loop is safe. Some possibly
    dangerous array lengths were also fixed.

Third issue: on MP-boards the recommended ramp-voltage (RVO) is 0mV
    according to the BKDG. The current implementation always set it
    to 25mV. This commit selects 0 or 25mV depending on CONFIG_MAX_PHYSICAL_CPUS.

Fourth issue: If a processor without PowerNow! support was inserted in a
    system with coreboot configured with SET_FIDVID then the boot process hanged
    mysteriously and very early. Apparently because init_fidvid_ap tampers with
    non-existing registers. This commit fixes the bug by bailing out
    from init_fidvid_ap if PowerNow! capability is missing.

Signed-off-by: Oskar Enoksson 
    Change-Id: I61f6e2210b84ccba33a36c5efc866447b7134417

See http://review.coreboot.org/239 for details.

-gerrit