Re: [coreboot] coreboot Digest, Vol 68, Issue 109

[Mark Beihoffer]

Contempt? Whatever.

Mark Beihoffer
Dragonfly Networks
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On Wed, Oct 20, 2010 at 12:31 AM,  wrote:
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> Today's Topics:
> [commit] r5976 - trunk/src/cpu/amd/car (repository service)
> Re: [PATCH] AMD F10h: set MMCONF bus count        according
> toconfigured value (Peter Stuge)
> Re: [PATCH] fix cpu ht speed display in rs780_gfx.c (Liu Tao)
> Extension to inteltool and a request (Keith Hui)
> Re: coreboot Digest, Vol 68, Issue 108 (Mark Beihoffer)
>
> Message: 1
> Date: Tue, 19 Oct 2010 23:08:12 +0200
> From: repository service 
> To: [e-mail]
> Subject: [coreboot] [commit] r5976 - trunk/src/cpu/amd/car
> Message-ID: 
> Content-Type: text/plain; charset=UTF-8
>
> Author: sduplichan
> Date: Tue Oct 19 23:08:11 2010
> New Revision: 5976
> URL: https://tracker.coreboot.org/trac/coreboot/changeset/5976
>
> Log:
> For AMD family 10h processors, msr c0010058 is always programmed
> for 256 buses, even if fewer are configured. This patch lets msr
> c0010058 programming use the configured bus count,
> CONFIG_MMCONF_BUS_NUMBER.
>
> Signed-off-by: Scott Duplichan 
> Acked-by: Myles Watson
>
> Modified:
>   trunk/src/cpu/amd/car/cache_as_ram.inc
>
> Modified: trunk/src/cpu/amd/car/cache_as_ram.inc
>
> ==============================================================================
> --- trunk/src/cpu/amd/car/cache_as_ram.inc      Tue Oct 19 17:25:06 2010
>      (r5975)
> +++ trunk/src/cpu/amd/car/cache_as_ram.inc      Tue Oct 19 23:08:11 2010
>      (r5976)
> @@ -132,14 +132,34 @@
>        wrmsr
>
> #if CONFIG_MMCONF_SUPPORT
>   /* Set MMIO config space BAR. */
>   movl    $MSR_MCFG_BASE, %ecx
>   rdmsr
>   andl    $(~(0xfff00000 | (0xf << 2))), %eax
>   orl     $((CONFIG_MMCONF_BASE_ADDRESS & 0xfff00000)), %eax
>   orl     $((8 << 2) | (1 << 0)), %eax
>   andl    $(~(0x0000ffff)), %edx
>   orl     $(CONFIG_MMCONF_BASE_ADDRESS >> 32), %edx
> #if (CONFIG_MMCONF_BASE_ADDRESS > 0xFFFFFFFF)
> #error "MMCONF_BASE_ADDRESS too big"
> #elif (CONFIG_MMCONF_BASE_ADDRESS & 0xFFFFF)
> #error "MMCONF_BASE_ADDRESS not 1MB aligned"
> #endif
>   movl    $0, %edx
>   movl    $((CONFIG_MMCONF_BASE_ADDRESS) | (1 << 0)), %eax
> #if (CONFIG_MMCONF_BUS_NUMBER == 1)
> #elif (CONFIG_MMCONF_BUS_NUMBER == 2)
>   orl     $(1 << 2), %eax
> #elif (CONFIG_MMCONF_BUS_NUMBER == 4)
>   orl     $(2 << 2), %eax
> #elif (CONFIG_MMCONF_BUS_NUMBER == 8)
>   orl     $(3 << 2), %eax
> #elif (CONFIG_MMCONF_BUS_NUMBER == 16)
>   orl     $(4 << 2), %eax
> #elif (CONFIG_MMCONF_BUS_NUMBER == 32)
>   orl     $(5 << 2), %eax
> #elif (CONFIG_MMCONF_BUS_NUMBER == 64)
>   orl     $(6 << 2), %eax
> #elif (CONFIG_MMCONF_BUS_NUMBER == 128)
>   orl     $(7 << 2), %eax
> #elif (CONFIG_MMCONF_BUS_NUMBER == 256)
>   orl     $(8 << 2), %eax
> #else
>   #error "bad MMCONF_BUS_NUMBER value"
> #endif
>   movl    $(0xc0010058), %ecx
>  wrmsr
>
> #endif
>
> Message: 2
> Date: Wed, 20 Oct 2010 00:17:31 +0200
> From: Peter Stuge 
> To: [e-mail]
> Subject: Re: [coreboot] [PATCH] AMD F10h: set MMCONF bus count
>        according       toconfigured value
> Message-ID: 
> Content-Type: text/plain; charset=us-ascii
>
> Scott Duplichan wrote:
> > back to inlined code with the extra error checks:
> >
> > Signed-off-by: Scott Duplichan <[e-mail]
>
> Acked-by: Peter Stuge
>
> Message: 3
> Date: Wed, 20 Oct 2010 09:13:17 +0800
> From: Liu Tao 
> To: Uwe Hermann 
> Cc: Myles Watson , [e-mail]
> Subject: Re: [coreboot] [PATCH] fix cpu ht speed display in
>        rs780_gfx.c
> Message-ID:
>        
> Content-Type: text/plain; charset=ISO-8859-1
>
> The name of sblink seems more clear, but for most cases, the name of sblk
> only appears in K8/Fam10 codes, so it didn't cause much confusions.
>
> A more consistent way to get HT southbridge link in sb700 chipset is to
> include
> the <cpu/amd/amdk8_sysconf.h> or <cpu/amd/amdfam10_sysconf.h>, and
> use global variable sysconf.sblk. For now, fam10 codes set sysconf.sblk
> during
> early romstage, but K8 codes didn't. Maybe we should fix K8 coeds to set
> sysconf.sblk earlyer, and use it in later device drivers.
>
> On Mon, Oct 18, 2010 at 6:01 AM, Uwe Hermann  wrote:
> > On Sun, Oct 17, 2010 at 11:39:46PM +0200, Uwe Hermann wrote:
> > > ?- Renamed sblk to sblink (the name of the register bits as per
> > > ? ?BIOS + Kernel Developer's Guide for AMD Athlon 64 & AMD Opteron
>
> Processors,
> > > ? ?chapter 3.3.8.
> >
> > Hm, I noticed that the K8/Fam10h code uses "sblk" as function/variable
>
> name
> > pretty consistently, but I can't seem to find that spelling in any of
> > the AMD manuals. Should we rename "sblk" to "sblink" in the whole tree?
>
> Message: 4
> Date: Wed, 20 Oct 2010 00:57:21 -0400
> From: Keith Hui 
> To: [e-mail]
> Subject: [coreboot] Extension to inteltool and a request
> Message-ID:
>        
> Content-Type: text/plain; charset="iso-8859-1"
>
> Hi all,
>
> This patch extends inteltool's MSR dumping to all Slot 1 Intel CPUs.
>
> I made this an attempt to gather some information for an updated L2
> patch, so I have a request to all,
>
> Can anyone with a Slot 1 CPU apply the attached patch, compile
> inteltool, and post the output together with some information on your
> CPU?
>
> Thanks.
>
> Patch is Signed-off-by: Keith Hui 
> if it's useful for the future and worth committing.