[1m[NOTE ]  coreboot-v1.1-dirty Mon Mar 27 12:56:05 UTC 2023 x86_32 bootblock starting (log level: 7)...[0m
[0m[DEBUG]  CPU: Intel(R) Core(TM) i7-9850HL CPU @ 1.90GHz[0m
[0m[DEBUG]  CPU: ID 906ea, Coffeelake U0 (6+2), ucode: 000000ef[0m
[0m[DEBUG]  CPU: AES supported, TXT supported, VT supported[0m
[0m[DEBUG]  MCH: device id 3ec4 (rev 07) is Coffeelake-H[0m
[0m[DEBUG]  PCH: device id a30c (rev 10) is Cannonlake-H QM370[0m
[0m[DEBUG]  IGD: device id 3e9b (rev 00) is Coffeelake-H GT2[0m
[0m[INFO ]  PMC: Using default GPE route.[0m
[0m[DEBUG]  misccfg_mask:fff000ff misccfg_value:43200[0m
[0m[DEBUG]  FMAP: Found "FLASH" version 1.1 at 0x50000.[0m
[0m[DEBUG]  FMAP: base = 0xff400000 size = 0xc00000 #areas = 5[0m
[0m[DEBUG]  FMAP: area COREBOOT found @ 50200 (12254720 bytes)[0m
[0m[INFO ]  CBFS: mcache @0xfef21400 built for 15 files, used 0x34c of 0x4000 bytes[0m
[0m[INFO ]  CBFS: Found 'fallback/romstage' @0x80 size 0xaac0 in mcache @0xfef2142c[0m
[0m[DEBUG]  BS: bootblock times (exec / console): total (unknown) / 97 ms[0m
[0m
[0m
[1m[NOTE ]  coreboot-v1.1-dirty Mon Mar 27 12:56:05 UTC 2023 x86_32 romstage starting (log level: 7)...[0m
[0m[DEBUG]  pm1_sts: 0000 pm1_en: 0000 pm1_cnt: 00000000[0m
[0m[DEBUG]  gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000[0m
[0m[DEBUG]  gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000[0m
[0m[DEBUG]  gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000[0m
[0m[DEBUG]  gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000[0m
[0m[DEBUG]  TCO_STS:   0000 0000[0m
[0m[DEBUG]  GEN_PMCON: a0054000 00000204[0m
[0m[DEBUG]  GBLRST_CAUSE: 00000000 00000000[0m
[0m[DEBUG]  HPR_CAUSE0: 00000000[0m
[0m[DEBUG]  prev_sleep_state 5[0m
[0m[DEBUG]  Before FSP Memory Init [0m
[0m[DEBUG]  FMAP: area COREBOOT found @ 50200 (12254720 bytes)[0m
[0m[INFO ]  CBFS: Found 'fspm.bin' @0x8fdc0 size 0x88000 in mcache @0xfef21624[0m
[0m[DEBUG]  FMAP: area RW_MRC_CACHE found @ 0 (65536 bytes)[0m
[1m[NOTE ]  MRC: no data in 'RW_MRC_CACHE'[0m
[0m[DEBUG]  cannonlake_memcfg_init Called! [0m
[0m[DEBUG]  SPD INDEX = 0[0m
[0m[INFO ]  CBFS: Found 'spd.bin' @0x8f040 size 0x200 in mcache @0xfef21604[0m
[0m[DEBUG]  meminit_cbfs_spd_index spd_data_ptr not null [0m
[0m[INFO ]  SPD: module type is DDR4[0m
[0m[INFO ]  SPD: banks 16, ranks 2, rows 16, columns 10, density 8192 Mb[0m
[0m[INFO ]  SPD: device width 8 bits, bus width 64 bits[0m
[0m[INFO ]  SPD: module size is 16384 MB (per channel)[0m
[0m[INFO ]  memory slot: 0 configuration done.[0m
[0m[INFO ]  memory slot: 2 configuration done.[0m
[0m[DEBUG]  CBMEM:[0m
[0m[DEBUG]  IMD: root @ 0x89fff000 254 entries.[0m
[0m[DEBUG]  IMD: root @ 0x89ffec00 62 entries.[0m
[0m[DEBUG]  External stage cache:[0m
[0m[DEBUG]  IMD: root @ 0x8abff000 254 entries.[0m
[0m[DEBUG]  IMD: root @ 0x8abfec00 62 entries.[0m
[0m[DEBUG]  2 DIMMs found[0m
[0m[DEBUG]  SMM Memory Map[0m
[0m[DEBUG]  SMRAM       : 0x8a000000 0x1000000[0m
[0m[DEBUG]   Subregion 0: 0x8a000000 0xa00000[0m
[0m[DEBUG]   Subregion 1: 0x8aa00000 0x200000[0m
[0m[DEBUG]   Subregion 2: 0x8ac00000 0x400000[0m
[0m[DEBUG]  top_of_ram = 0x8a000000[0m
[0m[DEBUG]  Normal boot[0m
[0m[INFO ]  CBFS: Found 'fallback/postcar' @0x143a40 size 0x5a44 in mcache @0xfef21698[0m
[0m[DEBUG]  Loading module at 0x89cdf000 with entry 0x89cdf031. filesize: 0x56a0 memsize: 0xb9d8[0m
[0m[DEBUG]  Processing 217 relocs. Offset value of 0x87cdf000[0m
[0m[DEBUG]  BS: romstage times (exec / console): total (unknown) / 233 ms[0m
[0m
[0m
[1m[NOTE ]  coreboot-v1.1-dirty Mon Mar 27 12:56:05 UTC 2023 x86_32 postcar starting (log level: 7)...[0m
[0m[DEBUG]  Normal boot[0m
[0m[DEBUG]  FMAP: area COREBOOT found @ 50200 (12254720 bytes)[0m
[0m[INFO ]  CBFS: Found 'fallback/ramstage' @0x71080 size 0x1ad4f in mcache @0x89ced10c[0m
[0m[DEBUG]  Loading module at 0x89c8d000 with entry 0x89c8d000. filesize: 0x37a60 memsize: 0x504d0[0m
[0m[DEBUG]  Processing 3857 relocs. Offset value of 0x85c8d000[0m
[0m[DEBUG]  BS: postcar times (exec / console): total (unknown) / 47 ms[0m
[0m
[0m
[1m[NOTE ]  coreboot-v1.1-dirty Mon Mar 27 12:56:05 UTC 2023 x86_32 ramstage starting (log level: 7)...[0m
[0m[DEBUG]  Normal boot[0m
[0m[DEBUG]  FMAP: area RW_MRC_CACHE found @ 0 (65536 bytes)[0m
[0m[DEBUG]  MRC: Checking cached data update for 'RW_MRC_CACHE'.[0m
[0m[INFO ]  SF: Detected 00 0000 with sector size 0x1000, total 0x2000000[0m
[7m[ERROR]  SF size 0x2000000 does not correspond to CONFIG_ROM_SIZE 0xc00000!![0m
[1m[NOTE ]  MRC: no data in 'RW_MRC_CACHE'[0m
[0m[DEBUG]  MRC: cache data 'RW_MRC_CACHE' needs update.[0m
[0m[DEBUG]  MRC: updated 'RW_MRC_CACHE'.[0m
[0m[DEBUG]  BS: BS_PRE_DEVICE entry times (exec / console): 10 / 44 ms[0m
[0m[DEBUG]  FMAP: area COREBOOT found @ 50200 (12254720 bytes)[0m
[0m[INFO ]  CBFS: Found 'cpu_microcode_blob.bin' @0xabc0 size 0x66400 in mcache @0x89ced0ac[0m
[0m[DEBUG]  microcode: sig=0x906ea pf=0x20 revision=0xef[0m
[0m[DEBUG]  Skip microcode update[0m
[0m[INFO ]  CBFS: Found 'fsps.bin' @0x117e00 size 0x2bbd3 in mcache @0x89ced264[0m
[0m[DEBUG]  Detected 6 core, 12 thread CPU.[0m
[0m[DEBUG]  Setting up SMI for CPU[0m
[0m[DEBUG]  IED base = 0x8ac00000[0m
[0m[DEBUG]  IED size = 0x00400000[0m
[0m[INFO ]  Will perform SMM setup.[0m
[0m[INFO ]  CPU: Intel(R) Core(TM) i7-9850HL CPU @ 1.90GHz.[0m
[0m[INFO ]  LAPIC 0x0 in XAPIC mode.[0m
[0m[DEBUG]  CPU: APIC: 00 enabled[0m
[0m[DEBUG]  CPU: APIC: 01 enabled[0m
[0m[DEBUG]  CPU: APIC: 02 enabled[0m
[0m[DEBUG]  CPU: APIC: 03 enabled[0m
[0m[DEBUG]  CPU: APIC: 04 enabled[0m
[0m[DEBUG]  CPU: APIC: 05 enabled[0m
[0m[DEBUG]  CPU: APIC: 06 enabled[0m
[0m[DEBUG]  CPU: APIC: 07 enabled[0m
[0m[DEBUG]  CPU: APIC: 08 enabled[0m
[0m[DEBUG]  CPU: APIC: 09 enabled[0m
[0m[DEBUG]  CPU: APIC: 0a enabled[0m
[0m[DEBUG]  CPU: APIC: 0b enabled[0m
[0m[DEBUG]  Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178[0m
[0m[DEBUG]  Processing 16 relocs. Offset value of 0x00030000[0m
[0m[DEBUG]  Attempting to start 11 APs[0m
[0m[DEBUG]  Waiting for 10ms after sending INIT.[0m
[0m[DEBUG]  Waiting for SIPI to complete...[0m
[0m[DEBUG]  done.[0m
[0m[INFO ]  LAPIC 0x1 in XAPIC mode.[0m
[0m[DEBUG]  Waiting for SIPI to complete...[0m
[0m[INFO ]  AP: slot 4 apic_id 1, MCU rev: 0x000000ef[0m
[0m[DEBUG]  done.[0m
[0m[INFO ]  LAPIC 0x2 in XAPIC mode.[0m
[0m[INFO ]  LAPIC 0x3 in XAPIC mode.[0m
[0m[INFO ]  AP: slot 5 apic_id 2, MCU rev: 0x000000ef[0m
[0m[INFO ]  AP: slot 1 apic_id 3, MCU rev: 0x000000ef[0m
[0m[INFO ]  LAPIC 0xa in XAPIC mode.[0m
[0m[INFO ]  LAPIC 0xb in XAPIC mode.[0m
[0m[INFO ]  AP: slot 7 apic_id a, MCU rev: 0x000000ef[0m
[0m[INFO ]  AP: slot 3 apic_id b, MCU rev: 0x000000ef[0m
[0m[INFO ]  LAPIC 0x5 in XAPIC mode.[0m
[0m[INFO ]  LAPIC 0x4 in XAPIC mode.[0m
[0m[INFO ]  AP: slot 6 apic_id 5, MCU rev: 0x000000ef[0m
[0m[INFO ]  AP: slot 2 apic_id 4, MCU rev: 0x000000ef[0m
[0m[INFO ]  LAPIC 0x7 in XAPIC mode.[0m
[0m[INFO ]  LAPIC 0x6 in XAPIC mode.[0m
[0m[INFO ]  AP: slot 8 apic_id 7, MCU rev: 0x000000ef[0m
[0m[INFO ]  AP: slot 9 apic_id 6, MCU rev: 0x000000ef[0m
[0m[INFO ]  LAPIC 0x9 in XAPIC mode.[0m
[0m[INFO ]  LAPIC 0x8 in XAPIC mode.[0m
[0m[INFO ]  AP: slot 11 apic_id 9, MCU rev: 0x000000ef[0m
[0m[INFO ]  AP: slot 10 apic_id 8, MCU rev: 0x000000ef[0m
[0m[DEBUG]  Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1f0 memsize: 0x1f0[0m
[0m[DEBUG]  Processing 11 relocs. Offset value of 0x00038000[0m
[0m[DEBUG]  smm_module_setup_stub: stack_top = 0x8a006000[0m
[0m[DEBUG]  smm_module_setup_stub: per cpu stack_size = 0x800[0m
[0m[DEBUG]  smm_module_setup_stub: runtime.start32_offset = 0x4c[0m
[0m[DEBUG]  smm_module_setup_stub: runtime.smm_size = 0x10000[0m
[0m[DEBUG]  SMM Module: stub loaded at 38000. Will call 0x89ca5b2f[0m
[0m[DEBUG]  Installing permanent SMM handler to 0x8a000000[0m
[0m[DEBUG]  FX_SAVE      [0x8a9fe800-0x8aa00000][0m
[0m[DEBUG]  HANDLER      [0x8a9fb000-0x8a9fd840][0m
[0m
[0m[DEBUG]  CPU 0[0m
[0m[DEBUG]    ss0        [0x8a9fac00-0x8a9fb000][0m
[0m[DEBUG]    stub0      [0x8a9f3000-0x8a9f31f0][0m
[0m
[0m[DEBUG]  CPU 1[0m
[0m[DEBUG]    ss1        [0x8a9fa800-0x8a9fac00][0m
[0m[DEBUG]    stub1      [0x8a9f2c00-0x8a9f2df0][0m
[0m
[0m[DEBUG]  CPU 2[0m
[0m[DEBUG]    ss2        [0x8a9fa400-0x8a9fa800][0m
[0m[DEBUG]    stub2      [0x8a9f2800-0x8a9f29f0][0m
[0m
[0m[DEBUG]  CPU 3[0m
[0m[DEBUG]    ss3        [0x8a9fa000-0x8a9fa400][0m
[0m[DEBUG]    stub3      [0x8a9f2400-0x8a9f25f0][0m
[0m
[0m[DEBUG]  CPU 4[0m
[0m[DEBUG]    ss4        [0x8a9f9c00-0x8a9fa000][0m
[0m[DEBUG]    stub4      [0x8a9f2000-0x8a9f21f0][0m
[0m
[0m[DEBUG]  CPU 5[0m
[0m[DEBUG]    ss5        [0x8a9f9800-0x8a9f9c00][0m
[0m[DEBUG]    stub5      [0x8a9f1c00-0x8a9f1df0][0m
[0m
[0m[DEBUG]  CPU 6[0m
[0m[DEBUG]    ss6        [0x8a9f9400-0x8a9f9800][0m
[0m[DEBUG]    stub6      [0x8a9f1800-0x8a9f19f0][0m
[0m
[0m[DEBUG]  CPU 7[0m
[0m[DEBUG]    ss7        [0x8a9f9000-0x8a9f9400][0m
[0m[DEBUG]    stub7      [0x8a9f1400-0x8a9f15f0][0m
[0m
[0m[DEBUG]  CPU 8[0m
[0m[DEBUG]    ss8        [0x8a9f8c00-0x8a9f9000][0m
[0m[DEBUG]    stub8      [0x8a9f1000-0x8a9f11f0][0m
[0m
[0m[DEBUG]  CPU 9[0m
[0m[DEBUG]    ss9        [0x8a9f8800-0x8a9f8c00][0m
[0m[DEBUG]    stub9      [0x8a9f0c00-0x8a9f0df0][0m
[0m
[0m[DEBUG]  CPU 10[0m
[0m[DEBUG]    ss10       [0x8a9f8400-0x8a9f8800][0m
[0m[DEBUG]    stub10     [0x8a9f0800-0x8a9f09f0][0m
[0m
[0m[DEBUG]  CPU 11[0m
[0m[DEBUG]    ss11       [0x8a9f8000-0x8a9f8400][0m
[0m[DEBUG]    stub11     [0x8a9f0400-0x8a9f05f0][0m
[0m
[0m[DEBUG]  stacks       [0x8a000000-0x8a006000][0m
[0m[DEBUG]  Loading module at 0x8a9fb000 with entry 0x8a9fb9ae. filesize: 0x2798 memsize: 0x2840[0m
[0m[DEBUG]  Processing 170 relocs. Offset value of 0x8a9fb000[0m
[0m[DEBUG]  Loading module at 0x8a9f3000 with entry 0x8a9f3000. filesize: 0x1f0 memsize: 0x1f0[0m
[0m[DEBUG]  Processing 11 relocs. Offset value of 0x8a9f3000[0m
[0m[DEBUG]  smm_module_setup_stub: stack_top = 0x8a006000[0m
[0m[DEBUG]  smm_module_setup_stub: per cpu stack_size = 0x800[0m
[0m[DEBUG]  smm_module_setup_stub: runtime.start32_offset = 0x4c[0m
[0m[DEBUG]  smm_module_setup_stub: runtime.smm_size = 0xa00000[0m
[0m[DEBUG]  SMM Module: placing smm entry code at 8a9f2c00,  cpu # 0x1[0m
[0m[DEBUG]  SMM Module: placing smm entry code at 8a9f2800,  cpu # 0x2[0m
[0m[DEBUG]  SMM Module: placing smm entry code at 8a9f2400,  cpu # 0x3[0m
[0m[DEBUG]  SMM Module: placing smm entry code at 8a9f2000,  cpu # 0x4[0m
[0m[DEBUG]  SMM Module: placing smm entry code at 8a9f1c00,  cpu # 0x5[0m
[0m[DEBUG]  SMM Module: placing smm entry code at 8a9f1800,  cpu # 0x6[0m
[0m[DEBUG]  SMM Module: placing smm entry code at 8a9f1400,  cpu # 0x7[0m
[0m[DEBUG]  SMM Module: placing smm entry code at 8a9f1000,  cpu # 0x8[0m
[0m[DEBUG]  SMM Module: placing smm entry code at 8a9f0c00,  cpu # 0x9[0m
[0m[DEBUG]  SMM Module: placing smm entry code at 8a9f0800,  cpu # 0xa[0m
[0m[DEBUG]  SMM Module: placing smm entry code at 8a9f0400,  cpu # 0xb[0m
[0m[DEBUG]  SMM Module: stub loaded at 8a9f3000. Will call 0x8a9fb9ae[0m
[0m[DEBUG]  Clearing SMI status registers[0m
[0m[DEBUG]  SMI_STS: TCO PM1 [0m
[0m[DEBUG]  PM1_STS: TMROF [0m
[0m[DEBUG]  TCO_STS: NEWCENTURY [0m
[0m[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x8a9eb000, cpu = 0[0m
[0m[DEBUG]  In relocation handler: CPU 0[0m
[0m[DEBUG]  New SMBASE=0x8a9eb000 IEDBASE=0x8ac00000[0m
[0m[DEBUG]  Writing SMRR. base = 0x8a000006, mask=0xff000800[0m
[0m[DEBUG]  Relocation complete.[0m
[0m[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x8a9ea000, cpu = 4[0m
[0m[DEBUG]  In relocation handler: CPU 4[0m
[0m[DEBUG]  New SMBASE=0x8a9ea000 IEDBASE=0x8ac00000[0m
[0m[DEBUG]  Relocation complete.[0m
[0m[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x8a9e8c00, cpu = 9[0m
[0m[DEBUG]  In relocation handler: CPU 9[0m
[0m[DEBUG]  New SMBASE=0x8a9e8c00 IEDBASE=0x8ac00000[0m
[0m[DEBUG]  Writing SMRR. base = 0x8a000006, mask=0xff000800[0m
[0m[DEBUG]  Relocation complete.[0m
[0m[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x8a9e9000, cpu = 8[0m
[0m[DEBUG]  In relocation handler: CPU 8[0m
[0m[DEBUG]  New SMBASE=0x8a9e9000 IEDBASE=0x8ac00000[0m
[0m[DEBUG]  Relocation complete.[0m
[0m[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x8a9e9c00, cpu = 5[0m
[0m[DEBUG]  In relocation handler: CPU 5[0m
[0m[DEBUG]  New SMBASE=0x8a9e9c00 IEDBASE=0x8ac00000[0m
[0m[DEBUG]  Writing SMRR. base = 0x8a000006, mask=0xff000800[0m
[0m[DEBUG]  Relocation complete.[0m
[0m[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x8a9eac00, cpu = 1[0m
[0m[DEBUG]  In relocation handler: CPU 1[0m
[0m[DEBUG]  New SMBASE=0x8a9eac00 IEDBASE=0x8ac00000[0m
[0m[DEBUG]  Relocation complete.[0m
[0m[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x8a9e8800, cpu = 10[0m
[0m[DEBUG]  In relocation handler: CPU 10[0m
[0m[DEBUG]  New SMBASE=0x8a9e8800 IEDBASE=0x8ac00000[0m
[0m[DEBUG]  Writing SMRR. base = 0x8a000006, mask=0xff000800[0m
[0m[DEBUG]  Relocation complete.[0m
[0m[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x8a9e8400, cpu = 11[0m
[0m[DEBUG]  In relocation handler: CPU 11[0m
[0m[DEBUG]  New SMBASE=0x8a9e8400 IEDBASE=0x8ac00000[0m
[0m[DEBUG]  Relocation complete.[0m
[0m[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x8a9e9800, cpu = 6[0m
[0m[DEBUG]  In relocation handler: CPU 6[0m
[0m[DEBUG]  New SMBASE=0x8a9e9800 IEDBASE=0x8ac00000[0m
[0m[DEBUG]  Relocation complete.[0m
[0m[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x8a9ea800, cpu = 2[0m
[0m[DEBUG]  In relocation handler: CPU 2[0m
[0m[DEBUG]  New SMBASE=0x8a9ea800 IEDBASE=0x8ac00000[0m
[0m[DEBUG]  Writing SMRR. base = 0x8a000006, mask=0xff000800[0m
[0m[DEBUG]  Relocation complete.[0m
[0m[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x8a9ea400, cpu = 3[0m
[0m[DEBUG]  In relocation handler: CPU 3[0m
[0m[DEBUG]  New SMBASE=0x8a9ea400 IEDBASE=0x8ac00000[0m
[0m[DEBUG]  Relocation complete.[0m
[0m[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x8a9e9400, cpu = 7[0m
[0m[DEBUG]  In relocation handler: CPU 7[0m
[0m[DEBUG]  New SMBASE=0x8a9e9400 IEDBASE=0x8ac00000[0m
[0m[DEBUG]  Writing SMRR. base = 0x8a000006, mask=0xff000800[0m
[0m[DEBUG]  Relocation complete.[0m
[0m[INFO ]  Initializing CPU #0[0m
[0m[DEBUG]  CPU: vendor Intel device 906ea[0m
[0m[DEBUG]  CPU: family 06, model 9e, stepping 0a[0m
[0m[DEBUG]  Clearing out pending MCEs[0m
[0m[DEBUG]  cpu: energy policy set to 6[0m
[0m[INFO ]  Turbo is available but hidden[0m
[0m[INFO ]  Turbo is available and visible[0m
[0m[DEBUG]  VMX status: enabled[0m
[0m[DEBUG]  IA32_FEATURE_CONTROL status: locked[0m
[0m[DEBUG]  Skip microcode update[0m
[0m[INFO ]  CPU #0 initialized[0m
[0m[INFO ]  Initializing CPU #4[0m
[0m[INFO ]  Initializing CPU #1[0m
[0m[INFO ]  Initializing CPU #5[0m
[0m[DEBUG]  CPU: vendor Intel device 906ea[0m
[0m[DEBUG]  CPU: family 06, model 9e, stepping 0a[0m
[0m[DEBUG]  CPU: vendor Intel device 906ea[0m
[0m[DEBUG]  CPU: family 06, model 9e, stepping 0a[0m
[0m[INFO ]  Initializing CPU #10[0m
[0m[INFO ]  Initializing CPU #11[0m
[0m[DEBUG]  CPU: vendor Intel device 906ea[0m
[0m[DEBUG]  CPU: family 06, model 9e, stepping 0a[0m
[0m[INFO ]  Initializing CPU #2[0m
[0m[INFO ]  Initializing CPU #6[0m
[0m[DEBUG]  CPU: vendor Intel device 906ea[0m
[0m[DEBUG]  CPU: family 06, model 9e, stepping 0a[0m
[0m[DEBUG]  CPU: vendor Intel device 906ea[0m
[0m[DEBUG]  CPU: family 06, model 9e, stepping 0a[0m
[0m[DEBUG]  Clearing out pending MCEs[0m
[0m[DEBUG]  Clearing out pending MCEs[0m
[0m[DEBUG]  cpu: energy policy set to 6[0m
[0m[DEBUG]  cpu: energy policy set to 6[0m
[0m[DEBUG]  VMX status: enabled[0m
[0m[DEBUG]  VMX status: enabled[0m
[0m[DEBUG]  IA32_FEATURE_CONTROL status: locked[0m
[0m[DEBUG]  IA32_FEATURE_CONTROL status: locked[0m
[0m[DEBUG]  Skip microcode update[0m
[0m[INFO ]  CPU #2 initialized[0m
[0m[DEBUG]  Skip microcode update[0m
[0m[INFO ]  CPU #6 initialized[0m
[0m[INFO ]  Initializing CPU #3[0m
[0m[INFO ]  Initializing CPU #7[0m
[0m[DEBUG]  CPU: vendor Intel device 906ea[0m
[0m[DEBUG]  CPU: family 06, model 9e, stepping 0a[0m
[0m[DEBUG]  CPU: vendor Intel device 906ea[0m
[0m[DEBUG]  CPU: family 06, model 9e, stepping 0a[0m
[0m[DEBUG]  Clearing out pending MCEs[0m
[0m[DEBUG]  Clearing out pending MCEs[0m
[0m[DEBUG]  cpu: energy policy set to 6[0m
[0m[DEBUG]  cpu: energy policy set to 6[0m
[0m[DEBUG]  VMX status: enabled[0m
[0m[DEBUG]  VMX status: enabled[0m
[0m[DEBUG]  IA32_FEATURE_CONTROL status: locked[0m
[0m[DEBUG]  IA32_FEATURE_CONTROL status: locked[0m
[0m[DEBUG]  Skip microcode update[0m
[0m[INFO ]  CPU #3 initialized[0m
[0m[DEBUG]  Skip microcode update[0m
[0m[INFO ]  CPU #7 initialized[0m
[0m[DEBUG]  CPU: vendor Intel device 906ea[0m
[0m[DEBUG]  CPU: family 06, model 9e, stepping 0a[0m
[0m[DEBUG]  Clearing out pending MCEs[0m
[0m[DEBUG]  Clearing out pending MCEs[0m
[0m[DEBUG]  cpu: energy policy set to 6[0m
[0m[DEBUG]  cpu: energy policy set to 6[0m
[0m[DEBUG]  VMX status: enabled[0m
[0m[DEBUG]  VMX status: enabled[0m
[0m[DEBUG]  IA32_FEATURE_CONTROL status: locked[0m
[0m[DEBUG]  IA32_FEATURE_CONTROL status: locked[0m
[0m[DEBUG]  Skip microcode update[0m
[0m[INFO ]  CPU #10 initialized[0m
[0m[DEBUG]  Skip microcode update[0m
[0m[INFO ]  CPU #11 initialized[0m
[0m[DEBUG]  CPU: vendor Intel device 906ea[0m
[0m[DEBUG]  CPU: family 06, model 9e, stepping 0a[0m
[0m[DEBUG]  Clearing out pending MCEs[0m
[0m[DEBUG]  Clearing out pending MCEs[0m
[0m[DEBUG]  cpu: energy policy set to 6[0m
[0m[DEBUG]  cpu: energy policy set to 6[0m
[0m[DEBUG]  VMX status: enabled[0m
[0m[DEBUG]  VMX status: enabled[0m
[0m[DEBUG]  IA32_FEATURE_CONTROL status: locked[0m
[0m[DEBUG]  IA32_FEATURE_CONTROL status: locked[0m
[0m[DEBUG]  Skip microcode update[0m
[0m[INFO ]  CPU #1 initialized[0m
[0m[DEBUG]  Skip microcode update[0m
[0m[INFO ]  CPU #5 initialized[0m
[0m[INFO ]  Initializing CPU #8[0m
[0m[INFO ]  Initializing CPU #9[0m
[0m[DEBUG]  CPU: vendor Intel device 906ea[0m
[0m[DEBUG]  CPU: family 06, model 9e, stepping 0a[0m
[0m[DEBUG]  CPU: vendor Intel device 906ea[0m
[0m[DEBUG]  CPU: family 06, model 9e, stepping 0a[0m
[0m[DEBUG]  Clearing out pending MCEs[0m
[0m[DEBUG]  Clearing out pending MCEs[0m
[0m[DEBUG]  cpu: energy policy set to 6[0m
[0m[DEBUG]  cpu: energy policy set to 6[0m
[0m[DEBUG]  VMX status: enabled[0m
[0m[DEBUG]  VMX status: enabled[0m
[0m[DEBUG]  IA32_FEATURE_CONTROL status: locked[0m
[0m[DEBUG]  IA32_FEATURE_CONTROL status: locked[0m
[0m[DEBUG]  Skip microcode update[0m
[0m[INFO ]  CPU #8 initialized[0m
[0m[DEBUG]  Skip microcode update[0m
[0m[INFO ]  CPU #9 initialized[0m
[0m[DEBUG]  Clearing out pending MCEs[0m
[0m[DEBUG]  cpu: energy policy set to 6[0m
[0m[DEBUG]  VMX status: enabled[0m
[0m[DEBUG]  IA32_FEATURE_CONTROL status: locked[0m
[0m[DEBUG]  Skip microcode update[0m
[0m[INFO ]  CPU #4 initialized[0m
[0m[INFO ]  bsp_do_flight_plan done after 1289 msecs.[0m
[0m[DEBUG]  CPU: frequency set to 4100 MHz[0m
[0m[DEBUG]  Enabling SMIs.[0m
[0m[DEBUG]  Locking SMM.[0m
[0m[DEBUG]  BS: BS_DEV_INIT_CHIPS entry times (exec / console): 882 / 645 ms[0m
[0m[DEBUG]  gpio_padcfg [0x6e, 08] DW0 [0x44000700 : 0x84000201 : 0x84000201][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 08] DW1 [0x00000020 : 0x00000000 : 0x00000020][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 08] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 08] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 11] DW0 [0x44000702 : 0x80900100 : 0x80900102][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 11] DW1 [0x00003023 : 0x00003000 : 0x00003023][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 11] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 11] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 13] DW0 [0x44000700 : 0x84000201 : 0x84000201][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 13] DW1 [0x00000025 : 0x00000000 : 0x00000025][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 13] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 13] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 15] DW0 [0x44000702 : 0x84000201 : 0x84000203][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 15] DW1 [0x00003027 : 0x00000000 : 0x00000027][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 15] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 15] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 16] DW0 [0x44000300 : 0x80900100 : 0x80900100][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 16] DW1 [0x00000028 : 0x00000000 : 0x00000028][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 16] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 16] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 25] DW0 [0x44000300 : 0x42880100 : 0x42880100][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 25] DW1 [0x00000030 : 0x00003000 : 0x00003030][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 25] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 25] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  GPE_EN[0x6e, 25]: Reg: 0x4, Value = 0x0[0m
[0m[DEBUG]  gpio_padcfg [0x6e, 27] DW0 [0x44000300 : 0x40100100 : 0x40100100][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 27] DW1 [0x00000032 : 0x00000000 : 0x00000032][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 27] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 27] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 28] DW0 [0x44000300 : 0x44000201 : 0x44000201][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 28] DW1 [0x00000033 : 0x00000000 : 0x00000033][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 28] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 28] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 29] DW0 [0x44000300 : 0x44000201 : 0x44000201][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 29] DW1 [0x00000034 : 0x00000000 : 0x00000034][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 29] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 29] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 39] DW0 [0x44000200 : 0x84000201 : 0x84000201][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 39] DW1 [0x0000003e : 0x00000000 : 0x0000003e][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 39] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 39] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 40] DW0 [0x44000300 : 0x44000200 : 0x44000200][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 40] DW1 [0x0000003f : 0x00000000 : 0x0000003f][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 40] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 40] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 41] DW0 [0x44000300 : 0x80100100 : 0x80100100][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 41] DW1 [0x00000040 : 0x00000000 : 0x00000040][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 41] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 41] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 42] DW0 [0x44000300 : 0x84000201 : 0x84000201][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 42] DW1 [0x00000041 : 0x00000000 : 0x00000041][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 42] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 42] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 43] DW0 [0x44000200 : 0x84000201 : 0x84000201][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 43] DW1 [0x00000042 : 0x00000000 : 0x00000042][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 43] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 43] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 48] DW0 [0x44000200 : 0x84000201 : 0x84000201][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 48] DW1 [0x00000047 : 0x00000000 : 0x00000047][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 48] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6e, 48] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 02] DW0 [0x44000200 : 0x44000201 : 0x44000201][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 02] DW1 [0x0000004a : 0x00000000 : 0x0000004a][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 02] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 02] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 05] DW0 [0x44000200 : 0x40880100 : 0x40880100][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 05] DW1 [0x0000004d : 0x00000000 : 0x0000004d][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 05] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 05] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  GPE_EN[0x6d, 05]: Reg: 0x0, Value = 0x940000[0m
[0m[DEBUG]  gpio_padcfg [0x6d, 08] DW0 [0x44000300 : 0x40900100 : 0x40900100][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 08] DW1 [0x00000050 : 0x00003000 : 0x00003050][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 08] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 08] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 09] DW0 [0x44000300 : 0x82880100 : 0x82880100][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 09] DW1 [0x00000051 : 0x00003000 : 0x00003051][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 09] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 09] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  GPE_EN[0x6d, 09]: Reg: 0x0, Value = 0x940000[0m
[0m[DEBUG]  gpio_padcfg [0x6d, 10] DW0 [0x44000300 : 0x84000200 : 0x84000200][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 10] DW1 [0x00000052 : 0x00000000 : 0x00000052][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 10] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 10] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 11] DW0 [0x44000300 : 0x44000201 : 0x44000201][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 11] DW1 [0x00000053 : 0x00003000 : 0x00003053][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 11] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 11] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 12] DW0 [0x44000300 : 0x84000201 : 0x84000201][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 12] DW1 [0x00000054 : 0x00000000 : 0x00000054][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 12] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 12] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 14] DW0 [0x44000300 : 0x84000201 : 0x84000201][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 14] DW1 [0x00000056 : 0x00000000 : 0x00000056][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 14] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 14] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 15] DW0 [0x44000300 : 0x84000201 : 0x84000201][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 15] DW1 [0x00000057 : 0x00000000 : 0x00000057][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 15] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 15] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 31] DW0 [0x44000300 : 0x80000100 : 0x80000100][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 31] DW1 [0x00000067 : 0x00000010 : 0x00000067][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 31] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 31] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 32] DW0 [0x44000300 : 0x80000100 : 0x80000100][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 32] DW1 [0x00000068 : 0x00000010 : 0x00000068][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 32] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 32] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 33] DW0 [0x44000300 : 0x84000201 : 0x84000201][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 33] DW1 [0x00000069 : 0x00000000 : 0x00000069][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 33] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 33] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 34] DW0 [0x44000300 : 0x80900100 : 0x80900100][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 34] DW1 [0x0000006a : 0x00003000 : 0x0000306a][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 34] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 34] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 35] DW0 [0x44001700 : 0x40880100 : 0x40880100][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 35] DW1 [0x0000006b : 0x00000000 : 0x0000006b][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 35] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 35] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  GPE_EN[0x6d, 35]: Reg: 0x4, Value = 0x200[0m
[0m[DEBUG]  gpio_padcfg [0x6d, 37] DW0 [0x44000300 : 0x44000201 : 0x44000201][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 37] DW1 [0x0000006d : 0x00000000 : 0x0000006d][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 37] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 37] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 38] DW0 [0x44000300 : 0x84000201 : 0x84000201][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 38] DW1 [0x0000006e : 0x00000000 : 0x0000006e][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 38] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 38] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 40] DW0 [0x44000300 : 0x40080100 : 0x40080100][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 40] DW1 [0x00000070 : 0x00000000 : 0x00000070][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 40] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 40] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  GPE_EN[0x6d, 40]: Reg: 0x4, Value = 0x200[0m
[0m[DEBUG]  gpio_padcfg [0x6d, 45] DW0 [0x44000300 : 0x80000400 : 0x80000400][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 45] DW1 [0x00000075 : 0x00000000 : 0x00000075][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 45] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 45] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 46] DW0 [0x44000300 : 0x80000400 : 0x80000400][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 46] DW1 [0x00000076 : 0x00000000 : 0x00000076][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 46] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 46] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 50] DW0 [0x44000702 : 0x80000100 : 0x80000102][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 50] DW1 [0x0000001a : 0x00003000 : 0x0000301a][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 50] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 50] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 51] DW0 [0x44000300 : 0x82040100 : 0x82040100][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 51] DW1 [0x0000001b : 0x00000000 : 0x0000001b][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 51] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 51] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 52] DW0 [0x44000300 : 0x40000400 : 0x40000400][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 52] DW1 [0x0000001c : 0x00000000 : 0x0000001c][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 52] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 52] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 54] DW0 [0x44000300 : 0x44080100 : 0x44080100][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 54] DW1 [0x0000001e : 0x00000000 : 0x0000001e][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 54] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 54] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  GPE_EN[0x6b, 54]: Reg: 0x8, Value = 0xffffffff[0m
[0m[DEBUG]  gpio_padcfg [0x6b, 55] DW0 [0x44000300 : 0x82000100 : 0x82000100][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 55] DW1 [0x0000001f : 0x00000010 : 0x0000001f][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 55] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 55] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 65] DW0 [0x44000702 : 0x84000201 : 0x84000203][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 65] DW1 [0x00000034 : 0x00000000 : 0x00000034][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 65] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 65] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 68] DW0 [0x44000300 : 0x80000100 : 0x80000100][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 68] DW1 [0x00000037 : 0x00000010 : 0x00000037][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 68] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 68] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 70] DW0 [0x44000300 : 0x84000201 : 0x84000201][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 70] DW1 [0x00000039 : 0x00000000 : 0x00000039][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 70] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 70] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 71] DW0 [0x44000300 : 0x80000100 : 0x80000100][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 71] DW1 [0x0000003a : 0x00000010 : 0x0000003a][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 71] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 71] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 53] DW0 [0x44000300 : 0x40000000 : 0x40000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 53] DW1 [0x00000071 : 0x00003000 : 0x00003071][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 53] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 53] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 55] DW0 [0x44000300 : 0x40000000 : 0x40000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 55] DW1 [0x00000073 : 0x00003000 : 0x00003073][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 55] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6d, 55] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 34] DW0 [0x44000300 : 0x84000201 : 0x84000201][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 34] DW1 [0x00000052 : 0x00000000 : 0x00000052][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 34] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 34] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 40] DW0 [0x44000300 : 0x84000201 : 0x84000201][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 40] DW1 [0x00000058 : 0x00000000 : 0x00000058][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 40] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 40] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 41] DW0 [0x44000300 : 0x84000200 : 0x84000200][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 41] DW1 [0x00000059 : 0x00000000 : 0x00000059][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 41] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 41] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 47] DW0 [0x44000300 : 0x82880100 : 0x82880100][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 47] DW1 [0x0000005f : 0x00000000 : 0x0000005f][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 47] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 47] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  GPE_EN[0x6b, 47]: Reg: 0x4, Value = 0x218[0m
[0m[DEBUG]  gpio_padcfg [0x6a, 38] DW0 [0x44000300 : 0x82900100 : 0x82900100][0m
[0m[DEBUG]  gpio_padcfg [0x6a, 38] DW1 [0x00000025 : 0x00003000 : 0x00003025][0m
[0m[DEBUG]  gpio_padcfg [0x6a, 38] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6a, 38] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6a, 40] DW0 [0x44000300 : 0x82100100 : 0x82100100][0m
[0m[DEBUG]  gpio_padcfg [0x6a, 40] DW1 [0x00000027 : 0x00000000 : 0x00000027][0m
[0m[DEBUG]  gpio_padcfg [0x6a, 40] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6a, 40] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6a, 41] DW0 [0x44000300 : 0x84000201 : 0x84000201][0m
[0m[DEBUG]  gpio_padcfg [0x6a, 41] DW1 [0x00000028 : 0x00000000 : 0x00000028][0m
[0m[DEBUG]  gpio_padcfg [0x6a, 41] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6a, 41] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6a, 48] DW0 [0x44000300 : 0x84000201 : 0x84000201][0m
[0m[DEBUG]  gpio_padcfg [0x6a, 48] DW1 [0x0000002f : 0x00000000 : 0x0000002f][0m
[0m[DEBUG]  gpio_padcfg [0x6a, 48] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6a, 48] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6a, 49] DW0 [0x44000700 : 0x84000201 : 0x84000201][0m
[0m[DEBUG]  gpio_padcfg [0x6a, 49] DW1 [0x00001030 : 0x00000000 : 0x00000030][0m
[0m[DEBUG]  gpio_padcfg [0x6a, 49] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6a, 49] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 01] DW0 [0x44000300 : 0x84000201 : 0x84000201][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 01] DW1 [0x00000019 : 0x00000000 : 0x00000019][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 01] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 01] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 02] DW0 [0x44000300 : 0x82080100 : 0x82080100][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 02] DW1 [0x0000001a : 0x00000000 : 0x0000001a][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 02] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 02] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  GPE_EN[0x6b, 02]: Reg: 0x0, Value = 0x940000[0m
[0m[DEBUG]  gpio_padcfg [0x6b, 11] DW0 [0x44000700 : 0x80880100 : 0x80880100][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 11] DW1 [0x00000023 : 0x00003000 : 0x00003023][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 11] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 11] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  GPE_EN[0x6b, 11]: Reg: 0x0, Value = 0x940000[0m
[0m[DEBUG]  gpio_padcfg [0x6b, 18] DW0 [0x44000300 : 0x80880100 : 0x80880100][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 18] DW1 [0x0000002a : 0x00000000 : 0x0000002a][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 18] DW2 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  gpio_padcfg [0x6b, 18] DW3 [0x00000000 : 0x00000000 : 0x00000000][0m
[0m[DEBUG]  GPE_EN[0x6b, 18]: Reg: 0x0, Value = 0x940000[0m
[0m[DEBUG]  WEAK: src/soc/intel/cannonlake/fsp_params.c/mainboard_silicon_init_params called[0m
[0m[INFO ]  VR config[0]:[0m
[0m[INFO ]    Psi1Threshold:  80[0m
[0m[INFO ]    Psi2Threshold:  20[0m
[0m[INFO ]    Psi3Threshold:  4[0m
[0m[INFO ]    Psi3Enable:     1[0m
[0m[INFO ]    Psi4Enable:     1[0m
[0m[INFO ]    ImonSlope:      0[0m
[0m[INFO ]    ImonOffset:     0[0m
[0m[INFO ]    VrVoltageLimit: 1520[0m
[0m[INFO ]    IccMax:         44[0m
[0m[INFO ]    AcLoadline:     1030[0m
[0m[INFO ]    DcLoadline:     1030[0m
[0m[INFO ]    TdcEnable:      1[0m
[0m[INFO ]    TdcPowerLimit:  80[0m
[0m[INFO ]  VR config[1]:[0m
[0m[INFO ]    Psi1Threshold:  80[0m
[0m[INFO ]    Psi2Threshold:  20[0m
[0m[INFO ]    Psi3Threshold:  4[0m
[0m[INFO ]    Psi3Enable:     1[0m
[0m[INFO ]    Psi4Enable:     1[0m
[0m[INFO ]    ImonSlope:      0[0m
[0m[INFO ]    ImonOffset:     0[0m
[0m[INFO ]    VrVoltageLimit: 1520[0m
[0m[INFO ]    IccMax:         512[0m
[0m[INFO ]    AcLoadline:     180[0m
[0m[INFO ]    DcLoadline:     180[0m
[0m[INFO ]    TdcEnable:      1[0m
[0m[INFO ]    TdcPowerLimit:  640[0m
[0m[INFO ]  VR config[2]:[0m
[0m[INFO ]    Psi1Threshold:  80[0m
[0m[INFO ]    Psi2Threshold:  20[0m
[0m[INFO ]    Psi3Threshold:  4[0m
[0m[INFO ]    Psi3Enable:     1[0m
[0m[INFO ]    Psi4Enable:     1[0m
[0m[INFO ]    ImonSlope:      0[0m
[0m[INFO ]    ImonOffset:     0[0m
[0m[INFO ]    VrVoltageLimit: 1520[0m
[0m[INFO ]    IccMax:         0[0m
[0m[INFO ]    AcLoadline:     270[0m
[0m[INFO ]    DcLoadline:     270[0m
[0m[INFO ]    TdcEnable:      1[0m
[0m[INFO ]    TdcPowerLimit:  200[0m
[0m[INFO ]  VR config[3]:[0m
[0m[INFO ]    Psi1Threshold:  80[0m
[0m[INFO ]    Psi2Threshold:  20[0m
[0m[INFO ]    Psi3Threshold:  4[0m
[0m[INFO ]    Psi3Enable:     1[0m
[0m[INFO ]    Psi4Enable:     1[0m
[0m[INFO ]    ImonSlope:      0[0m
[0m[INFO ]    ImonOffset:     0[0m
[0m[INFO ]    VrVoltageLimit: 1520[0m
[0m[INFO ]    IccMax:         0[0m
[0m[INFO ]    AcLoadline:     270[0m
[0m[INFO ]    DcLoadline:     270[0m
[0m[INFO ]    TdcEnable:      1[0m
[0m[INFO ]    TdcPowerLimit:  200[0m
[0m[INFO ]  PCI  1.0, PIN A, using IRQ #16[0m
[0m[INFO ]  PCI  1.1, PIN B, using IRQ #17[0m
[0m[INFO ]  PCI  1.2, PIN C, using IRQ #18[0m
[0m[INFO ]  PCI  1.3, PIN D, using IRQ #19[0m
[0m[INFO ]  PCI  2.0, PIN A, using IRQ #20[0m
[0m[INFO ]  PCI  4.0, PIN A, using IRQ #21[0m
[0m[INFO ]  PCI  5.0, PIN A, using IRQ #22[0m
[0m[INFO ]  PCI  8.0, PIN A, using IRQ #23[0m
[0m[INFO ]  PCI 12.0, PIN B, using IRQ #16[0m
[0m[INFO ]  PCI 12.6, PIN A, using IRQ #24[0m
[0m[INFO ]  PCI 13.0, PIN A, using IRQ #25[0m
[0m[INFO ]  PCI 14.0, PIN A, using IRQ #17[0m
[0m[INFO ]  PCI 14.1, PIN B, using IRQ #18[0m
[0m[INFO ]  PCI 14.3, PIN C, using IRQ #19[0m
[0m[INFO ]  PCI 14.5, PIN D, using IRQ #20[0m
[0m[INFO ]  PCI 15.0, PIN A, using IRQ #26[0m
[0m[INFO ]  PCI 15.1, PIN B, using IRQ #27[0m
[0m[INFO ]  PCI 15.2, PIN C, using IRQ #28[0m
[0m[INFO ]  PCI 15.3, PIN D, using IRQ #29[0m
[0m[INFO ]  PCI 16.0, PIN A, using IRQ #21[0m
[0m[INFO ]  PCI 16.1, PIN B, using IRQ #22[0m
[0m[INFO ]  PCI 16.2, PIN C, using IRQ #23[0m
[0m[INFO ]  PCI 16.3, PIN D, using IRQ #16[0m
[0m[INFO ]  PCI 16.4, PIN A, using IRQ #21[0m
[0m[INFO ]  PCI 16.5, PIN B, using IRQ #22[0m
[0m[INFO ]  PCI 17.0, PIN A, using IRQ #17[0m
[0m[INFO ]  PCI 19.2, PIN A, using IRQ #30[0m
[0m[INFO ]  PCI 1B.0, PIN A, using IRQ #16[0m
[0m[INFO ]  PCI 1B.1, PIN B, using IRQ #17[0m
[0m[INFO ]  PCI 1B.2, PIN C, using IRQ #18[0m
[0m[INFO ]  PCI 1B.3, PIN D, using IRQ #19[0m
[0m[INFO ]  PCI 1B.4, PIN A, using IRQ #16[0m
[0m[INFO ]  PCI 1B.5, PIN B, using IRQ #17[0m
[0m[INFO ]  PCI 1B.6, PIN C, using IRQ #18[0m
[0m[INFO ]  PCI 1B.7, PIN D, using IRQ #19[0m
[0m[INFO ]  PCI 1C.0, PIN A, using IRQ #16[0m
[0m[INFO ]  PCI 1C.1, PIN B, using IRQ #17[0m
[0m[INFO ]  PCI 1C.2, PIN C, using IRQ #18[0m
[0m[INFO ]  PCI 1C.3, PIN D, using IRQ #19[0m
[0m[INFO ]  PCI 1C.4, PIN A, using IRQ #16[0m
[0m[INFO ]  PCI 1C.5, PIN B, using IRQ #17[0m
[0m[INFO ]  PCI 1C.6, PIN C, using IRQ #18[0m
[0m[INFO ]  PCI 1C.7, PIN D, using IRQ #19[0m
[0m[INFO ]  PCI 1D.0, PIN A, using IRQ #16[0m
[0m[INFO ]  PCI 1D.1, PIN B, using IRQ #17[0m
[0m[INFO ]  PCI 1D.2, PIN C, using IRQ #18[0m
[0m[INFO ]  PCI 1D.3, PIN D, using IRQ #19[0m
[0m[INFO ]  PCI 1D.4, PIN A, using IRQ #16[0m
[0m[INFO ]  PCI 1D.5, PIN B, using IRQ #17[0m
[0m[INFO ]  PCI 1D.6, PIN C, using IRQ #18[0m
[0m[INFO ]  PCI 1D.7, PIN D, using IRQ #19[0m
[0m[INFO ]  PCI 1E.0, PIN A, using IRQ #31[0m
[0m[INFO ]  PCI 1E.1, PIN B, using IRQ #32[0m
[0m[INFO ]  PCI 1E.2, PIN C, using IRQ #33[0m
[0m[INFO ]  PCI 1E.3, PIN D, using IRQ #34[0m
[0m[INFO ]  PCI 1F.3, PIN B, using IRQ #21[0m
[0m[INFO ]  PCI 1F.4, PIN C, using IRQ #22[0m
[0m[INFO ]  PCI 1F.6, PIN D, using IRQ #23[0m
[0m[INFO ]  PCI 1F.7, PIN A, using IRQ #20[0m
[0m[INFO ]  IRQ: Using dynamically assigned PCI IO-APIC IRQs[0m
[0m[DEBUG]  PCI: 00:1e.0 10 <- [0x000000008f920000 - 0x000000008f920fff] size 0x00001000 gran 0x0c mem64[0m
[0m[DEBUG]  PCI: 00:1f.3 10 <- [0x000000008f910000 - 0x000000008f913fff] size 0x00004000 gran 0x0e mem64[0m
[0m[DEBUG]  PCI: 00:1f.3 20 <- [0x000000008f800000 - 0x000000008f8fffff] size 0x00100000 gran 0x14 mem64[0m
[0m[DEBUG]  PCI: 00:1f.4 10 <- [0x000000008f924000 - 0x000000008f9240ff] size 0x00000100 gran 0x08 mem64[0m
[0m[DEBUG]  PCI: 00:1f.5 10 <- [0x000000008f921000 - 0x000000008f921fff] size 0x00001000 gran 0x0c mem[0m
[0m[INFO ]  Done setting resources.[0m
[0m[INFO ]  Done allocating resources.[0m
[0m[DEBUG]  BS: BS_DEV_RESOURCES run times (exec / console): 3 / 75 ms[0m
[0m[DEBUG]  GLOBAL RESET![0m
[0m[INFO ]  global_reset() called![0m
[0m[DEBUG]  HECI: Global Reset(Type:1) Command