A new post titled "[GSoC] Better RISC-V support, week #2" has been published on the coreboot blog. Find the full post at http://blogs.coreboot.org/blog/2016/06/06/gsoc-better-risc-v-support-week-2/

<p>Last week, I updated my copy of <a href="https://github.com/riscv/riscv-isa-sim">spike</a> (to commit <a href="https://github.com/riscv/riscv-isa-sim/commit/2fe8a17abf9a3329f5314af89bce99385e5a16f6">2fe8a17a</a>), and familiarized myself with the differences between the old and the new version:</p>
<ul>
<li>The Host-Target Interface (HTIF) isn&#8217;t accessed through the <tt>mtohost</tt> and <tt>mfromhost</tt> CSRs anymore. Instead, you have to define two <a href="https://en.wikipedia.org/wiki/Executable_and_Linkable_Format">ELF</a> symbols (<tt>tohost</tt> and <tt>fromhost</tt>). Usually this is done by declaring two global variables with these names, but since the coreboot build system doesn&#8217;t natively produce an ELF file, it would get a little tricky.</li>
<li>Spike doesn&#8217;t implement a classic <a href="https://en.wikipedia.org/wiki/Universal_asynchronous_receiver/transmitter">UART</a>.</li>
<li>The memory layout is different. The default entry point is now at <tt>0x1000</tt>, where spike puts a small ROM, which jumps to the start of the emulated RAM, at <tt>0x80000000</tt>. One way to run coreboot is to load it at <tt>0x80000000</tt>, but then it can&#8217;t catch exceptions: The exception vector is at <tt>0x1010</tt>.</li>
<li>Within spike&#8217;s boot ROM, there&#8217;s also a text-based <a href="https://github.com/riscv/riscv-isa-sim/blob/7e5c1b420d0b332d6663a47182f9a472e400f663/riscv/sim.cc#L172">&#8220;platform tree&#8221;</a>, which describes the installed peripherals.</li>
</ul>
<p>&#8220;Why does coreboot need a serial console?&#8221;, you may ask. Coreboot uses it to log everything it does (at a configurable level of detail), and that&#8217;s quite useful for debugging and development.</p>
<p>Instead of working around the problems with HTIF, I decided to <a href="https://github.com/neuschaefer/riscv-isa-sim/commit/33e5b6f446cb21f54a04f6b7aec3cd2d81ab114f">implement</a> a minimal, <a href="https://en.wikipedia.org/wiki/8250_UART">8250</a>-compatible UART. I&#8217;m not done yet, but the goal is to use coreboot&#8217;s existing 8250 driver.</p>
<p><strong>Plans for this week</strong></p>
<p>This week, I will rewrite the bootblock and CBFS code to work with RISC-V&#8217;s new memory layout, and make sure that the spike UART works with coreboot&#8217;s 8250 UART driver. Booting Linux probably still takes some time.</p>