Dear Jose,

I felt that you are very close to resolving it and it is some minor issue not exactly in the Super I/O init code.

Great job and good luck with future challenges.

And of course enjoy coreboot!

Best regards,

-- 
Michał Żygowski
Firmware Engineer
https://3mdeb.com | @3mdeb_com
On 02.09.2020 16:12, Jose Trujillo via coreboot wrote:
Dear Michal:

Thank you very much for all your guidance.
The problem was resolved.

The code was OK but was not executed at the right time (was executed before LPC and SIO were initialized).

The attached code did the job

Have a great day.
Jose Trujillo.


‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐
On Tuesday, September 1, 2020 10:02 AM, Michal Zygowski <michal.zygowski@3mdeb.com> wrote:

Hi Jose,

and I do similar to you under romstage.c -> mainboard_early_init:
outb(0x55, 0x2e);
outb(0x05, 0x0a3f); /* GP50= RI_2 : in /
outb(0x05, 0x0a40); / GP51= DCD_2 : in /
outb(0x05, 0x0a41); / GP52= RXD_2 : in /
outb(0x04, 0x0a42); / GP53= TXD_2 : out /
outb(0x05, 0x0a43); / GP54= DSR_2 : in /
outb(0x04, 0x0a44); / GP55= RTS_2 : out /
outb(0x05, 0x0a45); / GP56= CTS_2 : in /
outb(0x04, 0x0a46); / GP57= DTR_2 : out */outb(0xaa, 0x2e);
but It doesn't work.
Also I set the same code under mainboard.c -> mainboard_init but
neither work.
You should not copy my code for the two major reasons:

1.  SCH5545 and SCH3114 are very different.
2.  GPIO configuration on SCH5545 is not accessible from SuperIO. The
    code I have written communicates with Environmental Controller (ARC
    coprocessor) which resides inside the SCH5545, because only the EC had
    access to those registers. The SCH5545 did not have GPIO config
    registers in the Runtime Registers block.

    This will obviously not work.


Any advice on this? because I cannot find any information on the
datasheet on how to set those registers and I suppose I just have to
set to the 0xa00 base address + register.
I suggest to look at TABLE 26-3 in the datasheet of your part
http://ww1.microchip.com/downloads/en/DeviceDoc/00001872A.pdf
and using these runtime registers definitions, write the right code that
will set the GPIOs up for UARTs.  Just use the appropriate 0xa00 base +
REG OFFSET from the table and you should be allright. For simplicity you
may also compare these registers to reference values from original
firmware (but with care! sometimes firmware vendors tend to make stupid
mistakes).

Thank you,
Jose Trujillo.
Best regards,

----------------

Michał Żygowski
Firmware Engineer
https://3mdeb.com | @3mdeb_com

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