[cathing up on my mail :-)]
"Adam Bezanson" firstname.lastname@example.org writes:
I've finally built linuxbios for my SC1200 based board. I've written my own flash programming utility so I can program the "romimage" file produced into my flash part from Linux command line. This all seems to work fine. On my board, I have the ability (with a jumper) to direct the ROMCS# signal to one of 3 chips on the board. One is a Disk on Chip which currently has a DOS filesystem on it, one is a 2Mbit flash chip which has the original Insyde BIOS, and the 3rd is a 16Mbit flash part soldered on the board where I'm trying to put linuxbios.
This 3rd chip is at 0xffe00000 - 0xffffffff, in order to enable this addressing I must hit bit 2 in F0 offset 0x52 to enable the Upper ROM size based on the ROM Mask at F0 offset 0x6e. This isn't enabled by default so I think as the chip comes up only 0xfffc0000 - 0xffffffff is visible. I'm not 100% sure, but I assume as the chip comes up it starts trying to fetch instructions from 0xfffc0000, is this true?
I think this is correct yes. If you get the ROMCS mapping to work you should either be able to use the MTD drivers (see if you can use the physmap driver in the Linux kernel), or use the devbios driver:
My question is, where should I program the "romimage" file that comes out of the build process? It would seem to me that the linuxbios.rom part would have to start at 0xfffc0000.
What I do is that I have the following options in my config file for LinuxBIOS:
option USE_GENERIC_ROM=1 option USE_ELF_BOOT=1 option ZKERNEL_START=0xfffe0000
Then I place linuxbios.rom in the last 64kByte of the BIOS chip (the CPU starts executing at linear address 0xfffffff0 with a magic segment selector in CS that starts at 0xffff0000) and additionally I place an etherboot image starting 128kBytes before the end of the BIOS chip. So with a 512kByte device with 128kByte pages that's accessible with the Linux MTD physmap driver I do:
modprobe -a physmap mtdchar
./erase /dev/mtd3 0x60000 dd if=natsemi.elf of=/dev/mtd3 bs=64k seek=2 dd if=linuxbios.rom of=/dev/mtd3 bs=64k seek=3
erase is a tool from the mtd utilities that erase a sector of a mtd device. natsemi.elf is the etherboot image that I've gotten by doing "make bin32/natsemi.elf".
So physically this means that linuxbios.rom is programmed at address 0xffff0000 and natsemi.elf is programmed at 0xfffe0000. Ah, yes, one more thing, I've added the attached patch that enables RAM from 0xe0000 to 0xfffff.
I hope this helps a bit.
--- northbridge/nsc/gx1/Config 16 Mar 2002 22:38:59 -0000 1.1 +++ northbridge/nsc/gx1/Config 5 Jan 2003 12:33:23 -0000 @@ -2,6 +2,8 @@ # Copyright (c) 2002 Christer Weinigel email@example.com # Configuration for the National Semiconductor GX1 processors
+option CONFIG_COMPRESS=1 + mainboardinit northbridge/nsc/gx1/cpu_setup.inc mainboardinit northbridge/nsc/gx1/gx_setup.inc mainboardinit northbridge/nsc/gx1/northbridge_setup.inc Index: northbridge/nsc/gx1/gx_setup.inc =================================================================== RCS file: /cvsroot/freebios/freebios/src/northbridge/nsc/gx1/gx_setup.inc,v retrieving revision 1.1 diff -u -r1.1 gx_setup.inc --- northbridge/nsc/gx1/gx_setup.inc 16 Mar 2002 22:39:00 -0000 1.1 +++ northbridge/nsc/gx1/gx_setup.inc 5 Jan 2003 12:33:23 -0000 @@ -32,7 +32,7 @@ .long BC_DRAM_TOP, 0x3fffffff .long BC_XMAP_1, 0x60 .long BC_XMAP_2, 0 - .long BC_XMAP_3, 0 + .long BC_XMAP_3, 0x77777777 /* Enable RAM from e0000-FFFFF */
.long MC_BANK_CFG, 0x00700070 /* No DIMMS installed */ .long MC_MEM_CNTRL1, XBUSARB