I did this exact thing while porting heads to a new motherboard, as the 4mb SPI was too small. Heres the steps, and they work.
_______________________________________________re-sending to coreboot list due to a problem with my gmail subscription.On Tue, Jan 14, 2020 at 10:32 AM Nico Huber <nico.h@gmx.de> wrote:
The IFD also contains a small table about flash chips (e.g. to know the
erase opcode / block size). I'm not sure if you need to adapt it or
if the PCH would fall back to automatic discovery via SFDP. Might also
depend on the PCH generation. I would match it with the new chip to be
on the safe side.This is an optional step. This table is more about letting ME know how to write to the specific chip. see https://github.com/corna/me_cleaner/issues/80IMHO, the worst thing you can do is to assume that it will work on the
first try. Better be prepared for more external flashingIt doesnt work on the first try, take it from me. I found the easiest way to do it was to use the stock factory rom, modify that with IFDtool and then use the newly modified IFD to build coreboot (while specifying new CBFS size inside of coreboot menuconfig)I did this exact thing while porting heads to a new motherboard, as the 4mb SPI was too small. Heres the steps, and they work.Step2 is optional and makes no difference to coreboot functionality. As noted above, its purely for ME.
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