coreboot-4.10-ae317695e3f03d55fbba1805ff06e004383e67c8 Mon Dec 2 16:05:12 UTC . Setting up static northbridge registers... done Initializing Graphics... Back from systemagent_early_init() POST: 0x38 SMBus controller enabled. POST: 0x39 POST: 0x3a Intel ME early init Intel ME firmware is ready ME: Requested 8MB UMA Starting native Platform init DMI: Running at X4 @ 5000MT/s FMAP: Found "FLASH" version 1.1 at 610000. FMAP: base = ff800000 size = 800000 #areas = 4 FMAP: area RW_MRC_CACHE found @ 600000 (65536 bytes) MRC: no data in 'RW_MRC_CACHE' SPD probe channel0, slot0 SPD probe channel0, slot1 SPD probe channel0, slot0 Row addr bits : 14 Column addr bits : 10 Number of ranks : 2 DIMM Capacity : 2048 MB CAS latencies : 6 7 8 9 tCKmin : 1.500 ns tAAmin : 13.125 ns tWRmin : 15.000 ns tRCDmin : 13.125 ns tRRDmin : 6.000 ns tRPmin : 13.125 ns tRASmin : 36.000 ns tRCmin : 49.125 ns tRFCmin : 110.000 ns tWTRmin : 7.500 ns tRTPmin : 7.500 ns tFAWmin : 30.000 ns channel[0] rankmap = 0x3 SPD probe channel0, slot1 SPD probe channel1, slot0 SPD probe channel1, slot1 SPD probe channel1, slot0 Row addr bits : 14 Column addr bits : 10 Number of ranks : 2 DIMM Capacity : 2048 MB CAS latencies : 6 7 8 9 tCKmin : 1.500 ns tAAmin : 13.125 ns tWRmin : 15.000 ns tRCDmin : 13.125 ns tRRDmin : 6.000 ns tRPmin : 13.125 ns tRASmin : 36.000 ns tRCmin : 49.125 ns tRFCmin : 110.000 ns tWTRmin : 7.500 ns tRTPmin : 7.500 ns tFAWmin : 30.000 ns channel[1] rankmap = 0x3 SPD probe channel1, slot1 Starting SandyBridge RAM training (0). Trying CAS 9, tCK 384. Found compatible clock, CAS pair. Selected DRAM frequency: 666 MHz Selected CAS latency : 9T PLL busy... done in 10 us MCU frequency is set at : 666 MHz Selected CWL latency : 7T Selected tRCD : 9T Selected tRP : 9T Selected tRAS : 24T Selected tWR : 10T Selected tFAW : 20T Selected tRRD : 4T Selected tRTP : 5T Selected tWTR : 5T Selected tRFC : 74T Done dimm mapping Update PCI-E configuration space: PCI(0, 0, 0)[a0] = 0 PCI(0, 0, 0)[a4] = 1 PCI(0, 0, 0)[bc] = 82a00000 PCI(0, 0, 0)[a8] = 7ce00000 PCI(0, 0, 0)[ac] = 1 PCI(0, 0, 0)[b8] = 80000000 PCI(0, 0, 0)[b0] = 80a00000 PCI(0, 0, 0)[b4] = 80800000 PCI(0, 0, 0)[7c] = 7f PCI(0, 0, 0)[70] = ff800000 PCI(0, 0, 0)[74] = 0 PCI(0, 0, 0)[78] = ff800c00 Done memory map Done io registers Done jedec reset Done MRS commands timC discovery failed: 1, 0, 6 t123: 1912, 9120, 500 ME: FW Partition Table : OK ME: Bringup Loader Failure : NO ME: Firmware Init Complete : NO ME: Manufacturing Mode : NO ME: Boot Options Present : NO ME: Update In Progress : NO ME: Current Working State : Initializing ME: Current Operation State : Bring up ME: Current Operation Mode : Normal ME: Error Code : Debug Failure ME: Progress Phase : BUP Phase ME: Power Management Event : Pseudo-global reset ME: Progress Phase State : 0x47 ME: HFS error : 4 ME: FWS2: 0x16470000 ME: Bist in progress: 0x0 ME: ICC Status : 0x0 ME: Invoke MEBx : 0x0 ME: CPU replaced : 0x0 ME: MBP ready : 0x0 ME: MFS failure : 0x0 ME: Warm reset req : 0x0 ME: CPU repl valid : 0x0 ME: (Reserved) : 0x0 ME: FW update req : 0x0 ME: (Reserved) : 0x0 ME: Current state : 0x47 ME: Current PM event: 0x6 ME: Progress code : 0x1 Waited long enough, or CPU was not replaced, continue... PASSED! Tell ME that DRAM is ready ME: FWS2: 0x16470000 ME: Bist in progress: 0x0 ME: ICC Status : 0x0 ME: Invoke MEBx : 0x0 ME: CPU replaced : 0x0 ME: MBP ready : 0x0 ME: MFS failure : 0x0 ME: Warm reset req : 0x0 ME: CPU repl valid : 0x0 ME: (Reserved) : 0x0 ME: FW update req : 0x0 ME: (Reserved) : 0x0 ME: Current state : 0x47 ME: Current PM event: 0x6 ME: Progress code : 0x1 ME: Requested BIOS Action: No DID Ack received ME: FW Partition Table : OK ME: Bringup Loader Failure : NO ME: Firmware Init Complete : NO ME: Manufacturing Mode : NO ME: Boot Options Present : NO ME: Update In Progress : NO ME: Current Working State : Initializing ME: Current Operation State : Bring up ME: Current Operation Mode : Normal ME: Error Code : Debug Failure ME: Progress Phase : BUP Phase ME: Power Management Event : Pseudo-global reset ME: Progress Phase State : 0x47 memcfg DDR3 ref clock 133 MHz memcfg DDR3 clock 1330 MHz memcfg channel assignment: A: 0, B 1, C 2 memcfg channel[0] config (00620008): ECC inactive enhanced interleave mode on rank interleave on DIMMA 2048 MB width x8 dual rank, selected DIMMB 0 MB width x8 single rank memcfg channel[1] config (00620008): ECC inactive enhanced interleave mode on rank interleave on DIMMA 2048 MB width x8 dual rank, selected DIMMB 0 MB width x8 single rank CBMEM: IMD: root @ 7ffff000 254 entries. IMD: root @ 7fffec00 62 entries. External stage cache: IMD: root @ 803ff000 254 entries. IMD: root @ 803fec00 62 entries. CBMEM entry for DIMM info: 0x7fffea40 POST: 0x3b POST: 0x3c POST: 0x3d POST: 0x3f MTRR Range: Start=ff800000 End=0 (Size 800000) MTRR Range: Start=0 End=1000000 (Size 1000000) MTRR Range: Start=7f800000 End=80000000 (Size 800000) MTRR Range: Start=80000000 End=80800000 (Size 800000) CBFS: 'Master Header Locator' located CBFS at [610200:800000) CBFS: Locating 'fallback/postcar' CBFS: Found @ offset 3d4c0 size 3e3c Decompressing stage fallback/postcar @ 0x7fff2fc0 (31704 bytes) Loading module at 7fff3000 with entry 7fff3000. filesize: 0x3c10 memsize: 0x7b98 Processing 116 relocs. Offset value of 0x7dff3000 coreboot-4.10-ae317695e3f03d55fbba1805ff06e004383e67c8 Mon Dec 2 16:05:12 UTC . CBFS: 'Master Header Locator' located CBFS at [610200:800000) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 15dc0 size 16a68 Decompressing stage fallback/ramstage @ 0x7ffacfc0 (281400 bytes) Loading module at 7ffad000 with entry 7ffad000. filesize: 0x2fad8 memsize: 0x448 Processing 3563 relocs. Offset value of 0x7f1ad000 coreboot-4.10-ae317695e3f03d55fbba1805ff06e004383e67c8 Mon Dec 2 16:05:12 UTC . POST: 0x39 POST: 0x80 Normal boot. POST: 0x70 BS: BS_PRE_DEVICE times (us): entry 0 run 1055 exit 0 POST: 0x71 BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 1059 exit 0 POST: 0x72 Enumerating buses... CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled PCI: pci_scan_bus for bus 00 POST: 0x24 PCI: 00:00.0 [8086/0104] enabled PCI: 00:01.0 [8086/0101] enabled PCI: 00:02.0 [8086/0116] enabled PCI: 00:04.0 [8086/0103] enabled PCI: 00:16.0 [8086/1c3a] enabled PCI: 00:16.1: Disabling device PCI: 00:16.2: Disabling device PCI: 00:16.3: Disabling device PCI: 00:19.0 [8086/1502] enabled PCI: 00:1a.0 [8086/1c2d] enabled PCI: 00:1b.0 [8086/1c20] enabled PCH: PCIe Root Port coalescing is enabled PCI: 00:1c.0 [8086/1c10] enabled PCI: 00:1c.1: Disabling device PCI: 00:1c.2: Disabling device PCI: 00:1c.3: Disabling device PCI: 00:1c.4: Disabling device PCI: 00:1c.4: check set enabled PCH: Remap PCIe function 5 to 1 PCI: 00:1c.5 [8086/1c1a] enabled PCH: Remap PCIe function 6 to 1 PCI: 00:1c.6 [8086/1c1c] enabled PCI: 00:1c.7: Disabling device PCH: PCIe map 1c.1 -> 1c.6 PCH: PCIe map 1c.5 -> 1c.1 PCH: PCIe map 1c.6 -> 1c.5 PCI: 00:1d.0 [8086/1c26] enabled PCI: 00:1e.0: Disabling device PCI: 00:1e.0 [8086/2448] disabled PCI: 00:1f.0 [8086/1c4f] enabled PCI: 00:1f.2 [8086/1c01] enabled PCI: 00:1f.3 [8086/1c22] enabled PCI: 00:1f.5 [8086/1c09] enabled PCI: 00:1f.6: Disabling device PCI: 00:1f.6 [8086/1c24] disabled No operations POST: 0x25 PCI: Leftover static devices: PCI: 00:16.1 PCI: 00:16.2 PCI: 00:16.3 PCI: 00:1c.6 PCI: 00:1c.2 PCI: 00:1c.3 PCI: 00:1c.4 PCI: 00:1c.7 PCI: Check your devicetree.cb. PCI: pci_scan_bus for bus 01 POST: 0x24 POST: 0x25 POST: 0x55 scan_bus: scanning of bus PCI: 00:01.0 took 5779 usecs PCI: pci_scan_bus for bus 02 POST: 0x24 POST: 0x25 POST: 0x55 scan_bus: scanning of bus PCI: 00:1c.0 took 5812 usecs PCI: pci_scan_bus for bus 03 POST: 0x24 PCI: 03:00.0 [197b/2368] enabled POST: 0x25 POST: 0x55 Enabling Common Clock Configuration ASPM: Enabled None Failed to enable LTR for dev = PCI: 03:00.0 scan_bus: scanning of bus PCI: 00:1c.1 took 17779 usecs PCI: pci_scan_bus for bus 04 POST: 0x24 PCI: 04:00.0 subordinate PCI PCI: 04:00.0 [10b5/8112] enabled POST: 0x25 PCI: pci_scan_bus for bus 05 POST: 0x24 POST: 0x25 POST: 0x55 scan_bus: scanning of bus PCI: 04:00.0 took 5860 usecs POST: 0x55 ASPM: Enabled None Failed to enable LTR for dev = PCI: 04:00.0 scan_bus: scanning of bus PCI: 00:1c.5 took 27852 usecs PNP: 002e.0 disabled PNP: 002e.1 disabled PNP: 002e.2 enabled PNP: 002e.3 enabled PNP: 002e.5 disabled PNP: 002e.6 disabled PNP: 002e.307 disabled PNP: 002e.8 disabled PNP: 002e.9 enabled PNP: 002e.109 enabled PNP: 002e.209 disabled PNP: 002e.309 disabled PNP: 002e.a disabled PNP: 002e.b disabled PNP: 002e.c disabled scan_bus: scanning of bus PCI: 00:1f.0 took 29411 usecs scan_bus: scanning of bus PCI: 00:1f.3 took 2 usecs POST: 0x55 scan_bus: scanning of bus DOMAIN: 0000 took 239107 usecs scan_bus: scanning of bus Root Device took 248147 usecs done FMAP: Found "FLASH" version 1.1 at 610000. FMAP: base = ff800000 size = 800000 #areas = 4 FMAP: area RW_MRC_CACHE found @ 600000 (65536 bytes) MRC: Checking cached data update for 'RW_MRC_CACHE'. Manufacturer: ef SF: Detected W25Q64_V with sector size 0x1000, total 0x800000 MRC: no data in 'RW_MRC_CACHE' MRC: cache data 'RW_MRC_CACHE' needs update. BS: BS_DEV_ENUMERATE times (us): entry 0 run 256641 exit 35424 POST: 0x73 found VGA at PCI: 00:02.0 Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. Done reading resources. Setting resources... TOUUD 0x17ce00000 TOLUD 0x82a00000 TOM 0x100000000 MEBASE 0xff800000 IGD decoded, subtracting 32M UMA and 2M GTT TSEG base 0x80000000 size 8M Available memory below 4GB: 2048M Available memory above 4GB: 1998M PCI: 00:01.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus o PCI: 00:01.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus m PCI: 00:01.0 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus m PCI: 00:02.0 10 <- [0x00e0000000 - 0x00e03fffff] size 0x00400000 gran 0x16 mem64 PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c pref4 PCI: 00:02.0 20 <- [0x0000002000 - 0x000000203f] size 0x00000040 gran 0x06 io PCI: 00:04.0 10 <- [0x00e0620000 - 0x00e0627fff] size 0x00008000 gran 0x0f mem64 PCI: 00:16.0 10 <- [0x00e0631000 - 0x00e063100f] size 0x00000010 gran 0x04 mem64 PCI: 00:19.0 10 <- [0x00e0600000 - 0x00e061ffff] size 0x00020000 gran 0x11 mem PCI: 00:19.0 14 <- [0x00e062c000 - 0x00e062cfff] size 0x00001000 gran 0x0c mem PCI: 00:19.0 18 <- [0x0000002040 - 0x000000205f] size 0x00000020 gran 0x05 io PCI: 00:1a.0 10 <- [0x00e062e000 - 0x00e062e3ff] size 0x00000400 gran 0x0a mem PCI: 00:1b.0 10 <- [0x00e0628000 - 0x00e062bfff] size 0x00004000 gran 0x0e mem64 PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus o PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus m PCI: 00:1c.0 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus m PCI: 00:1c.1 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus o PCI: 00:1c.1 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus m PCI: 00:1c.1 20 <- [0x00e0400000 - 0x00e04fffff] size 0x00100000 gran 0x14 bus m PCI: 03:00.0 10 <- [0x0000001010 - 0x0000001017] size 0x00000008 gran 0x03 io PCI: 03:00.0 14 <- [0x0000001020 - 0x0000001023] size 0x00000004 gran 0x02 io PCI: 03:00.0 18 <- [0x0000001018 - 0x000000101f] size 0x00000008 gran 0x03 io PCI: 03:00.0 1c <- [0x0000001024 - 0x0000001027] size 0x00000004 gran 0x02 io PCI: 03:00.0 20 <- [0x0000001000 - 0x000000100f] size 0x00000010 gran 0x04 io PCI: 03:00.0 30 <- [0x00e0400000 - 0x00e040ffff] size 0x00010000 gran 0x10 romem PCI: 00:1c.5 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus o PCI: 00:1c.5 24 <- [0x00e0500000 - 0x00e05fffff] size 0x00100000 gran 0x14 bus m PCI: 00:1c.5 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus m PCI: 04:00.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus o PCI: 04:00.0 24 <- [0x00e05fffff - 0x00e05ffffe] size 0x00000000 gran 0x14 bus m PCI: 04:00.0 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus m PCI: 04:00.0 10 <- [0x00e0500000 - 0x00e050ffff] size 0x00010000 gran 0x10 pref4 PCI: 00:1d.0 10 <- [0x00e062f000 - 0x00e062f3ff] size 0x00000400 gran 0x0a mem PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq PCI: 00:1f.2 10 <- [0x00000020a0 - 0x00000020a7] size 0x00000008 gran 0x03 io PCI: 00:1f.2 14 <- [0x00000020c0 - 0x00000020c3] size 0x00000004 gran 0x02 io PCI: 00:1f.2 18 <- [0x00000020a8 - 0x00000020af] size 0x00000008 gran 0x03 io PCI: 00:1f.2 1c <- [0x00000020c4 - 0x00000020c7] size 0x00000004 gran 0x02 io PCI: 00:1f.2 20 <- [0x0000002060 - 0x000000207f] size 0x00000020 gran 0x05 io PCI: 00:1f.2 24 <- [0x00e062d000 - 0x00e062d7ff] size 0x00000800 gran 0x0b mem PCI: 00:1f.3 10 <- [0x00e0630000 - 0x00e06300ff] size 0x00000100 gran 0x08 mem64 PCI: 00:1f.5 10 <- [0x00000020b0 - 0x00000020b7] size 0x00000008 gran 0x03 io PCI: 00:1f.5 14 <- [0x00000020c8 - 0x00000020cb] size 0x00000004 gran 0x02 io PCI: 00:1f.5 18 <- [0x00000020b8 - 0x00000020bf] size 0x00000008 gran 0x03 io PCI: 00:1f.5 1c <- [0x00000020cc - 0x00000020cf] size 0x00000004 gran 0x02 io PCI: 00:1f.5 20 <- [0x0000002080 - 0x000000208f] size 0x00000010 gran 0x04 io PCI: 00:1f.5 24 <- [0x0000002090 - 0x000000209f] size 0x00000010 gran 0x04 io Done setting resources. Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 0 run 410810 exit 0 POST: 0x74 Enabling resources... PCI: 00:00.0 subsystem <- 8086/0104 PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 bridge ctrl <- 0003 PCI: 00:01.0 subsystem <- 8086/0101 PCI: 00:01.0 cmd <- 00 PCI: 00:02.0 subsystem <- 8086/2010 PCI: 00:02.0 cmd <- 03 PCI: 00:04.0 cmd <- 02 PCI: 00:16.0 subsystem <- 8086/1c3a PCI: 00:16.0 cmd <- 02 PCI: 00:19.0 subsystem <- 8086/1502 PCI: 00:19.0 cmd <- 103 PCI: 00:1a.0 subsystem <- 8086/1c2d PCI: 00:1a.0 cmd <- 102 PCI: 00:1b.0 subsystem <- 8086/1c20 PCI: 00:1b.0 cmd <- 102 PCI: 00:1c.0 bridge ctrl <- 0003 PCI: 00:1c.0 subsystem <- 8086/1c10 PCI: 00:1c.0 cmd <- 100 PCI: 00:1c.1 bridge ctrl <- 0003 PCI: 00:1c.1 subsystem <- 8086/1c1a PCI: 00:1c.1 cmd <- 107 PCI: 00:1c.5 bridge ctrl <- 0003 PCI: 00:1c.5 subsystem <- 8086/1c1c PCI: 00:1c.5 cmd <- 106 PCI: 00:1d.0 subsystem <- 8086/1c26 PCI: 00:1d.0 cmd <- 102 pch_decode_init PCI: 00:1f.0 subsystem <- 8086/1c4f PCI: 00:1f.0 cmd <- 107 PCI: 00:1f.2 subsystem <- 8086/1c01 PCI: 00:1f.2 cmd <- 03 PCI: 00:1f.3 subsystem <- 8086/1c22 PCI: 00:1f.3 cmd <- 103 PCI: 00:1f.5 subsystem <- 8086/1c09 PCI: 00:1f.5 cmd <- 01 PCI: 03:00.0 cmd <- 03 PCI: 04:00.0 bridge ctrl <- 0003 PCI: 04:00.0 cmd <- 02 done. BS: BS_DEV_ENABLE times (us): entry 0 run 106740 exit 0 Found TPM SLB9635 TT 1.2 by Infineon TPM: Startup TPM: command 0x99 returned 0x0 TPM: Asserting physical presence TPM: command 0x4000000a returned 0x0 TPM: command 0x65 returned 0x0 TPM: Can't read capabilities. POST: 0xed POST: 0x75 Initializing devices... Root Device init ... Root Device init finished in 1918 usecs POST: 0x75 CPU_CLUSTER: 0 init ... MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6 0x0000000080000000 - 0x00000000d0000000 size 0x50000000 type 0 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6 MTRR: Fixed MSR 0x250 0x0606060606060606 MTRR: Fixed MSR 0x258 0x0606060606060606 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 MTRR: Fixed MSR 0x26a 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 MTRR: Fixed MSR 0x26c 0x0606060606060606 MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 CPU physical address size: 36 bits MTRR: default type WB/UC MTRR counts: 4/3. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6 MTRR: 1 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1 MTRR: 2 base 0x0000000100000000 mask 0x0000000f80000000 type 6 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 CPU has 2 cores, 4 threads enabled. Setting up SMI for CPU Will perform SMM setup. CBFS: 'Master Header Locator' located CBFS at [610200:800000) CBFS: Locating 'cpu_microcode_blob.bin' CBFS: Found @ offset 12d40 size 3000 microcode: sig=0x206a7 pf=0x10 revision=0x2f CPU: Intel(R) Core(TM) i5-2515E CPU @ 2.50GHz. Loading module at 00030000 with entry 00030000. filesize: 0x170 memsize: 0x170 Processing 16 relocs. Offset value of 0x00030000 Attempting to start 3 APs Waiting for 10ms after sending INIT. Waiting for 1st SIPI to complete...AP: slot 1 apic_id 1. done. Waiting for 2nd SIPI to complete...done. AP: slot 3 apic_id 2. AP: slot 2 apic_id 3. Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8 Processing 13 relocs. Offset value of 0x00038000 SMM Module: stub loaded at 00038000. Will call 7ffc6064(00000000) Installing SMM handler to 0x80000000 Loading module at 80010000 with entry 80010112. filesize: 0x10c8 memsize: 0x50e8 Processing 51 relocs. Offset value of 0x80010000 Loading module at 80008000 with entry 80008000. filesize: 0x1a8 memsize: 0x1a8 Processing 13 relocs. Offset value of 0x80008000 SMM Module: placing jmp sequence at 80007c00 rel16 0x03fd SMM Module: placing jmp sequence at 80007800 rel16 0x07fd SMM Module: placing jmp sequence at 80007400 rel16 0x0bfd SMM Module: stub loaded at 80008000. Will call 80010112(00000000) Initializing Southbridge SMI... New SMBASE 0x80000000 In relocation handler: cpu 0 New SMBASE=0x80000000 IEDBASE=0x80400000 Writing SMRR. base = 0x80000006, mask=0xff800800 Relocation complete. microcode: Update skipped, already up-to-date New SMBASE 0x7ffffc00 In relocation handler: cpu 1 New SMBASE=0x7ffffc00 IEDBASE=0x80400000 Writing SMRR. base = 0x80000006, mask=0xff800800 Relocation complete. microcode: Update skipped, already up-to-date New SMBASE 0x7ffff400 In relocation handler: cpu 3 New SMBASE=0x7ffff400 IEDBASE=0x80400000 Writing SMRR. base = 0x80000006, mask=0xff800800 Relocation complete. microcode: Update skipped, already up-to-date New SMBASE 0x7ffff800 In relocation handler: cpu 2 New SMBASE=0x7ffff800 IEDBASE=0x80400000 Writing SMRR. base = 0x80000006, mask=0xff800800 Relocation complete. microcode: Update skipped, already up-to-date Initializing CPU #0 CPU: vendor Intel device 206a7 CPU: family 06, model 2a, stepping 07 POST: 0x60 Enabling cache CPU: Intel(R) Core(TM) i5-2515E CPU @ 2.50GHz. CPU: platform id 4 CPU: cpuid(1) 0x206a7 CPU: AES supported CPU: TXT supported CPU: VT supported Setting up local APIC... apic_id: 0x00 done. IA32_FEATURE_CONTROL already locked; VMX status: enabled IA32_FEATURE_CONTROL already locked model_x06ax: energy policy set to 6 model_x06ax: frequency set to 2500 Turbo is available but hidden Turbo has been enabled CPU #0 initialized Initializing CPU #1 Initializing CPU #2 Initializing CPU #3 CPU: vendor Intel device 206a7 CPU: family 06, model 2a, stepping 07 CPU: vendor Intel device 206a7 CPU: family 06, model 2a, stepping 07 POST: 0x60 POST: 0x60 Enabling cache Enabling cache CPU: Intel(R) Core(TM) i5-2515E CPU @ 2.50GHz. CPU: Intel(R) Core(TM) i5-2515E CPU @ 2.50GHz. CPU: platform id 4 CPU: platform id 4 CPU: cpuid(1) 0x206a7 CPU: cpuid(1) 0x206a7 CPU: AES supported CPU: TXT supported CPU: VT supported CPU: AES supported CPU: TXT supported CPU: VT supported Setting up local APIC... Setting up local APIC... apic_id: 0x03 done. apic_id: 0x02 done. IA32_FEATURE_CONTROL already locked; VMX status: enabled IA32_FEATURE_CONTROL already locked; VMX status: enabled IA32_FEATURE_CONTROL already locked IA32_FEATURE_CONTROL already locked model_x06ax: energy policy set to 6 model_x06ax: energy policy set to 6 model_x06ax: frequency set to 2500 model_x06ax: frequency set to 2500 CPU #3 initialized CPU #2 initialized CPU: vendor Intel device 206a7 CPU: family 06, model 2a, stepping 07 POST: 0x60 Enabling cache CPU: Intel(R) Core(TM) i5-2515E CPU @ 2.50GHz. CPU: platform id 4 CPU: cpuid(1) 0x206a7 CPU: AES supported CPU: TXT supported CPU: VT supported Setting up local APIC... apic_id: 0x01 done. IA32_FEATURE_CONTROL already locked; VMX status: enabled IA32_FEATURE_CONTROL already locked model_x06ax: energy policy set to 6 model_x06ax: frequency set to 2500 CPU #1 initialized bsp_do_flight_plan done after 331 msecs. Initializing southbridge SMI... SMI_STS: GPE0_STS: GPIO15 GPIO3 GPIO2 GPIO1 GPIO0 ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI10 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 TCO_STS: Locking SMM. CPU_CLUSTER: 0 init finished in 538897 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:00.0 init ... Disabling PEG12. Disabling PEG11. Disabling PEG60. Disabling Device 7. Set BIOS_RESET_CPL CPU TDP: 35 Watts PCI: 00:00.0 init finished in 12960 usecs POST: 0x75 PCI: 00:01.0 init ... PCI: 00:01.0 init finished in 2004 usecs POST: 0x75 PCI: 00:02.0 init ... GT Power Management Init SNB GT2 Power Meter Weights CBFS: 'Master Header Locator' located CBFS at [610200:800000) CBFS: Locating 'pci8086,0116.rom' CBFS: Found @ offset 2d440 size 10000 In CBFS, ROM address for PCI: 00:02.0 = ffe3d688 Copying VGA ROM Image from ffe3d688 to 0xc0000, 0xf200 bytes Calling Option ROM... intel_vga_int15_handler: AX=5f34 BX=c000 CX=0002 DX=03da intel_vga_int15_handler: AX=5f52 BX=0000 CX=0002 DX=0008 Unknown INT15 function 5f52! int15 call returned error. intel_vga_int15_handler: AX=5f14 BX=078f CX=000a DX=fde8 Unknown INT15 function 5f14! int15 call returned error. intel_vga_int15_handler: AX=5f35 BX=c000 CX=0002 DX=03da intel_vga_int15_handler: AX=5f70 BX=c003 CX=0002 DX=0303 ... Option ROM returned. VBE: Getting information about VESA mode 4116 VBE: Function call failed! Error: In vbe_get_mode_info function