diff --git a/src/devices/hypertransport.c b/src/devices/hypertransport.c
index 1458297..28051f5 100644
--- a/src/devices/hypertransport.c
+++ b/src/devices/hypertransport.c
@@ -597,7 +597,7 @@ unsigned int hypertransport_scan_chain(struct bus *bus,
 	/* Now that nothing is overlapping it is safe to scan the
 	 * children. 
 	 */
-	max = pci_scan_bus(bus, 0x00, ((next_unitid-1) << 3)|7, max); 
+	max = pci_scan_bus(bus, 0x00, 0xff & (((next_unitid-1) << 3)|7), max); 
 	return max; 
 }
 
diff --git a/src/mainboard/tyan/s2912_fam10/Config.lb b/src/mainboard/tyan/s2912_fam10/Config.lb
index 01b7375..8e07ed7 100644
--- a/src/mainboard/tyan/s2912_fam10/Config.lb
+++ b/src/mainboard/tyan/s2912_fam10/Config.lb
@@ -82,16 +82,17 @@ if HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
 
 if USE_DCACHE_RAM
+	makedefine CACHE_AS_RAM_AUTO_C:=cache_as_ram_auto.c
 
 	if CONFIG_USE_INIT	
 		makerule ./cache_as_ram_auto.o
-		        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+			depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h"
         		action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
 		end
 	else
 		makerule ./cache_as_ram_auto.inc
-        		depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		        action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
+			depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h"
+			action "$(CC) -I$(TOP)/src -I. $(CFLAGS) $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
 		        action "perl -e 's/.rodata/.rom.data/g' -pi $@"
         		action "perl -e 's/.text/.section .rom.text/g' -pi $@"
 		end
@@ -226,18 +227,20 @@ if CONFIG_CHIP_NAME
 	config chip.h
 end
 
-chip northbridge/amd/amdk8/root_complex
+dir /southbridge/nvidia/mcp55
+
+chip northbridge/amd/amdfam10/root_complex
         device apic_cluster 0 on
-                chip cpu/amd/socket_F
+                chip cpu/amd/socket_F_1207
                         device apic 0 on end
                 end
         end
 	device pci_domain 0 on
-		chip northbridge/amd/amdk8 #mc0
+		chip northbridge/amd/amdfam10 #mc0
 			device pci 18.0 on end
 			device pci 18.0 on end 
 			device pci 18.0 on 
-				#  devices on link 0, link 0 == LDT 0 
+				#  SB on link 2.0.
 			        chip southbridge/nvidia/mcp55 
 					device pci 0.0 on end   # HT
                 			device pci 1.0 on # LPC
@@ -339,7 +342,12 @@ chip northbridge/amd/amdk8/root_complex
 	                		device pci 5.0 on end # SATA 0
 	                		device pci 5.1 on end # SATA 1
 	                		device pci 5.2 on end # SATA 2
-                			device pci 6.0 on end # PCI
+                			device pci 6.0 on
+                                                chip drivers/pci/onboard
+                                                        device pci 4.0 on end
+							register "rom_address" = "0xfff80000"
+						end
+					 end # PCI
         	        		device pci 6.1 off end # AZA
 	                		device pci 8.0 on end # NIC
 	                		device pci 9.0 on end # NIC
@@ -359,6 +367,7 @@ chip northbridge/amd/amdk8/root_complex
 			device pci 18.1 on end
 			device pci 18.2 on end
 			device pci 18.3 on end
+			device pci 18.4 on end
 		end # mc0
 		
 	end # PCI domain
diff --git a/src/mainboard/tyan/s2912_fam10/Options.lb b/src/mainboard/tyan/s2912_fam10/Options.lb
index 3326cdb..0f5f96d 100644
--- a/src/mainboard/tyan/s2912_fam10/Options.lb
+++ b/src/mainboard/tyan/s2912_fam10/Options.lb
@@ -46,7 +46,6 @@ uses CONFIG_ROM_PAYLOAD
 uses CONFIG_ROM_PAYLOAD_START
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
 uses PAYLOAD_SIZE
 uses _ROMBASE
 uses XIP_ROM_SIZE
@@ -84,7 +83,6 @@ uses CONFIG_USBDEBUG_DIRECT
 uses CONFIG_PCI_ROM_RUN
 uses HW_MEM_HOLE_SIZEK
 uses HW_MEM_HOLE_SIZE_AUTO_INC
-uses K8_HT_FREQ_1G_SUPPORT
 
 uses HT_CHAIN_UNITID_BASE
 uses HT_CHAIN_END_UNITID_BASE
@@ -107,13 +105,19 @@ uses CONFIG_PCI_64BIT_PREF_MEM
 
 uses CONFIG_LB_MEM_TOPK
 
+uses PCI_BUS_SEGN_BITS
+
 uses CONFIG_AP_CODE_IN_CAR
 
 uses MEM_TRAIN_SEQ
 
 uses WAIT_BEFORE_CPUS_INIT
 
+uses CONFIG_AMDMCT
+
 uses CONFIG_USE_PRINTK_IN_CAR
+uses CAR_FAM10
+uses AMD_UCODE_PATCH_FILE
 
 ###
 ### Build options
@@ -132,12 +136,12 @@ default ROM_SIZE=524288
 #default FALLBACK_SIZE=0x40000
 
 #FALLBACK: 256K-4K
-default FALLBACK_SIZE=0x3f000
+default FALLBACK_SIZE=0x7f000
 #FAILOVER: 4K
 default FAILOVER_SIZE=0x01000
 
 #more 1M for pgtbl
-default CONFIG_LB_MEM_TOPK=2048
+default CONFIG_LB_MEM_TOPK=16384
 
 ##
 ## Build code for the fallback boot
@@ -165,7 +169,7 @@ default HAVE_MP_TABLE=1
 ## ACPI tables will be included
 default HAVE_ACPI_TABLES=0
 ## extra SSDT num
-default ACPI_SSDTX_NUM=3
+default ACPI_SSDTX_NUM=31
 
 ##
 ## Build code to export a CMOS option table
@@ -184,14 +188,14 @@ default LB_CKS_LOC=123
 ## Only worry about 2 micro processors
 ##
 default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
 default CONFIG_MAX_PHYSICAL_CPUS=2
+default CONFIG_MAX_CPUS=4 * CONFIG_MAX_PHYSICAL_CPUS
 default CONFIG_LOGICAL_CPUS=1
 
 #default SERIAL_CPU_INIT=0
 
-default ENABLE_APIC_EXT_ID=0
-default APIC_ID_OFFSET=0x10
+default ENABLE_APIC_EXT_ID=1
+default APIC_ID_OFFSET=0x00
 default LIFT_BSP_APIC_ID=1
 
 #CHIP_NAME ?
@@ -208,9 +212,6 @@ default HW_MEM_HOLE_SIZEK=0x100000
 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
 #default HW_MEM_HOLE_SIZE_AUTO_INC=1
 
-#Opteron K8 1G HT Support
-default K8_HT_FREQ_1G_SUPPORT=1
-
 #VGA Console
 default CONFIG_CONSOLE_VGA=1
 default CONFIG_PCI_ROM_RUN=1
@@ -218,7 +219,7 @@ default CONFIG_PCI_ROM_RUN=1
 #default CONFIG_USBDEBUG_DIRECT=1
 
 #HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device
-default HT_CHAIN_UNITID_BASE=0
+default HT_CHAIN_UNITID_BASE=1
 
 #real SB Unit ID, default is 0x20, mean dont touch it at last
 #default HT_CHAIN_END_UNITID_BASE=0x6
@@ -236,14 +237,14 @@ default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
 ## enable CACHE_AS_RAM specifics
 ##
 default USE_DCACHE_RAM=1
-default DCACHE_RAM_BASE=0xc8000
-default DCACHE_RAM_SIZE=0x08000
-default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
+default DCACHE_RAM_BASE=0xc4000
+default DCACHE_RAM_SIZE=0x0c000
+default DCACHE_RAM_GLOBAL_VAR_SIZE=0x04000
 default CONFIG_USE_INIT=0
 
-default CONFIG_AP_CODE_IN_CAR=0
-default MEM_TRAIN_SEQ=1
-default WAIT_BEFORE_CPUS_INIT=1
+default MEM_TRAIN_SEQ=2
+default WAIT_BEFORE_CPUS_INIT=0
+default CONFIG_AMDMCT = 1
 
 ##
 ## Build code to setup a generic IOAPIC
@@ -253,11 +254,20 @@ default CONFIG_IOAPIC=1
 ##
 ## Clean up the motherboard id strings
 ##
-default MAINBOARD_PART_NUMBER="S2912"
+default MAINBOARD_PART_NUMBER="S2912 (Fam10)"
 default MAINBOARD_VENDOR="Tyan"
 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2912
 
+##
+## Set microcode patch file name
+##
+##      Barcelona rev Ax:  "mc_patch_01000020.h"
+##      Barcelona rev B0, B1, BA: "mc_patch_01000084.h"
+##      Barcelona rev B2, B3: "mc_patch_01000083.h"
+##
+default AMD_UCODE_PATCH_FILE="mc_patch_01000083.h"
+
 ###
 ### coreboot layout values
 ###
@@ -273,7 +283,7 @@ default STACK_SIZE=0x2000
 ##
 ## Use a small 32K heap
 ##
-default HEAP_SIZE=0x8000
+default HEAP_SIZE=0xc0000
 
 ##
 ## Only use the option table in a normal image
@@ -283,7 +293,7 @@ default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
 ##
 ## Coreboot C code runs at this location in RAM
 ##
-default _RAMBASE=0x00100000
+default _RAMBASE=0x00200000
 
 ##
 ## Load the payload from the ROM
diff --git a/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c b/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c
index 3c97280..9cd2a4f 100644
--- a/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c
+++ b/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c
@@ -24,9 +24,8 @@
 
 #define RAMINIT_SYSINFO 1
 
-#define K8_ALLOCATE_IO_RANGE 1
-//#define K8_SCAN_PCI_BUS 1
-
+#define FAM10_SCAN_PCI_BUS 0
+#define FAM10_ALLOCATE_IO_RANGE 0
 
 #define QRANK_DIMM_SUPPORT 1
 
@@ -34,14 +33,8 @@
 #define SET_NB_CFG_54 1
 #endif
 
-//used by init_cpus and fidvid
-#define K8_SET_FIDVID 0
-//if we want to wait for core1 done before DQS training, set it to 0
-#define K8_SET_FIDVID_CORE0_ONLY 1
-
-#if K8_REV_F_SUPPORT == 1
-#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
-#endif
+#define FAM10_SET_FIDVID 1
+#define FAM10_SET_FIDVID_CORE_RANGE 0
 
 #define DBGP_DEFAULT 7
  
@@ -55,6 +48,10 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
+static void post_code(u8 value) {
+    outb(value, 0x80);
+}
+
 #if USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
@@ -64,17 +61,16 @@
 #endif
 #include "ram/ramtest.c"
 
-#include <cpu/amd/model_fxx_rev.h>
+#include <cpu/amd/model_10xxx_rev.h>
 
 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
+#include "northbridge/amd/amdfam10/raminit.h"
+#include "northbridge/amd/amdfam10/amdfam10.h"
 
 #endif
 
 #include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
+#include "northbridge/amd/amdfam10/reset_test.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
 
@@ -86,11 +82,11 @@
         #include "lib/memcpy.c"
 #endif
 
-#include "northbridge/amd/amdk8/debug.c"
+#include "northbridge/amd/amdfam10/debug.c"
 
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
 
-#include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "northbridge/amd/amdfam10/setup_resource_map.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
@@ -114,18 +110,17 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/amd/amdk8/amdk8_f.h"
-#include "northbridge/amd/amdk8/coherent_ht.c"
+#include "northbridge/amd/amdfam10/amdfam10.h"
+#include "northbridge/amd/amdht/ht_wrapper.c"
 
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-
-#include "northbridge/amd/amdk8/raminit_f.c"
-
-#include "sdram/generic_sdram.c"
+#include "include/cpu/x86/mem.h"
+#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
+#include "northbridge/amd/amdfam10/raminit_amdmct.c"
+#include "northbridge/amd/amdfam10/amdfam10_pci.c"
 
 #include "resourcemap.c" 
 
-#include "cpu/amd/dualcore/dualcore.c"
+#include "cpu/amd/quadcore/quadcore.c"
 
 #define MCP55_NUM 1
 #define MCP55_USE_NIC 1
@@ -147,16 +142,16 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 
-#include "cpu/amd/model_fxx/init_cpus.c"
+#include "cpu/amd/model_10xxx/init_cpus.c"
 
-#include "cpu/amd/model_fxx/fidvid.c"
+#include "cpu/amd/model_10xxx/fidvid.c"
 
 #endif
 
 #if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
 
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
+#include "northbridge/amd/amdfam10/early_ht.c"
 
 
 static void sio_setup(void)
@@ -197,6 +192,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
         /* Nothing special needs to be done to find bus 0 */
         /* Allow the HT devices to be found */
 
+        set_bsp_node_CHtExtNodeCfgEn();
         enumerate_ht_chain();
 
         sio_setup();
@@ -250,116 +246,161 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 }
 
 #if USE_FAILOVER_IMAGE==0
+#include "spd_addr.h"
+#include "cpu/amd/microcode/microcode.c"
+#include "cpu/amd/model_10xxx/update_microcode.c"
 
 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	static const uint16_t spd_addr [] = {
-			(0xa<<3)|0, (0xa<<3)|2, 0, 0,
-			(0xa<<3)|1, (0xa<<3)|3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
-			(0xa<<3)|4, (0xa<<3)|6, 0, 0,
-			(0xa<<3)|5, (0xa<<3)|7, 0, 0,
-#endif
-	};
+        struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
 
-        struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
-
-        int needs_reset = 0;
-        unsigned bsp_apicid = 0;
+	u32 bsp_apicid = 0;
+	u32 val;
+	msr_t msr;
+ 
+	post_code(0x30);
 
         if (bist == 0) {
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
         }
 
-	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
-
-        setup_mb_resource_map();
+	post_code(0x32);
 
+	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
         uart_init();
-	
+        console_init();
+	printk_debug("\n");
+
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
-
 #if CONFIG_USBDEBUG_DIRECT
 	mcp55_enable_usbdebug_direct(DBGP_DEFAULT);
 	early_usbdebug_direct_init();
 #endif
-        console_init();
-        print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
 
-        print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+	val = cpuid_eax(1);
+	printk_debug("BSP Family_Model: %08x \n", val);
+	printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
+	printk_debug("bsp_apicid = %02x \n", bsp_apicid);
+	printk_debug("cpu_init_detectedx = %08x \n", cpu_init_detectedx);
 
-#if MEM_TRAIN_SEQ == 1
-        set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
-#endif
-        setup_coherent_ht_domain(); // routing table and start other core0
 
-        wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
-        // It is said that we should start core1 after all core0 launched
-        /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
-         * So here need to make sure last core0 is started, esp for two way system,
-         * (there may be apic id conflicts in that case)
-         */
-        start_other_cores();
-        wait_all_other_cores_started(bsp_apicid);
-#endif
+	/* Setup sysinfo defaults */
+	set_sysinfo_in_ram(0);
 
-        /* it will set up chains and store link pair for optimization later */
-        ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
+	update_microcode(val);
+	post_code(0x33);
 
-#if K8_SET_FIDVID == 1
+	cpuSetAMDMSR();
+	post_code(0x34);
 
-        {
-                msr_t msr;
-                msr=rdmsr(0xc0010042);
-                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+	amd_ht_init(sysinfo);
+	post_code(0x35);
 
-        }
+	/* Setup nodes PCI space and start core 0 AP init. */
+	finalize_node_setup(sysinfo);
 
-        enable_fid_change();
+	/* Setup any mainboard PCI settings etc. */
+	setup_mb_resource_map();
+	post_code(0x36);
 
-        enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
+	/* wait for all the APs core0 started by finalize_node_setup. */
+	/* FIXME: A bunch of cores are going to start output to serial at once.
+	   It would be nice to fixup prink spinlocks for ROM XIP mode.
+	   I think it could be done by putting the spinlock flag in the cache
+	   of the BSP located right after sysinfo.
+	 */
+	wait_all_core0_started();
 
-        init_fidvid_bsp(bsp_apicid);
+#if CONFIG_LOGICAL_CPUS==1
+	/* Core0 on each node is configured. Now setup any additional cores. */
+	printk_debug("start_other_cores()\n");
+	start_other_cores();
+	post_code(0x37);
+	wait_all_other_cores_started(bsp_apicid);
+#endif
 
-        // show final fid and vid
-        {
-                msr_t msr;
-                msr=rdmsr(0xc0010042);
-                print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+	post_code(0x38);
 
-        }
+#if FAM10_SET_FIDVID == 1
+	msr = rdmsr(0xc0010071);
+	printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+
+	/* FIXME: The sb fid change may survive the warm reset and only
+	   need to be done once.*/
+	enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
+
+	post_code(0x39);
+
+	if (!warm_reset_detect(0)) {			// BSP is node 0
+		init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
+	} else {
+		init_fidvid_stage2(bsp_apicid, 0);	// BSP is node 0
+	}
+
+	post_code(0x3A);
+
+	/* show final fid and vid */
+	msr=rdmsr(0xc0010071);
+	printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 #endif
 
-        needs_reset |= optimize_link_coherent_ht();
-        needs_reset |= optimize_link_incoherent_ht(sysinfo);
-        needs_reset |= mcp55_early_setup_x();
+        /* FIXME: IS this required? needs_reset |= mcp55_early_setup_x(); */
 
-        // fidvid change will issue one LDTSTOP and the HT change will be effective too
-        if (needs_reset) {
-                print_info("ht reset -\r\n");
-              	soft_reset();
-        }
+	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
+	if (!warm_reset_detect(0)) {
+		print_info("...WARM RESET...\n\n\n");
+		soft_reset();
+		die("After soft_reset_x - shouldn't see this message!!!\n");
+	}
+
+	post_code(0x3B);
 
-        allow_all_aps_stop(bsp_apicid);
+	/* FIXME:  Move this to chipset init.
+	enable cf9 for hard reset */
+	print_debug("enable_cf9_x()\n");
+	/* FIXME: enable_cf9_x(sysinfo->sbbusn, sysinfo->sbdn); */
+	post_code(0x3C);
 
-        //It's the time to set ctrl in sysinfo now;
+	/* It's the time to set ctrl in sysinfo now; */
+	printk_debug("fill_mem_ctrl()\n");
 	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+	post_code(0x3D);
+
+
+	printk_debug("enable_smbus()\n");
+	enable_smbus();
+	post_code(0x3E);
+
 
-        enable_smbus(); 
+	memreset_setup();
+	post_code(0x40);
 
-        memreset_setup();
+//	die("Die Before MCT init.");
+
+	printk_debug("raminit_amdmct()\n");
+	raminit_amdmct(sysinfo);
+	post_code(0x41);
+
+
+/*
+	dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
+	dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
+	dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
+	dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
+*/
 
-        //do we need apci timer, tsc...., only debug need it for better output
-        /* all ap stopped? */
-//        init_timer(); // Need to use TMICT to synconize FID/VID
+//	ram_check(0x00200000, 0x00200000 + (640 * 1024));
+//	ram_check(0x40200000, 0x40200000 + (640 * 1024));
 
-        sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 
-        post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+//	die("After MCT init before CAR disabled.");
 
+	post_code(0x42);
+	printk_debug("\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
+	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
+	post_code(0x43);	// Should never see this post code.
 }
 
 
diff --git a/src/mainboard/tyan/s2912_fam10/chip.h b/src/mainboard/tyan/s2912_fam10/chip.h
index a34af2c..f34d17c 100644
--- a/src/mainboard/tyan/s2912_fam10/chip.h
+++ b/src/mainboard/tyan/s2912_fam10/chip.h
@@ -19,9 +19,9 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-extern struct chip_operations mainboard_tyan_s2912_ops;
+extern struct chip_operations mainboard_tyan_s2912_fam10_ops;
 
-struct mainboard_tyan_s2912_config {
+struct mainboard_tyan_s2912_fam10_config {
 //	int fixup_scsi;
 //	int fixup_vga;
 };
diff --git a/src/mainboard/tyan/s2912_fam10/cmos.layout b/src/mainboard/tyan/s2912_fam10/cmos.layout
index 0621cfc..2a147e2 100644
--- a/src/mainboard/tyan/s2912_fam10/cmos.layout
+++ b/src/mainboard/tyan/s2912_fam10/cmos.layout
@@ -53,7 +53,7 @@ entries
 395          1       e       1        hw_scrubber
 396          1       e       1        interleave_chip_selects
 397          2       e       8        max_mem_clock
-399	     1	     e	     2	      dual_core
+399	     1	     e	     2	      quad_core
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
diff --git a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c
index 7bb5f76..557e511 100644
--- a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c
+++ b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c
@@ -28,67 +28,43 @@
 #include <cpu/amd/dualcore.h>
 #endif
 
-#include <cpu/amd/amdk8_sysconf.h>
+#include <cpu/amd/amdfam10_sysconf.h>
 
 #include "mb_sysconf.h"
 
 // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
 struct mb_sysconf_t mb_sysconf;
 
-unsigned pci1234x[] = 
-{        //Here you only need to set value in pci1234 for HT-IO that could be installed or not
-	 //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
-        0x0000ff0,
-        0x0000ff0,
-        0x0000ff0,
-//        0x0000ff0,
-//        0x0000ff0,
-//        0x0000ff0,
-//        0x0000ff0,
-//        0x0000ff0
+/* Here you only need to set value in pci1234 for HT-IO that could be
+installed or not You may need to preset pci1234 for HTIO board, please
+refer to src/northbridge/amd/amdfam10/get_pci1234.c for detail */
+static u32 pci1234x[] = {
+	0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc,
+	0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc,
+	0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc,
+	0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc,
+	0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc,
+	0x0000ffc, 0x0000ffc,
+	};
+
+
+/* HT Chain device num, actually it is unit id base of every ht device
+in chain, assume every chain only have 4 ht device at most */
+
+static unsigned hcdnx[] = {
+	0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
+	0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
+	0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
+	0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
+	0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
+	0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
+	0x20202020, 0x20202020,
 };
-unsigned hcdnx[] = 
-{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
-	0x20202020,
-	0x20202020,
-        0x20202020,
-//        0x20202020,
-//        0x20202020,
-//        0x20202020,
-//        0x20202020,
-//        0x20202020,
-};
-
 
-extern void get_sblk_pci1234(void);
+extern void get_pci1234(void);
 
 static unsigned get_bus_conf_done = 0;
 
-static unsigned get_hcid(unsigned i)
-{
-        unsigned id = 0;
-
-        unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
-
-        unsigned devn = sysconf.hcdn[i] & 0xff;
-
-        device_t dev;
-
-        dev = dev_find_slot(busn, PCI_DEVFN(devn,0));
-
-        switch (dev->device) {
-        case 0x0369: //IO55
-                id = 4;
-                break;
-        }
-
-        // we may need more way to find out hcid: subsystem id? GPIO read ?
-
-        // we need use id for 1. bus num, 2. mptable, 3. acpi table
-
-        return id;
-}
-
 void get_bus_conf(void)
 {
 
@@ -113,13 +89,11 @@ void get_bus_conf(void)
                 sysconf.hcdn[i] = hcdnx[i];
         }
 
-        get_sblk_pci1234();
-
-	sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
+        get_pci1234();
 
 	m->bus_type[0] = 1; //pci
-	
-	m->bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff;
+	sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
+	m->bus_mcp55[0] = (sysconf.pci1234[0] >> 12) & 0xff;
 
                 /* MCP55 */
                 dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0));
@@ -143,8 +117,8 @@ void get_bus_conf(void)
 	for(i=0; i< sysconf.hc_possible_num; i++) {
 		if(!(sysconf.pci1234[i] & 0x1) ) continue;
 
-                unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
-                unsigned busn_max = (sysconf.pci1234[i] >> 24) & 0xff;
+                unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff;
+                unsigned busn_max = (sysconf.pci1234[i] >> 20) & 0xff;
 		for (j = busn; j <= busn_max; j++) 
 			m->bus_type[j] = 1;
 		if(m->bus_isa <= busn_max) 
diff --git a/src/mainboard/tyan/s2912_fam10/irq_tables.c b/src/mainboard/tyan/s2912_fam10/irq_tables.c
index c79f0ca..2640837 100644
--- a/src/mainboard/tyan/s2912_fam10/irq_tables.c
+++ b/src/mainboard/tyan/s2912_fam10/irq_tables.c
@@ -31,7 +31,7 @@
 #include <stdint.h>
 #include <arch/pirq_routing.h>
 
-#include <cpu/amd/amdk8_sysconf.h>
+#include <cpu/amd/amdfam10_sysconf.h>
 #include "mb_sysconf.h"
 
 static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, 
@@ -102,13 +102,22 @@ unsigned long write_pirq_routing_table(unsigned long addr)
         
         for(i=1; i< sysconf.hc_possible_num; i++) {
                 if(!(sysconf.pci1234[i] & 0x1) ) continue;
-                unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
+                unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff;
                 unsigned devn = sysconf.hcdn[i] & 0xff;
 
                 write_pirq_info(pirq_info, busn, (devn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
                 pirq_info++; slot_num++;
 	}
 
+#if CBB
+	write_pirq_info(pirq_info, CBB, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+	pirq_info++; slot_num++;
+	if(sysconf.nodes>32) {
+		write_pirq_info(pirq_info, CBB-1, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+		pirq_info++; slot_num++;
+	}
+#endif
+
 	pirq->size = 32 + 16 * slot_num; 
 
         for (i = 0; i < pirq->size; i++)
diff --git a/src/mainboard/tyan/s2912_fam10/mainboard.c b/src/mainboard/tyan/s2912_fam10/mainboard.c
index 7144580..4ceb052 100644
--- a/src/mainboard/tyan/s2912_fam10/mainboard.c
+++ b/src/mainboard/tyan/s2912_fam10/mainboard.c
@@ -27,7 +27,7 @@
 #include "chip.h"
 
 #if CONFIG_CHIP_NAME == 1
-struct chip_operations mainboard_tyan_s2912_ops = {
-	CHIP_NAME("Tyan S2912 Mainboard")
+struct chip_operations mainboard_tyan_s2912_fam10_ops = {
+	CHIP_NAME("Tyan S2912 Mainboard (Family 10)")
 };
 #endif
diff --git a/src/mainboard/tyan/s2912_fam10/mptable.c b/src/mainboard/tyan/s2912_fam10/mptable.c
index 236f778..dba25b4 100644
--- a/src/mainboard/tyan/s2912_fam10/mptable.c
+++ b/src/mainboard/tyan/s2912_fam10/mptable.c
@@ -25,7 +25,7 @@
 #include <string.h>
 #include <stdint.h>
 
-#include <cpu/amd/amdk8_sysconf.h>
+#include <cpu/amd/amdfam10_sysconf.h>
 
 #include "mb_sysconf.h"
 
diff --git a/src/mainboard/tyan/s2912_fam10/resourcemap.c b/src/mainboard/tyan/s2912_fam10/resourcemap.c
index 4801643..cb135a3 100644
--- a/src/mainboard/tyan/s2912_fam10/resourcemap.c
+++ b/src/mainboard/tyan/s2912_fam10/resourcemap.c
@@ -49,14 +49,14 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the upper address bits of a 40 bit  address
 		 *	   that define the end of the DRAM region.
 		 */
-		PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
-		PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
-		PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
-		PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
-		PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
-		PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
-		PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
+		// PCI_ADDR(CBB, CDB, 1, 0x44), 0x0000f8f8, 0x00000000,
+		PCI_ADDR(CBB, CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
+		PCI_ADDR(CBB, CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
+		PCI_ADDR(CBB, CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
+		PCI_ADDR(CBB, CDB, 1, 0x64), 0x0000f8f8, 0x00000004,
+		PCI_ADDR(CBB, CDB, 1, 0x6C), 0x0000f8f8, 0x00000005,
+		PCI_ADDR(CBB, CDB, 1, 0x74), 0x0000f8f8, 0x00000006,
+		PCI_ADDR(CBB, CDB, 1, 0x7C), 0x0000f8f8, 0x00000007,
 
 		/* DRAM Base i Registers
 		 * F1:0x40 i = 0
@@ -88,14 +88,14 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the upper address bits of a 40-bit address
 		 *	   that define the start of the DRAM region.
 		 */
-		PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
+		// PCI_ADDR(CBB, CDB, 1, 0x40), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CBB, CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CBB, CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CBB, CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CBB, CDB, 1, 0x60), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CBB, CDB, 1, 0x68), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CBB, CDB, 1, 0x70), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CBB, CDB, 1, 0x78), 0x0000f8fc, 0x00000000,
 
 		/* Memory-Mapped I/O Limit i Registers
 		 * F1:0x84 i = 0
@@ -129,14 +129,14 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the upp adddress bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
-		PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
-//		PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
+		PCI_ADDR(CBB, CDB, 1, 0x84), 0x00000048, 0x00000000,
+		PCI_ADDR(CBB, CDB, 1, 0x8C), 0x00000048, 0x00000000,
+		PCI_ADDR(CBB, CDB, 1, 0x94), 0x00000048, 0x00000000,
+		PCI_ADDR(CBB, CDB, 1, 0x9C), 0x00000048, 0x00000000,
+		PCI_ADDR(CBB, CDB, 1, 0xA4), 0x00000048, 0x00000000,
+		PCI_ADDR(CBB, CDB, 1, 0xAC), 0x00000048, 0x00000000,
+		PCI_ADDR(CBB, CDB, 1, 0xB4), 0x00000048, 0x00000000,
+//		PCI_ADDR(CBB, CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
 
 		/* Memory-Mapped I/O Base i Registers
 		 * F1:0x80 i = 0
@@ -164,14 +164,14 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the upper address bits of a 40bit address 
 		 *	   that defines the start of memory-mapped I/O region i
 		 */
-		PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
-//		PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
+		PCI_ADDR(CBB, CDB, 1, 0x80), 0x000000f0, 0x00000000,
+		PCI_ADDR(CBB, CDB, 1, 0x88), 0x000000f0, 0x00000000,
+		PCI_ADDR(CBB, CDB, 1, 0x90), 0x000000f0, 0x00000000,
+		PCI_ADDR(CBB, CDB, 1, 0x98), 0x000000f0, 0x00000000,
+		PCI_ADDR(CBB, CDB, 1, 0xA0), 0x000000f0, 0x00000000,
+		PCI_ADDR(CBB, CDB, 1, 0xA8), 0x000000f0, 0x00000000,
+		PCI_ADDR(CBB, CDB, 1, 0xB0), 0x000000f0, 0x00000000,
+//		PCI_ADDR(CBB, CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
 
 		/* PCI I/O Limit i Registers
 		 * F1:0xC4 i = 0
@@ -198,10 +198,10 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the end of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-//		PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000,
-//		PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x01fff020, // need to talk to ANALOG of second CK804 to release PCI E reset
-		PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
+//		PCI_ADDR(CBB, CDB, 1, 0xC4), 0xFE000FC8, 0x00007000,
+//		PCI_ADDR(CBB, CDB, 1, 0xCC), 0xFE000FC8, 0x01fff020, // need to talk to ANALOG of second CK804 to release PCI E reset
+		PCI_ADDR(CBB, CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
+		PCI_ADDR(CBB, CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
 
 		/* PCI I/O Base i Registers
 		 * F1:0xC0 i = 0
@@ -228,10 +228,10 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the start of PCI I/O region n 
 		 * [31:25] Reserved
 		 */
-//		PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
-//		PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00008033,
-		PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
+//		PCI_ADDR(CBB, CDB, 1, 0xC0), 0xFE000FCC, 0x00000033,
+//		PCI_ADDR(CBB, CDB, 1, 0xC8), 0xFE000FCC, 0x00008033,
+		PCI_ADDR(CBB, CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
+		PCI_ADDR(CBB, CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
 
 		/* Config Base and Limit i Registers
 		 * F1:0xE0 i = 0
@@ -269,10 +269,10 @@ static void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration region i
 		 */
-//		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */
-//		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of cpu 0 --> nvidia io55 	*/
-		PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, 
+//		PCI_ADDR(CBB, CDB, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */
+//		PCI_ADDR(CBB, CDB, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of cpu 0 --> nvidia io55 	*/
+		PCI_ADDR(CBB, CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
+		PCI_ADDR(CBB, CDB, 1, 0xEC), 0x0000FC88, 0x00000000, 
 
 	};
 
diff --git a/targets/tyan/s2912_fam10/Config-abuild.lb b/targets/tyan/s2912_fam10/Config-abuild.lb
index fc53090..af03fc6 100644
--- a/targets/tyan/s2912_fam10/Config-abuild.lb
+++ b/targets/tyan/s2912_fam10/Config-abuild.lb
@@ -18,25 +18,25 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-target tyan_s2912
-mainboard tyan/s2912
+target tyan_s2912_fam10
+mainboard tyan/s2912_fam10
 
 __COMPRESSION__
 
-romimage "normal"
+romimage "fallback"
 	option USE_FALLBACK_IMAGE=0
-	option ROM_IMAGE_SIZE=0x20000
+	option ROM_IMAGE_SIZE=0x3f0000
 	option XIP_ROM_SIZE=0x40000
-	option COREBOOT_EXTRA_VERSION=".0-Normal"
+	option COREBOOT_EXTRA_VERSION=".0-fallback"
 	payload __PAYLOAD__
 end
 
-romimage "fallback" 
+romimage "failover" 
 	option USE_FALLBACK_IMAGE=1
-	option ROM_IMAGE_SIZE=0x20000
+	option ROM_IMAGE_SIZE=0x3f0000
 	option XIP_ROM_SIZE=0x40000
-	option COREBOOT_EXTRA_VERSION=".0-Fallback"
+	option COREBOOT_EXTRA_VERSION=".0-failover"
 	payload __PAYLOAD__
 end
 
-buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom ROM_SIZE "fallback" "failover"
diff --git a/targets/tyan/s2912_fam10/Config.lb b/targets/tyan/s2912_fam10/Config.lb
index 28deabc..08c797b 100644
--- a/targets/tyan/s2912_fam10/Config.lb
+++ b/targets/tyan/s2912_fam10/Config.lb
@@ -21,8 +21,14 @@
 
 # Sample config file for s2912
 
-target s2912
-mainboard tyan/s2912
+target s2912_fam10
+mainboard tyan/s2912_fam10
+
+option DEFAULT_CONSOLE_LOGLEVEL = 8
+
+# option ROM_SIZE=512 * 1024
+option ROM_SIZE=(512-44)*1024
+option FALLBACK_SIZE=ROM_SIZE-0x1000
 
 # serengeti_leopard
 romimage "normal"
@@ -34,11 +40,12 @@ romimage "normal"
 #        option ROM_SIZE = 458752 
 #       44k for atixx.rom
 #        option ROM_SIZE = 479232
+#	option ROM_SIZE=((512*1024)-(44*1024))
         option USE_FAILOVER_IMAGE=0
 	option USE_FALLBACK_IMAGE=0
 #	option ROM_IMAGE_SIZE=0x13800
 #	option ROM_IMAGE_SIZE=0x18800
-	option ROM_IMAGE_SIZE=0x20000
+	option ROM_IMAGE_SIZE=0x30000
 #	option ROM_IMAGE_SIZE=0x15800
 	option XIP_ROM_SIZE=0x40000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
@@ -52,13 +59,14 @@ romimage "normal"
 #	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
 #	payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf
 #	payload ../../../../payloads/forcedeth--filo_hda2_vga.zelf
-	payload ../../../../payloads/forcedeth--filo_hda2_vga_5_4_2_mcp55.zelf
+###	payload ../../../../payloads/forcedeth--filo_hda2_vga_5_4_2_mcp55.zelf
 #	payload ../../../payloads/tg3_com2.zelf
 #       payload ../../../payloads/e1000--filo.zelf
 #        payload ../../../payloads/tg3--e1000--filo.zelf
 #        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
 #	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
 #	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
+	payload /home/argggh/src/filo/filo-0.5/filo.elf
 end
 
 romimage "fallback" 
@@ -68,7 +76,7 @@ romimage "fallback"
 #	option ROM_IMAGE_SIZE=0x19800
 	option ROM_IMAGE_SIZE=0x20000
 #	option ROM_IMAGE_SIZE=0x15800
-	option XIP_ROM_SIZE=0x40000
+	option XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 #       payload ../../../payloads/tg3--ide_disk.zelf
 #        payload ../../../payloads/filo.elf
@@ -84,7 +92,7 @@ romimage "fallback"
 #	payload ../../../../payloads/adlo.elf
 #	payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf
 #	payload ../../../../payloads/forcedeth_mcp55_filo_hda2.zelf
-	payload ../../../../payloads/forcedeth--filo_hda2_vga_5_4_2_mcp55.zelf
+###	payload ../../../../payloads/forcedeth--filo_hda2_vga_5_4_2_mcp55.zelf
 #	payload ../../../../payloads/forcedeth--filo_hda2_vga.zelf
 #	payload ../../../payloads/tg3_com2.zelf
 #       payload ../../../payloads/e1000--filo.zelf
@@ -92,6 +100,7 @@ romimage "fallback"
 #        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
 #	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
 #	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
+	payload /home/argggh/src/filo/filo-0.5/filo.elf
 end
 
 romimage "failover"
@@ -102,5 +111,5 @@ romimage "failover"
         option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
 end
 
-#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
-buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
+#buildrom ./coreboot.rom ROM_SIZE "normal" "failover"
+buildrom ./coreboot.rom ROM_SIZE "fallback" "failover"
diff --git a/targets/tyan/s2912_fam10/VERSION b/targets/tyan/s2912_fam10/VERSION
deleted file mode 100644
index 202f8ca..0000000
--- a/targets/tyan/s2912_fam10/VERSION
+++ /dev/null
@@ -1 +0,0 @@
-_s2912
