coreboot-2.0.0_Fallback ti. 12. aug. 13:51:54 +0200 2008 starting... BSP Family_Model: 00100f23 *sysinfo range: [000cc000,000cdfa0] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: equivalent rev id = 0x1022, current patch id = 0x00000000 microcode: patch id to apply = 0x01000083 microcode: updated to patch id = 0x01000083 success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify() event class: 05 event: 1004 data: 04 00 00 01 AMD_CB_ManualBUIDSwapList() AMD_CB_EventNotify() event class: 05 event: 2006 data: 04 00 02 ff Exit amd_ht_init() cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done Prep FID/VID Node:00 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c3310f24 F3xD8: 03001515 F3xDC: 00005428 Prep FID/VID Node:01 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c3310f24 F3xD8: 03001515 F3xDC: 00005428 setup_remote_node: 01 done Start node 01 done. Wait all core0s started core0: --- { APICID = 04 NODEID = 01 COREID = 00} --- mi Ccorroceo0d set: aerqteudi vaolne nnotd ree:v 0 1id Wa=i t0x 1a0ll2 2c, ocreu0rrse sntta prattedc hd iodn e= 0sxta0r0t00_0ot0h0e0r _coresm(i)cro cionidte : npoadet:c h 00i d tcoo reaspp:l y03 = 0 xS0ta1r0t00 0o8th3e rm icocrreoc o-d neo:d uepidd:a te0d0 toc opreast:ch 0i3d =i n0ixt0 1n0o00de08:3 0s1u c cceosrses : 03c puS eSttAaMrDtM SoRt her cor ed o-n eno deiniid t : _ ccco0oofir1rrdee evxx xi:::cdo _r ae---p-s--(--:-s {{{0ta 3 g eAAA 1PPPstIII)CaCC aIrIIpDtDDi e c=d==i dap:000 0132a4 pNNN iOOOFcDDDIiEEEDdIIIV:DDDI D=== 0o000n00 CCACOOPORR:R EEEIII04DDD === 000123}}} --- --- c-cc--ooor rr eeeAxxxmmm::P: iii cscc -r-trr--o-o-ao-rc-c-c o to o{d{d{eded e e ::: : A A APe0PePeIqIq1IqCuCuCuAPiIiIiIDv vDvD a asa =tl=l=l e ae ennrntttt000 56 e7 drr rNeN:eeNOvvOvO D0D D EiE2EiiddIdIAIDP D D ======s t 000a000xx1x1r1 t11 1 C0CCe00O222OOdR:R222RE,E E,, I I0ID3DccDc u uu===rrr rr ree00e01n2n3n}tt}t} -pp--p-aa--att--t-ccc hh h AiiimPmmidddii csc cr=rtr== o oaocr00c0coxootxxd000ddeede000e:0:::0000 0 e000e0eq0qq500u000uuAiPi000ivv v a asaltlleeeannrnttttmmem riiirrde:ecccevrrv vr o oo 0i6iciccoodAdod ddd P eee =::=s=: t0a0p0ppaaxrxax1ttt1t10e0ccc022d2hhh2 2:2, ,,iii dd0 dc c 7cuututtoo orrrr r ree aeaappnnBpnpetpptt lg llyyppyipan aa t=t ==tc c cFhIh00h0 x D xx00i0iVidI11d1d 0 D00 =00=0= M 00 0000S00088x8xRx0 3303000000 0 0x0c0mm0m0i000iicc0c00001rr0r00o000ooccc0 7 ooo d1dd eee:::0 xmmmii2uuuicpcc8pprdddrrao8oaaaoctc0cttoeeoeo0dcddddde e4e tt:t: : 0oo o p ppx apppaa3t0taaatctc0cttccc4hhh 5 hhh i i0i iidid4d 4 dd dt t t ==o=oo a0a0a0FpxxpIxpp0p00pDlVl1l1100yIy0y 0 00 D= =0=0000 o 0 08880n0x x333x0 0B0 1 1 1S0P0ss0s0u0,0uucc0c0 00Acc0c08e8Pee83ss3s3ICsss _ m mimidiic cc: rrr cccpppoo0oc0uuuccoooSSSdeedd eettteeB:::AAASMM MP u DDuuDpMpfMMpdSdSdiSadRaRaRt t t eee=dd d 1tt0tooo5 0 pddp0pdaoaooatn tntncececeWhahh i tiiiiiidndnd nif i i =tto=t= _ __r0f f00fxixiAix0d0d0dP v1v1v10i0si0i0d0d0td_a0_0_00aag0a08p8ppe83 3(3(( ss 1 s :ttts saasaugguaugceceecpc_c1c11))eae)es spssissaaappcp i iii dcccii i ddd=cccp :::ppuuu1 S00SS0e 1e32etttA A A MFFMFMIIDIDDMDDMMDVVSSVSRIRIRI DD D ooonnn AAAPPP d:::dd ooo00nnn0e3ee12 iiinnniii trtt__e_faffiiiddbddvvvaiciiddkd_ __aaa=p pp(((1s0sst1tta0aagg5ge0ee1111))) a aapppcioiicccmimiiddod:n:: _0f00675id (FpFFIIIaDcDDVVkVIeIIDDDd ) ooo n=nn A1AAPPP0:5:: 0 0000567 Wait for AP stage 1: ap_apicid = 2 readback = 2010501 common_fid(packed) = 10500 Wait for AP stage 1: ap_apicid = 3 readback = 3010501 common_fid(packed) = 10500 Wait for AP stage 1: ap_apicid = 4 readback = 4010501 common_fid(packed) = 10500 Wait for AP stage 1: ap_apicid = 5 readback = 5010501 common_fid(packed) = 10500 Wait for AP stage 1: ap_apicid = 6 readback = 6010501 common_fid(packed) = 10500 Wait for AP stage 1: ap_apicid = 7 readback = 7010501 common_fid(packed) = 10500 common_fid = 10500 FID Change Node:00, F3xD4: c3310f25 FID Change Node:01, F3xD4: c3310f25 End FIDVIDMSR 0xc0010071 0x28a800c4 0x30045044 ...WARM RESET... coreboot-2.0.0_Fallback ti. 12. aug. 13:51:54 +0200 2008 starting... BSP Family_Model: 00100f23 *sysinfo range: [000cc000,000cdfa0] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: equivalent rev id = 0x1022, current patch id = 0x00000000 microcode: patch id to apply = 0x01000083 microcode: updated to patch id = 0x01000083 success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify() event class: 05 event: 1004 data: 04 00 00 01 AMD_CB_ManualBUIDSwapList() AMD_CB_EventNotify() event class: 05 event: 2006 data: 04 00 02 ff Exit amd_ht_init() cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done Prep FID/VID Node:00 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c3310f25 F3xD8: 03001515 F3xDC: 00005428 Prep FID/VID Node:01 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c3310f25 F3xD8: 03001515 F3xDC: 00005428 setup_remote_node: 01 done Start node 01 done. Wait all core0s started Core0 started cono ren0o:de : --0-1 {W a AiPtI aClIlD =c ore040 sN sOtDaEIrDt ed= d0o1 nCeO RsEtIaDr =t _0ot0h}e -r-_-cor es(m)icr oicnoitd en: oedqe:u i0va0l e cnotr reesv: 0i3d = S t0ax1r0t2 o2t,h ceur rcroenrte -p antcohd eiidd: = 000x 0c0o00r0e0s:0 00 3 inimti cnroocdeod:e :0 1p a tccorh esid: t0o3 ap pSltya r=t 0oxt0h1e0r0 0co08r3e -m incodroeciodd: ccce:o0oo r1rrue eepx xxc:::d o art ---ee---sd---: to{{0{ 3 p aAA APPPtsItcIIaChrICC tDIIie DDdd= ===a p00 200xa 31 0pNNN1iOOO0cDDD0iEEE0dIII0:DDD8 3= == 0s000u00 cC CCcOeROORRsEsEEIIDI DD = = =0 c020p3u1}S} }e -t---A--- c-ccM-D ooorM r rmeeeSAxxRximm:i :icP:rc c rosr -ooct -oad--cc--oo-droten- dd-{ee e:e d{ ::{ e: q Aee iu0nAPqqAIuuPi1iPAvtICiiIIvvCPa_CflIDaaI llDsieD dn =ee tnn=avt= i ttr0dtr6 _rree0 05dvN7see tvv : Oi DNa NgiiOd0EO2 IDeddD2 EA DE=P I Ia==D =Ds0 p 00=tx0=i11 cxx a110r 00iC21d001t22 eO2 :R,C 22CdO,:E O0,Rc4 R IEc0DEucI uIu3 rDrD=rr er r=en=e0 tn2 n}t0t0 1p 3 -p}p}a a t-a-c-tt--ch-c -h-h i id midd iA =mcmP= = iric s 0cor0t0xrcooxax0ocdc0r00oeo0t00d0:d0e0e00 e0d::00e:0 00q 0e0000ueqq050ivuuA aii P lvv seaamntllitaemmriniec rtctcnreoer rtvcdoro r o:ceceoid ovvdde0d i e :6ed:i: A P d =p p p a=tsa a0x ctt=t1c0 achr0x0 hh2t1 xi 2e0i1di,dd2d0 t :2 2cot ,t2,u o0 o a7crucarapp upeprnprlprr tlleyeB yyn n=ep t t ga==p 0it a0pxnc0txxa0 h c00t1Fih11c0IdD 00h0 0Vi00 =0Id00id 8D 00 803 =8=33xM 0 S0x0 0mR0 xmm0i0c00ii00rx0cc000oc0rr0o0c00o0c0o00coo0d100 dd0e000ee:7 :: mi u 1p cuudrpmp0odidaxmi2cacatce8otrtredadeocod 8edoc t0: dtoto0 peodo ca: e p4t p:pact0pa axcatpthacc 3htcthhi0 c d0ih 4d iihddt5 i i o0=dd== 4 t a40oxt00p 0oxxpa 1 00lyp0a11p00 p0Ep0n00=lyl0d00 0 y8 00x= 3F8803 = I31 0 D0V x0s0Iss0xu0cDuu1010cMcc0008eScc003sRee0s0s s8ss0 038m xc 3i 0crm 0 cmp1oicciu0cppcrcS0ouuoSre7dSceot1eeottcA : dAAoM0uxeMMdDp2:DDeMdS8 MM: aRauSSut 8pRRp ed0 a0dda tce4ttd eo d 0 pd dxdtaotoo3ootn en0n cpe0eph a 0atit 3 idccn0iihhi0nn = t4ii ii_ tt0_ddf_xff i 0ii==dendd v1vav00i00ibixxd0_dld0010s_e_108ts_s0003atct0a0 gaf0g0 eg98_e8s2e32x23u a ( c pa)a cesippsusuci iccscicfiicdicdl e:des:ls :s _ s0200mcp1e 3um S _ ecccptturpASluMe(SeDt)AtMSMA RDMe nMDSaMRbS lRe d_osnmeb ud sd(o o)ninenie t _ rifnaiinimdiit_vntfii_fidti_d_davstvmidaid_gdmsce_tt2sta( aag)pgei e2 c2r aaiampd:piic ini0cidt6id:_: a 0m0d57mc t begin: mctAutoInitMCT_D: mct_init Node 00000000 mctAutoInitMCT_D: clear_legacy_Mode mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: Set Cl, Wb mctAutoInitMCT_D: mctSMBhub_Init mctAutoInitMCT_D: mct_initDCT mct_initDCT: DCTInit_D 0 DIMMPresence: i=00000000 DIMMPresence: smbaddr=00000050 DIMMPresence: i=00000001 DIMMPresence: smbaddr=00000051 DIMMPresence: i=00000002 DIMMPresence: smbaddr=00000052 DIMMPresence: i=00000003 DIMMPresence: smbaddr=00000053 DIMMPresence: i=00000004 DIMMPresence: smbaddr=00000000 DIMMPresence: i=00000005 DIMMPresence: smbaddr=00000000 DIMMPresence: i=00000006 DIMMPresence: smbaddr=00000000 DIMMPresence: i=00000007 DIMMPresence: smbaddr=00000000 DIMMPresence: DIMMValid=0000000c DIMMPresence: DIMMPresent=0000000c DIMMPresence: RegDIMMPresent=0000000c DIMMPresence: DimmECCPresent=0000000c DIMMPresence: DimmPARPresent=00000000 DIMMPresence: Dimmx4Present=00000000 DIMMPresence: Dimmx8Present=0000000c DIMMPresence: Dimmx16Present=00000000 DIMMPresence: DimmPlPresent=0000000c DIMMPresence: DimmDRPresent=00000000 DIMMPresence: DimmQRPresent=00000000 DIMMPresence: DATAload[0]=00000001 DIMMPresence: MAload[0]=00000008 DIMMPresence: MAdimms[0]=00000001 DIMMPresence: DATAload[1]=00000001 DIMMPresence: MAload[1]=00000008 DIMMPresence: MAdimms[1]=00000001 DIMMPresence: Status 00001003 DIMMPresence: ErrStatus 00000000 DIMMPresence: ErrCode 00000000 DIMMPresence: Done DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 00001003 SPDCalcWidth: ErrStatus 00000010 SPDCalcWidth: ErrCode 00000000 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done SPDGetTCL_D: DIMMCASL 00000003 SPDGetTCL_D: DIMMAutoSpeed 00000003 SPDGetTCL_D: Status 00001003 SPDGetTCL_D: ErrStatus 00000010 SPDGetTCL_D: ErrCode 00000000 SPDGetTCL_D: Done AutoCycTiming: DramTimingLo 0067aa24 AutoCycTiming: DramTimingHi 00820300 AutoCycTiming: Status 00001003 AutoCycTiming: ErrStatus 00000010 AutoCycTiming: ErrCode 00000000 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done AutoConfig_D: DCT: 00000000 SPDSetBanks: Status 00001003 SPDSetBanks: ErrStatus 00000010 SPDSetBanks: ErrCode 00000000 SPDSetBanks: Done AfterStitch DCT0 and DCT1: DRAM Controller Select Low Register = 00002003 AfterStitch DCT0 and DCT1: DRAM Controller Select High Register = 00002000 AfterStitch pDCTstat->NodeSysBase = 00000000 mct_AfterStitchMemory: pDCTstat->NodeSysLimit 001fffff StitchMemory: Status 00001003 StitchMemory: ErrStatus 00000010 StitchMemory: ErrCode 00000000 StitchMemory: Done InterleaveBanks_D: Status 00001003 InterleaveBanks_D: ErrStatus 00000090 InterleaveBanks_D: ErrCode 00000000 InterleaveBanks_D: Done DramTimingLo: val=00000008 DramTimingLo: val=00000008 DramTimingLo: val=00000006 DramTimingLo: val=00000004 DramTimingLo: val=00000002 DramTimingLo: val=00000000 DramTimingLo: val=00000008 DramTimingLo: val=00000008 AutoConfig_D: DramControl: 00000005 AutoConfig_D: DramTimingLo: ef67aa24 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000000 AutoConfig_D: DramConfigLo: 00080010 AutoConfig_D: DramConfigHi: 6f48800a AutoConfig: Status 00001003 AutoConfig: ErrStatus 00000090 AutoConfig: ErrCode 00000000 AutoConfig: Done DCTInit_D: AutoConfig_D Done dct: 00000000 Speed: 00000003 CH_ODC_CTL: 20111222 CH_ADDR_TMG: 00000000 DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D StartupDCT_D: MemClkFreqVal StartupDCT_D: DqsRcvEnTrain set StartupDCT_D: DramInit mct_initDCT: DCTInit_D 1 DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 00001003 SPDCalcWidth: ErrStatus 00000090 SPDCalcWidth: ErrCode 00000000 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming: DramTimingLo 0067aa24 AutoCycTiming: DramTimingHi 00820300 AutoCycTiming: Status 00001003 AutoCycTiming: ErrStatus 00000090 AutoCycTiming: ErrCode 00000000 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done AutoConfig_D: DCT: 00000001 SPDSetBanks: Status 00001003 SPDSetBanks: ErrStatus 00000090 SPDSetBanks: ErrCode 00000000 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 00000000 mct_AfterStitchMemory: pDCTstat->NodeSysLimit 003ffffe StitchMemory: Status 00001003 StitchMemory: ErrStatus 00000090 StitchMemory: ErrCode 00000000 StitchMemory: Done InterleaveBanks_D: Status 00001003 InterleaveBanks_D: ErrStatus 00000090 InterleaveBanks_D: ErrCode 00000000 InterleaveBanks_D: Done DramTimingLo: val=00000008 DramTimingLo: val=00000008 DramTimingLo: val=00000006 DramTimingLo: val=00000004 DramTimingLo: val=00000002 DramTimingLo: val=00000000 DramTimingLo: val=00000008 DramTimingLo: val=00000008 AutoConfig_D: DramControl: 00000005 AutoConfig_D: DramTimingLo: ef67aa24 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000000 AutoConfig_D: DramConfigLo: 00080010 AutoConfig_D: DramConfigHi: 6f48800a AutoConfig: Status 00001003 AutoConfig: ErrStatus 00000090 AutoConfig: ErrCode 00000000 AutoConfig: Done DCTInit_D: AutoConfig_D Done dct: 00000001 Speed: 00000003 CH_ODC_CTL: 20111222 CH_ADDR_TMG: 00000000 DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D StartupDCT_D: MemClkFreqVal StartupDCT_D: DqsRcvEnTrain set StartupDCT_D: DramInit mctAutoInitMCT_D: mct_init Node 00000001 mctAutoInitMCT_D: clear_legacy_Mode mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: Set Cl, Wb mctAutoInitMCT_D: mctSMBhub_Init mctAutoInitMCT_D: mct_initDCT mct_initDCT: DCTInit_D 0 DIMMPresence: i=00000000 DIMMPresence: smbaddr=00000054 DIMMPresence: i=00000001 DIMMPresence: smbaddr=00000055 DIMMPresence: i=00000002 DIMMPresence: smbaddr=00000056 DIMMPresence: i=00000003 DIMMPresence: smbaddr=00000057 DIMMPresence: i=00000004 DIMMPresence: smbaddr=00000000 DIMMPresence: i=00000005 DIMMPresence: smbaddr=00000000 DIMMPresence: i=00000006 DIMMPresence: smbaddr=00000000 DIMMPresence: i=00000007 DIMMPresence: smbaddr=00000000 DIMMPresence: DIMMValid=0000000c DIMMPresence: DIMMPresent=0000000c DIMMPresence: RegDIMMPresent=0000000c DIMMPresence: DimmECCPresent=0000000c DIMMPresence: DimmPARPresent=00000000 DIMMPresence: Dimmx4Present=00000000 DIMMPresence: Dimmx8Present=0000000c DIMMPresence: Dimmx16Present=00000000 DIMMPresence: DimmPlPresent=0000000c DIMMPresence: DimmDRPresent=00000000 DIMMPresence: DimmQRPresent=00000000 DIMMPresence: DATAload[0]=00000001 DIMMPresence: MAload[0]=00000008 DIMMPresence: MAdimms[0]=00000001 DIMMPresence: DATAload[1]=00000001 DIMMPresence: MAload[1]=00000008 DIMMPresence: MAdimms[1]=00000001 DIMMPresence: Status 00001003 DIMMPresence: ErrStatus 00000000 DIMMPresence: ErrCode 00000000 DIMMPresence: Done DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 00001003 SPDCalcWidth: ErrStatus 00000010 SPDCalcWidth: ErrCode 00000000 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done SPDGetTCL_D: DIMMCASL 00000003 SPDGetTCL_D: DIMMAutoSpeed 00000003 SPDGetTCL_D: Status 00001003 SPDGetTCL_D: ErrStatus 00000010 SPDGetTCL_D: ErrCode 00000000 SPDGetTCL_D: Done AutoCycTiming: DramTimingLo 0067aa24 AutoCycTiming: DramTimingHi 00820300 AutoCycTiming: Status 00001003 AutoCycTiming: ErrStatus 00000010 AutoCycTiming: ErrCode 00000000 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done AutoConfig_D: DCT: 00000000 SPDSetBanks: Status 00001003 SPDSetBanks: ErrStatus 00000010 SPDSetBanks: ErrCode 00000000 SPDSetBanks: Done AfterStitch DCT0 and DCT1: DRAM Controller Select Low Register = 00006003 AfterStitch DCT0 and DCT1: DRAM Controller Select High Register = 00006000 AfterStitch pDCTstat->NodeSysBase = 00400000 mct_AfterStitchMemory: pDCTstat->NodeSysLimit 001fffff StitchMemory: Status 00001003 StitchMemory: ErrStatus 00000010 StitchMemory: ErrCode 00000000 StitchMemory: Done InterleaveBanks_D: Status 00001003 InterleaveBanks_D: ErrStatus 00000090 InterleaveBanks_D: ErrCode 00000000 InterleaveBanks_D: Done DramTimingLo: val=00000008 DramTimingLo: val=00000008 DramTimingLo: val=00000006 DramTimingLo: val=00000004 DramTimingLo: val=00000002 DramTimingLo: val=00000000 DramTimingLo: val=00000008 DramTimingLo: val=00000008 AutoConfig_D: DramControl: 00000005 AutoConfig_D: DramTimingLo: ef67aa24 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000000 AutoConfig_D: DramConfigLo: 00080010 AutoConfig_D: DramConfigHi: 6f48800a AutoConfig: Status 00001003 AutoConfig: ErrStatus 00000090 AutoConfig: ErrCode 00000000 AutoConfig: Done DCTInit_D: AutoConfig_D Done dct: 00000000 Speed: 00000003 CH_ODC_CTL: 20111222 CH_ADDR_TMG: 00000000 DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D StartupDCT_D: MemClkFreqVal StartupDCT_D: DqsRcvEnTrain set StartupDCT_D: DramInit mct_initDCT: DCTInit_D 1 DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 00001003 SPDCalcWidth: ErrStatus 00000090 SPDCalcWidth: ErrCode 00000000 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming: DramTimingLo 0067aa24 AutoCycTiming: DramTimingHi 00820300 AutoCycTiming: Status 00001003 AutoCycTiming: ErrStatus 00000090 AutoCycTiming: ErrCode 00000000 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done AutoConfig_D: DCT: 00000001 SPDSetBanks: Status 00001003 SPDSetBanks: ErrStatus 00000090 SPDSetBanks: ErrCode 00000000 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 00400000 mct_AfterStitchMemory: pDCTstat->NodeSysLimit 003ffffe StitchMemory: Status 00001003 StitchMemory: ErrStatus 00000090 StitchMemory: ErrCode 00000000 StitchMemory: Done InterleaveBanks_D: Status 00001003 InterleaveBanks_D: ErrStatus 00000090 InterleaveBanks_D: ErrCode 00000000 InterleaveBanks_D: Done DramTimingLo: val=00000008 DramTimingLo: val=00000008 DramTimingLo: val=00000006 DramTimingLo: val=00000004 DramTimingLo: val=00000002 DramTimingLo: val=00000000 DramTimingLo: val=00000008 DramTimingLo: val=00000008 AutoConfig_D: DramControl: 00000005 AutoConfig_D: DramTimingLo: ef67aa24 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000000 AutoConfig_D: DramConfigLo: 00080010 AutoConfig_D: DramConfigHi: 6f48800a AutoConfig: Status 00001003 AutoConfig: ErrStatus 00000090 AutoConfig: ErrCode 00000000 AutoConfig: Done DCTInit_D: AutoConfig_D Done dct: 00000001 Speed: 00000003 CH_ODC_CTL: 20111222 CH_ADDR_TMG: 00000000 DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D StartupDCT_D: MemClkFreqVal StartupDCT_D: DqsRcvEnTrain set StartupDCT_D: DramInit mctAutoInitMCT_D: mct_init Node 00000002 mctAutoInitMCT_D: mct_init Node 00000003 mctAutoInitMCT_D: mct_init Node 00000004 mctAutoInitMCT_D: mct_init Node 00000005 mctAutoInitMCT_D: mct_init Node 00000006 mctAutoInitMCT_D: mct_init Node 00000007 mctAutoInitMCT_D: SyncDCTsReady_D mct_SyncDCTsReady: Node 00000000 mct_SyncDCTsReady: DramEnabled mct_SyncDCTsReady: Node 00000001 mct_SyncDCTsReady: DramEnabled mctAutoInitMCT_D: HTMemMapInit_D Node: 00 base: 00 limit: 3fffff BottomIO: e00000 Node: 01 base: 400000 limit: 7fffff BottomIO: e00000 Copy dram map from Node 0 to Node 01 mctAutoInitMCT_D: CPUMemTyping_D CPUMemTyping: Cache32bTOP:00800000 CPUMemTyping: Bottom32bIO:00800000 CPUMemTyping: Bottom40bIO:00000000 mctAutoInitMCT_D: DQSTiming_D DQSTiming_D: mct_BeforeDQSTrain_D: DQSTiming_D: TrainReceiverEn_D FirstPass: TrainRcvrEn: 1 TrainRcvrEn: 2 TrainRcvrEn: 3 TrainRcvrEn: 4 Rank not enabled_D Rank not enabled_D Rank not enabled_D Rank not enabled_D Rank not enabled_D Rank not enabled_D TrainRcvrEn: mct_DisableDQSRcvEn_D TrainRcvrEn: Status 00001003 TrainRcvrEn: ErrStatus 00000090 TrainRcvrEn: ErrCode 00000000 TrainRcvrEn: Done TrainRcvrEn: 1 TrainRcvrEn: 2 TrainRcvrEn: 3 TrainRcvrEn: 4 Rank not enabled_D Rank not enabled_D Rank not enabled_D Rank not enabled_D Rank not enabled_D Rank not enabled_D TrainRcvrEn: mct_DisableDQSRcvEn_D TrainRcvrEn: Status 00001003 TrainRcvrEn: ErrStatus 00000090 TrainRcvrEn: ErrCode 00000000 TrainRcvrEn: Done DQSTiming_D: mct_TrainDQSPos_D TrainDQSRdWrPos: Status 00001003 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000090 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001003 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000090 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001003 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000090 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001003 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000090 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001003 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000090 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001003 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000090 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001003 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000090 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001003 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000090 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done DQSTiming_D: mctSetEccDQSRcvrEn_D DQSTiming_D: TrainMaxReadLatency_D DQSTiming_D: mct_EndDQSTraining_D DQSTiming_D: MCTMemClr_D mctAutoInitMCT_D: UMAMemTyping_D mctAutoInitMCT_D: :OtherTiming InterleaveNodes_D: Status 00001003 InterleaveNodes_D: ErrStatus 00000090 InterleaveNodes_D: ErrCode 00000000 InterleaveNodes_D: Done InterleaveChannels: F2x110 DRAM Controller Select Low Register = 00000584 InterleaveChannels_D: Node 00000000 InterleaveChannels_D: Status 00001003 InterleaveChannels_D: ErrStatus 00000090 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels: F2x110 DRAM Controller Select Low Register = 00004584 InterleaveChannels_D: Node 00000001 InterleaveChannels_D: Status 00001003 InterleaveChannels_D: ErrStatus 00000090 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000002 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000003 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000004 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000005 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000006 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000007 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Done mctAutoInitMCT_D: ECCInit_D ECCInit 0 ECC enabled on node: 00000000 ECC enabled on node: 00000001 ECCInit 1 ECCInit 2 ECCInit 3 mctAutoInitMCT_D: MCTMemClr_D mct_FinalMCT_D: Clr Cl, Wb All Done raminit_amdmct end: *** Yes, the copy/decompress is taking a while, FIXME! v_esp=000cbf38 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Uncompressing coreboot to RAM. src=fffdf000 dst=00200000 coreboot_ram.nrv2b length = 0000d5c7 coreboot_ram.bin length = 0002746c Jumping to coreboot. coreboot-2.0.0_Fallback ti. 12. aug. 13:51:54 +0200 2008 booting... Enumerating buses... APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled PCI: 00:18.0 links increase to 8 PCI: 00:18.3 siblings=3 CPU: APIC: 00 enabled CPU: APIC: 01 enabled CPU: APIC: 02 enabled CPU: APIC: 03 enabled PCI: 00:19.0 [1022/1200] enabled PCI: 00:19.1 [1022/1201] enabled PCI: 00:19.2 [1022/1202] enabled PCI: 00:19.3 [1022/1203] enabled PCI: 00:19.4 [1022/1204] enabled PCI: 00:19.0 links increase to 8 PCI: 00:19.3 siblings=3 CPU: APIC: 04 enabled CPU: APIC: 05 enabled CPU: APIC: 06 enabled CPU: APIC: 07 enabled PCI: pci_scan_bus for bus 00 PCI: 00:18.0 [1022/1200] enabled PCI: 00:18.1 [1022/1201] enabled PCI: 00:18.2 [1022/1202] enabled PCI: 00:18.3 [1022/1203] enabled PCI: 00:18.4 [1022/1204] enabled PCI: 00:19.0 [1022/1200] enabled PCI: 00:19.1 [1022/1201] enabled PCI: 00:19.2 [1022/1202] enabled PCI: 00:19.3 [1022/1203] enabled PCI: 00:19.4 [1022/1204] enabled PCI: 00:00.0 [10de/0369] enabled PCI: 00:01.0 [10de/0369] enabled next_unitid: 0011 PCI: pci_scan_bus for bus 00 PCI: 00:01.0 [10de/0369] enabled PCI: 00:02.0 [10de/0364] enabled PCI: 00:02.1 [10de/0368] enabled PCI: 00:02.2 [10de/036a] enabled PCI: 00:02.3 [10de/036b] enabled PCI: 00:03.0 [10de/036c] enabled PCI: 00:03.1 [10de/036d] enabled PCI: 00:05.0 [10de/036e] enabled PCI: 00:06.0 [10de/037f] enabled PCI: 00:06.1 [10de/037f] enabled PCI: 00:06.2 [10de/037f] enabled PCI: 00:07.0 [10de/0370] enabled PCI: 00:07.1 [10de/0371] disabled PCI: 00:09.0 [10de/0372] enabled PCI: 00:0a.0 [10de/0372] enabled PCI: 00:0b.0 [10de/0376] enabled PCI: 00:0e.0 [10de/0378] enabled PCI: 00:10.0 [10de/0377] enabled PNP: 002e.0 disabled PNP: 002e.1 disabled PNP: 002e.2 enabled PNP: 002e.3 enabled PNP: 002e.5 enabled PNP: 002e.6 disabled PNP: 002e.7 disabled PNP: 002e.8 disabled PNP: 002e.9 disabled PNP: 002e.a disabled PNP: 002e.b enabled smbus: PCI: 00:02.1[0]->I2C: 01:50 enabled smbus: PCI: 00:02.1[0]->I2C: 01:51 enabled smbus: PCI: 00:02.1[0]->I2C: 01:52 enabled smbus: PCI: 00:02.1[0]->I2C: 01:53 enabled smbus: PCI: 00:02.1[0]->I2C: 01:54 enabled smbus: PCI: 00:02.1[0]->I2C: 01:55 enabled smbus: PCI: 00:02.1[0]->I2C: 01:56 enabled smbus: PCI: 00:02.1[0]->I2C: 01:57 enabled smbus: PCI: 00:02.1[1]->I2C: 02:51 enabled PCI: pci_scan_bus for bus 01 PCI: 01:04.0 [1002/515e] enabled PCI: pci_scan_bus returning with max=001 PCI: pci_scan_bus for bus 02 PCI: pci_scan_bus returning with max=002 PCI: pci_scan_bus for bus 03 PCI: pci_scan_bus returning with max=003 PCI: pci_scan_bus for bus 04 PCI: pci_scan_bus returning with max=004 PCI: pci_scan_bus returning with max=004 PCI: pci_scan_bus returning with max=004 done Allocating resources... Reading resources... PCI: 00:0b.0 1c <- [0x00fffff000 - 0x00ffffefff] size 0x00000000 gran 0x0c bus 02 io PCI: 00:0b.0 24 <- [0xfffffffffff00000 - 0xffffffffffefffff] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:0b.0 20 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 02 mem PCI: 00:0e.0 1c <- [0x00fffff000 - 0x00ffffefff] size 0x00000000 gran 0x0c bus 03 io PCI: 00:0e.0 24 <- [0xfffffffffff00000 - 0xffffffffffefffff] size 0x00000000 gran 0x14 bus 03 prefmem PCI: 00:0e.0 20 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 03 mem PCI: 00:10.0 1c <- [0x00fffff000 - 0x00ffffefff] size 0x00000000 gran 0x0c bus 04 io PCI: 00:10.0 24 <- [0xfffffffffff00000 - 0xffffffffffefffff] size 0x00000000 gran 0x14 bus 04 prefmem PCI: 00:10.0 20 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 04 mem Done reading resources. Allocating VGA resource PCI: 01:04.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:07.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Setting resources... VGA: PCI: 00:18.0 (aka node 0) link 2 has VGA device PCI: 00:18.0 210d8 <- [0x0000001000 - 0x0000003fff] size 0x00003000 gran 0x0c io PCI: 00:18.0 210b8 <- [0x00f0000000 - 0x00f7ffffff] size 0x08000000 gran 0x14 prefmem PCI: 00:18.0 210b0 <- [0x00fc000000 - 0x00fc1fffff] size 0x00200000 gran 0x14 mem PCI: 00:02.0 14 <- [0x00fc140000 - 0x00fc140fff] size 0x00001000 gran 0x0c mem PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq PNP: 002e.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq PNP: 002e.b 60 <- [0x0000000290 - 0x0000000297] size 0x00000008 gran 0x03 io PNP: 002e.b 70 <- [0x0000000005 - 0x0000000005] size 0x00000001 gran 0x00 irq PCI: 00:02.1 20 <- [0x0000002c00 - 0x0000002c3f] size 0x00000040 gran 0x06 io PCI: 00:02.1 24 <- [0x0000002c40 - 0x0000002c7f] size 0x00000040 gran 0x06 io PCI: 00:02.1 60 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io PCI: 00:02.1 64 <- [0x0000002400 - 0x00000024ff] size 0x00000100 gran 0x08 io PCI: 00:02.1 68 <- [0x0000002800 - 0x00000028ff] size 0x00000100 gran 0x08 io PCI: 00:02.3 10 <- [0x00fc100000 - 0x00fc13ffff] size 0x00040000 gran 0x12 mem PCI: 00:03.0 10 <- [0x00fc141000 - 0x00fc141fff] size 0x00001000 gran 0x0c mem PCI: 00:03.1 10 <- [0x00fc147000 - 0x00fc1470ff] size 0x00000100 gran 0x08 mem PCI: 00:05.0 20 <- [0x0000002c80 - 0x0000002c8f] size 0x00000010 gran 0x04 io PCI: 00:06.0 10 <- [0x0000002cc0 - 0x0000002cc7] size 0x00000008 gran 0x03 io PCI: 00:06.0 14 <- [0x0000003030 - 0x0000003033] size 0x00000004 gran 0x02 io PCI: 00:06.0 18 <- [0x0000002cd0 - 0x0000002cd7] size 0x00000008 gran 0x03 io PCI: 00:06.0 1c <- [0x0000003040 - 0x0000003043] size 0x00000004 gran 0x02 io PCI: 00:06.0 20 <- [0x0000002c90 - 0x0000002c9f] size 0x00000010 gran 0x04 io PCI: 00:06.0 24 <- [0x00fc142000 - 0x00fc142fff] size 0x00001000 gran 0x0c mem PCI: 00:06.1 10 <- [0x0000002ce0 - 0x0000002ce7] size 0x00000008 gran 0x03 io PCI: 00:06.1 14 <- [0x0000003050 - 0x0000003053] size 0x00000004 gran 0x02 io PCI: 00:06.1 18 <- [0x0000002cf0 - 0x0000002cf7] size 0x00000008 gran 0x03 io PCI: 00:06.1 1c <- [0x0000003060 - 0x0000003063] size 0x00000004 gran 0x02 io PCI: 00:06.1 20 <- [0x0000002ca0 - 0x0000002caf] size 0x00000010 gran 0x04 io PCI: 00:06.1 24 <- [0x00fc143000 - 0x00fc143fff] size 0x00001000 gran 0x0c mem PCI: 00:06.2 10 <- [0x0000002d00 - 0x0000002d07] size 0x00000008 gran 0x03 io PCI: 00:06.2 14 <- [0x0000003070 - 0x0000003073] size 0x00000004 gran 0x02 io PCI: 00:06.2 18 <- [0x0000003000 - 0x0000003007] size 0x00000008 gran 0x03 io PCI: 00:06.2 1c <- [0x0000003080 - 0x0000003083] size 0x00000004 gran 0x02 io PCI: 00:06.2 20 <- [0x0000002cb0 - 0x0000002cbf] size 0x00000010 gran 0x04 io PCI: 00:06.2 24 <- [0x00fc144000 - 0x00fc144fff] size 0x00001000 gran 0x0c mem PCI: 00:07.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io PCI: 00:07.0 24 <- [0x00f0000000 - 0x00f7ffffff] size 0x08000000 gran 0x14 bus 01 prefmem PCI: 00:07.0 20 <- [0x00fc000000 - 0x00fc0fffff] size 0x00100000 gran 0x14 bus 01 mem PCI: 01:04.0 10 <- [0x00f0000000 - 0x00f7ffffff] size 0x08000000 gran 0x1b prefmem PCI: 01:04.0 14 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 01:04.0 18 <- [0x00fc000000 - 0x00fc00ffff] size 0x00010000 gran 0x10 mem PCI: 01:04.0 30 <- [0x00fff80000 - 0x00fff9ffff] size 0x00020000 gran 0x11 romem PCI: 00:09.0 10 <- [0x00fc145000 - 0x00fc145fff] size 0x00001000 gran 0x0c mem PCI: 00:09.0 14 <- [0x0000003010 - 0x0000003017] size 0x00000008 gran 0x03 io PCI: 00:09.0 18 <- [0x00fc148000 - 0x00fc1480ff] size 0x00000100 gran 0x08 mem PCI: 00:09.0 1c <- [0x00fc14a000 - 0x00fc14a00f] size 0x00000010 gran 0x04 mem PCI: 00:0a.0 10 <- [0x00fc146000 - 0x00fc146fff] size 0x00001000 gran 0x0c mem PCI: 00:0a.0 14 <- [0x0000003020 - 0x0000003027] size 0x00000008 gran 0x03 io PCI: 00:0a.0 18 <- [0x00fc149000 - 0x00fc1490ff] size 0x00000100 gran 0x08 mem PCI: 00:0a.0 1c <- [0x00fc14b000 - 0x00fc14b00f] size 0x00000010 gran 0x04 mem PCI: 00:18.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem PCI: 00:19.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem Done setting resources. Done allocating resources. Enabling resources... PCI: 00:18.0 cmd <- 00 PCI: 00:01.0 subsystem <- 10f1/2912 PCI: 00:01.0 cmd <- 06 PCI: 00:02.0 subsystem <- 10f1/2912 PCI: 00:02.0 cmd <- 0f mcp55 lpc decode:PNP: 002e.2, base=0x000003f8, end=0x000003ff mcp55 lpc decode:PNP: 002e.3, base=0x000002f8, end=0x000002ff mcp55 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000060 mcp55 lpc decode:PNP: 002e.5, base=0x00000064, end=0x00000064 w83627hf hwm smbus enabled mcp55 lpc decode:PNP: 002e.b, base=0x00000290, end=0x00000297 PCI: 00:02.1 subsystem <- 10f1/2912 PCI: 00:02.1 cmd <- 01 PCI: 00:02.2 cmd <- 400 PCI: 00:02.3 cmd <- 02 PCI: 00:03.0 subsystem <- 10f1/2912 PCI: 00:03.0 cmd <- 02 PCI: 00:03.1 subsystem <- 10f1/2912 PCI: 00:03.1 cmd <- 02 PCI: 00:05.0 subsystem <- 10f1/2912 PCI: 00:05.0 cmd <- 01 PCI: 00:06.0 subsystem <- 10f1/2912 PCI: 00:06.0 cmd <- 03 PCI: 00:06.1 subsystem <- 10f1/2912 PCI: 00:06.1 cmd <- 03 PCI: 00:06.2 subsystem <- 10f1/2912 PCI: 00:06.2 cmd <- 03 PCI: 00:07.0 bridge ctrl <- 000b PCI: 00:07.0 cmd <- 07 PCI: 01:04.0 subsystem <- 10f1/2912 PCI: 01:04.0 cmd <- 83 PCI: 00:09.0 subsystem <- 10f1/2912 PCI: 00:09.0 cmd <- 03 PCI: 00:0a.0 subsystem <- 10f1/2912 PCI: 00:0a.0 cmd <- 03 PCI: 00:0b.0 bridge ctrl <- 0003 PCI: 00:0b.0 cmd <- 00 PCI: 00:0e.0 bridge ctrl <- 0003 PCI: 00:0e.0 cmd <- 00 PCI: 00:10.0 bridge ctrl <- 0003 PCI: 00:10.0 cmd <- 00 PCI: 00:18.1 subsystem <- 10f1/2912 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 10f1/2912 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 subsystem <- 10f1/2912 PCI: 00:18.4 cmd <- 00 PCI: 00:19.0 cmd <- 00 PCI: 00:19.1 cmd <- 00 PCI: 00:19.2 cmd <- 00 PCI: 00:19.3 cmd <- 00 PCI: 00:19.4 cmd <- 00 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init start_eip=0x0000b000, offset=0x00200000, code_size=0x0000005b Initializing CPU #0 CPU: vendor AMD device 100f23 CPU: family 10, model 02, stepping 03 nodeid = 00, coreid = 00 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB DONE variable MTRRs Clear out the extra MTRR's MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Setting up local apic... apic_id: 0x00 done. CPU model: Quad-Core AMD Opteron(tm) Processor 2350 siblings = 03, CPU #0 Initialized Initializing CPU #1 CPU: vendor AMD device 100f23 CPU: family 10, model 02, stepping 03 nodeid = 00, coreid = 01 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB DONE variable MTRRs Clear out the extra MTRR's MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Setting up local apic... apic_id: 0x01 done. CPU model: Quad-Core AMD Opteron(tm) Processor 2350 siblings = 03, CPU #1 Initialized Initializing CPU #2 CPU: vendor AMD device 100f23 CPU: family 10, model 02, stepping 03 nodeid = 00, coreid = 02 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB DONE variable MTRRs Clear out the extra MTRR's MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Setting up local apic... apic_id: 0x02 done. CPU model: Quad-Core AMD Opteron(tm) Processor 2350 siblings = 03, CPU #2 Initialized Initializing CPU #3 CPU: vendor AMD device 100f23 CPU: family 10, model 02, stepping 03 nodeid = 00, coreid = 03 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB DONE variable MTRRs Clear out the extra MTRR's MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Setting up local apic... apic_id: 0x03 done. CPU model: Quad-Core AMD Opteron(tm) Processor 2350 siblings = 03, CPU #3 Initialized Initializing CPU #4 CPU: vendor AMD device 100f23 CPU: family 10, model 02, stepping 03 nodeid = 01, coreid = 00 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB DONE variable MTRRs Clear out the extra MTRR's MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Setting up local apic... apic_id: 0x04 done. CPU model: Quad-Core AMD Opteron(tm) Processor 2350 siblings = 03, CPU #4 Initialized Initializing CPU #5 CPU: vendor AMD device 100f23 CPU: family 10, model 02, stepping 03 nodeid = 01, coreid = 01 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB DONE variable MTRRs Clear out the extra MTRR's MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Setting up local apic... apic_id: 0x05 done. CPU model: Quad-Core AMD Opteron(tm) Processor 2350 siblings = 03, CPU #5 Initialized Initializing CPU #6 CPU: vendor AMD device 100f23 CPU: family 10, model 02, stepping 03 nodeid = 01, coreid = 02 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB DONE variable MTRRs Clear out the extra MTRR's MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Setting up local apic... apic_id: 0x06 done. CPU model: Quad-Core AMD Opteron(tm) Processor 2350 siblings = 03, CPU #6 Initialized Initializing CPU #7 Waiting for 1 CPUS to stop CPU: vendor AMD device 100f23 CPU: family 10, model 02, stepping 03 nodeid = 01, coreid = 03 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB DONE variable MTRRs Clear out the extra MTRR's MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Setting up local apic... apic_id: 0x07 done. CPU model: Quad-Core AMD Opteron(tm) Processor 2350 siblings = 03, CPU #7 Initialized All AP CPUs stopped PCI: 00:18.0 init PCI: 00:02.0 init set power on after power fail RTC Init Invalid CMOS LB checksum PNP: 002e.2 init PNP: 002e.3 init PNP: 002e.5 init Keyboard init... PNP: 002e.b init PCI: 00:02.1 init PCI: 00:03.1 init PCI: 00:05.0 init IDE0 PCI: 00:06.0 init SATA S SATA P PCI: 00:06.1 init SATA S SATA P PCI: 00:06.2 init SATA S SATA P PCI: 00:07.0 init dev_root mem base = 0x00f0000000 [0x50] <-- 0xf0000000 PCI: 01:04.0 init rom address for PCI: 01:04.0 = fff80000 copying VGA ROM Image from 0xfff80000 to 0xc0000, 0xb000 bytes entering emulator un-inited int vector halt_sys: file /home/argggh/projects/dnc/sw/coreboot-v2/src/devices/emulator/x86emu/ops.c, line 4387 PCI: 00:09.0 init MCP55 MAC PHY ID 0x01410c00 PHY ADDR 32 PCI: 00:0a.0 init MCP55 MAC PHY ID 0x01410c00 PHY ADDR 1 PCI: 00:0b.0 init PCI: 00:0e.0 init PCI: 00:10.0 init PCI: 00:18.1 init PCI: 00:18.2 init PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 00:18.4 init PCI: 00:19.0 init PCI: 00:19.1 init PCI: 00:19.2 init PCI: 00:19.3 init NB: Function 3 Misc Control.. done. PCI: 00:19.4 init PCI: 00:02.2 init PCI: 00:02.3 init Devices initialized i=0 bus range: [0, 4] bus_isa=5 Writing IRQ routing tables to 0xf0000...done. Wrote the mp table end at: 00000020 - 000002b4 Moving GDT to 0x500...ok Adjust low_table_end from 0x00000530 to 0x00001000 Adjust rom_table_end from 0x000f0400 to 0x00100000 Wrote coreboot table at: 00000530 - 00000e98 checksum e39f elfboot: Attempting to load payload. rom_stream: 0xfff8b000 - 0xfffdefff Found ELF candidate at offset 0 header_offset is 0 Try to load at offset 0x0 New segment addr 0x100000 size 0x41270 offset 0xc0 filesize 0x134ac (cleaned up) New segment addr 0x100000 size 0x41270 offset 0xc0 filesize 0x134ac New segment addr 0x141270 size 0x48 offset 0x1356c filesize 0x48 (cleaned up) New segment addr 0x141270 size 0x48 offset 0x1356c filesize 0x48 Dropping non PT_LOAD segment Dropping non PT_LOAD segment Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000041270 filesz: 0x00000000000134ac Clearing Segment: addr: 0x00000000001134ac memsz: 0x000000000002ddc4 Loading Segment: addr: 0x0000000000141270 memsz: 0x0000000000000048 filesz: 0x0000000000000048 Jumping to boot code at 0x100084 FILO version 0.5.6 (argggh@pelargir) ti. 12. aug. 13:17:48 +0200 2008 collect_linuxbios_info: Searching for LinuxBIOS tables... find_lb_table: Found candidate at: 00000530 find_lb_table: header checksum o.k. find_lb_table: table checksum o.k. find_lb_table: record count o.k. collect_linuxbios_info: Found LinuxBIOS table at: 00000530 convert_memmap: 0x00000000000000 0x00000000001000 16 convert_memmap: 0x00000000001000 0x0000000009f000 1 convert_memmap: 0x000000000c0000 0x00000000030000 1 convert_memmap: 0x000000000f0000 0x00000000010000 16 convert_memmap: 0x00000000100000 0x0000003ff00000 1 convert_memmap: 0x00000040000000 0x00000040000000 1 pci_init: Scanning PCI: found 28 devices pci_init: 00:01.0 10de:0369 0500 00 pci_init: 00:02.0 10de:0364 0601 00 pci_init: 00:02.1 10de:0368 0c05 00 pci_init: 00:02.2 10de:036a 0500 00 pci_init: 00:02.3 10de:036b 0b40 00 pci_init: 00:03.0 10de:036c 0c03 10 pci_init: 00:03.1 10de:036d 0c03 20 pci_init: 00:05.0 10de:036e 0101 8a pci_init: 00:06.0 10de:037f 0101 85 pci_init: 00:06.1 10de:037f 0101 85 pci_init: 00:06.2 10de:037f 0101 85 pci_init: 00:07.0 10de:0370 0604 00 pci_init: 00:09.0 10de:0372 0200 00 pci_init: 00:0a.0 10de:0372 0200 00 pci_init: 00:0b.0 10de:0376 0604 00 pci_init: 00:0e.0 10de:0378 0604 00 pci_init: 00:10.0 10de:0377 0604 00 pci_init: 00:18.0 1022:1200 0600 00 pci_init: 00:18.1 1022:1201 0600 00 pci_init: 00:18.2 1022:1202 0600 00 pci_init: 00:18.3 1022:1203 0600 00 pci_init: 00:18.4 1022:1204 0600 00 pci_init: 00:19.0 1022:1200 0600 00 pci_init: 00:19.1 1022:1201 0600 00 pci_init: 00:19.2 1022:1202 0600 00 pci_init: 00:19.3 1022:1203 0600 00 pci_init: 00:19.4 1022:1204 0600 00 pci_init: 01:04.0 1002:515e 0300 00 menu: hde1:/grub/menu.lst find_ide_controller: found PCI IDE controller 10de:037f prog_if=0x85 find_ide_controller: primary channel: native PCI mode find_ide_controller: cmd_base=0x2cc0 ctrl_base=0x3030 init_controller: init_controller: drive 4 ide_software_reset: Waiting for ide2 to become ready for reset... ok ide_software_reset: Resetting ide2... IDE time out reset failed, but we may be on SATA ide_software_reset: ok init_drive: Testing for hde init_drive: Testing for hde init_controller: MASTER CHECK: master no init_controller: /*slave */ -- drive is 4 init_controller: NO MASTER -- check slave! init_drive: Testing for hde init_drive: Testing for hde init_controller: SLAVE ONLY CHECK: slave no Drive 4 does not exist devopen: failed to open ide Press any key to continue. Press any key to continue. Press any key to continue. Press any key to continue. Press any key to continue.