Hi David,

Thanks for your inputs. I had some build problem building superiotool from coreboot due to missing pci.h. I copied superiotool from my ubuntu12.04 and have requested output below. Is it the case that superio chip on this board listed by superiotool (WPCE775x / NPCE781x) is not supported by coreboot? In src/superio/nuvoton directory I see nct5104d and wpcm 450 directory.

root@localhost:~# ./superiotool -v
superiotool r6637
root@localhost:~# ./superiotool
superiotool r6637
Found Nuvoton WPCE775x / NPCE781x (id=0x00, rev=0x04) at 0x4e
root@localhost:~# ./superiotool -d
superiotool r6637
Found Nuvoton WPCE775x / NPCE781x (id=0x00, rev=0x04) at 0x4e
Register dump:
idx 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f
val fc 11 00 00 06 00 00 04 00 14 01 01 00 00 00 00
def fc 11 RR RR RR 00 00 MM 00 04 RR RR RR 00 RR RR
LDN 0x03 (CIR Port (CIRP))
idx 30 60 61 70 71 74 75 f0
val 00 00 00 00 00 00 00 00
def 00 03 f8 04 03 04 04 02
LDN 0x04 (Mobile System Wake-Up Control Config (MSWC))
idx 30 60 61 70 71 74 75
val 00 00 00 00 03 04 04
def 00 00 00 00 03 04 04
LDN 0x05 (Mouse config (KBC))
idx 30 70 71 74 75
val 00 0c 03 04 04
def 00 0c 03 04 04
LDN 0x06 (Keyboard config (KBC))
idx 30 60 61 62 63 70 71 74 75
val 00 00 60 00 64 01 03 04 04
def 00 00 60 00 64 01 03 04 04
LDN 0x0f (Shared memory (SHM))
idx 30 60 61 70 71 74 75 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb
val 00 00 00 00 03 04 04 09 87 03 00 00 00 00 00 00 00 00 00
def 00 00 00 00 00 04 04 MM 07 RR RR 00 00 00 00 00 00 00 00
LDN 0x11 (Power management I/F Channel 1 (PM1))
idx 30 60 61 62 63 70 71 74 75
val 01 00 62 00 66 00 03 04 04
def 00 00 62 00 66 01 03 04 04
LDN 0x12 (Power management I/F Channel 2 (PM2))
idx 30 60 61 62 63 70 71 74 75
val 01 00 80 00 80 00 03 04 04
def 00 00 68 00 6c 01 03 04 04
LDN 0x15 (Enhanced Wake On CIR (EWOC))
idx 30 60 61 62 63 70 71 74 75
val 00 00 00 00 00 00 00 00 00
def 00 00 00 00 00 00 03 04 04
LDN 0x17 (Power Management I/F Channel 3 (PM3))
idx 30 60 61 62 63 70 71 74 75
val 01 00 81 00 81 00 03 04 04
def 00 00 6a 00 6e 01 03 04 04
LDN 0x1a (Serial Port with Fast Infrared Port (FIR))
idx 30 60 61 70 71 74 75 f0
val 00 00 00 00 00 00 00 00
def 00 02 f8 03 03 04 04 02
root@localhost:~# ./superiotool -e
superiotool r6637
Found Nuvoton WPCE775x / NPCE781x (id=0x00, rev=0x04) at 0x4e
root@localhost:~#

On Sun, Nov 9, 2014 at 12:23 PM, David Hendricks <david.hendricks@gmail.com> wrote:

Hi Gailu,
You might need to set an enable bit for the UART2 logical device in the EC. Can you run superiotool (from coreboot/util/superiotool) to dump the EC config registers on the CRB?

(I'm just guessing - I've never used a Bayley Bay CRB)

On Fri, Nov 7, 2014 at 8:46 AM, Gailu Singh <gailu96@gmail.com> wrote:
Hi,

I got the schematics now and I see that J9B4 is connected to Embedded Controller (EC), so I think that this is not 8250 UART2. Am I right?

I am not able to find the documentation what purpose is served by Embedded Controller and does coreboot use it at all? Any pointers please. I am trying to understand what is the purpose of COM port at J9B4. Any specific document that I should refer to to understand it? I checked user guide and schematics.

There are 2 com ports I see using usb to serial and Port0 is used for console. Is another port on usb to serial is spare and can be used for console or is it serving some other purpose in coreboot.

On Fri, Nov 7, 2014 at 3:51 PM, Gailu Singh <gailu96@gmail.com> wrote:
Hi Experts,

I have working console uart 0 on Baytrail CRB board. However I am trying to change to uart 2 (J9B4) DB9 connector. I have changed CONFIG_UART_FOR_CONSOLE=2 from menuconfig, cleaned and rebuild and flashed coreboot but do not see any log on port 2. Is there any other changes required apart from CONFIG_UART_FOR_CONSOLE ?

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