coreboot-2.3" Thu Dec  3 00:56:18 CET 2009 starting...
SMBus controller enabled
Copying coreboot to RAM.
Loading stage image.
Stage: loading fallback/coreboot_ram @ 0x100000 (147456 bytes), entry @ 0x100000
Stage: done loading.
Jumping to image.
coreboot-2.3 Thu Dec  3 10:33:42 CET 2009 booting...
clocks_per_usec: 650
Enumerating buses...
APIC_CLUSTER: 0 enabled
Finding PCI configuration type.
PCI: Using configuration type 1
PCI_DOMAIN: 0000 enabled
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/7180] enabled
PCI: 00:01.0 [8086/7181] disabled
PCI: 00:07.0 [8086/7110] enabled
PCI: 00:07.1 [8086/7111] enabled
PCI: 00:07.2 [8086/7112] enabled
PCI: 00:07.3 [8086/7113] enabled
Found SMSC Super I/O (ID=0x46, rev=0x01)
PNP: 03f0.0 enabled
PNP: 03f0.3 enabled
PNP: 03f0.4 enabled
PNP: 03f0.5 enabled
PNP: 03f0.7 enabled
PNP: 03f0.8 enabled
PCI: pci_scan_bus returning with max=000
done
Allocating resources...
Reading resources...
APIC: 00 missing read_resources
PNP: 03f0.0 missing read_resources
PNP: 03f0.3 missing read_resources
PNP: 03f0.4 missing read_resources
PNP: 03f0.5 missing read_resources
PNP: 03f0.7 missing read_resources
PNP: 03f0.8 missing read_resources
Done reading resources.
skipping PNP: 03f0.0@60 fixed resource, size=0!
skipping PNP: 03f0.0@70 fixed resource, size=0!
skipping PNP: 03f0.0@74 fixed resource, size=0!
skipping PNP: 03f0.3@60 fixed resource, size=0!
skipping PNP: 03f0.3@70 fixed resource, size=0!
skipping PNP: 03f0.4@60 fixed resource, size=0!
skipping PNP: 03f0.4@70 fixed resource, size=0!
skipping PNP: 03f0.5@60 fixed resource, size=0!
skipping PNP: 03f0.5@70 fixed resource, size=0!
skipping PNP: 03f0.7@60 fixed resource, size=0!
skipping PNP: 03f0.7@62 fixed resource, size=0!
skipping PNP: 03f0.7@70 fixed resource, size=0!
skipping PNP: 03f0.7@72 fixed resource, size=0!
Setting resources...
Setting RAM size to 128 MB
PCI: 00:00.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem
PNP: 03f0.0 missing set_resources
PNP: 03f0.3 missing set_resources
PNP: 03f0.4 missing set_resources
PNP: 03f0.5 missing set_resources
PNP: 03f0.7 missing set_resources
PCI: 00:07.1 20 <- [0x0000001020 - 0x000000102f] size 0x00000010 gran 0x04 io
PCI: 00:07.2 20 <- [0x0000001000 - 0x000000101f] size 0x00000020 gran 0x05 io
Done setting resources.
Done allocating resources.
Enabling resources...
PCI: 00:00.0 cmd <- 06
PCI: 00:07.0 cmd <- 07
PCI: 00:07.1 cmd <- 01
PCI: 00:07.2 cmd <- 01
PCI: 00:07.3 cmd <- 01
done.
Initializing devices...
Root Device init
APIC_CLUSTER: 0 init
Initializing CPU #0
CPU: vendor Intel device 660
CPU: family 06, model 06, stepping 00
Enabling cache

Setting fixed MTRRs(0-88) Type: UC
Setting fixed MTRRs(0-16) Type: WB
Setting fixed MTRRs(24-88) Type: WB
DONE fixed MTRRs
Setting variable MTRR 0, base:    0MB, range:  128MB, type WB
DONE variable MTRRs
Clear out the extra MTRR's

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

microcode_info: sig = 0x00000660 pf=0x00000001 rev = 0x00000000
Disabling local apic...done.
CPU #0 initialized
PCI: 00:00.0 init
PCI: 00:07.0 init
RTC Init
PCI: 00:07.1 init
IDE: Primary IDE interface: on
IDE: Secondary IDE interface: on
IDE: Access to legacy IDE ports: on
IDE: Primary IDE interface, drive 0: UDMA/33: off
IDE: Primary IDE interface, drive 1: UDMA/33: off
IDE: Secondary IDE interface, drive 0: UDMA/33: off
IDE: Secondary IDE interface, drive 1: UDMA/33: off
PCI: 00:07.2 init
Devices initialized
Initializing CBMEM area to 0x7ff0000 (65536 bytes)
Adding CBMEM entry as no. 1
Moving GDT to 07ff0200...ok
High Tables Base is 7ff0000.
Copying Interrupt Routing Table to 0x000f0000... done.
Adding CBMEM entry as no. 2
Copying Interrupt Routing Table to 0x07ff0400... done.
PIRQ table: 112 bytes.
Adding CBMEM entry as no. 3
Writing high table forward entry at 0x00000500
Wrote coreboot table at: 00000500 - 00000518  checksum e3df
New low_table_end: 0x00000518
Now going to write high coreboot table at 0x07ff1400
rom_table_end = 0x07ff1400
Adjust low_table_end from 0x00000518 to 0x00001000 
Adjust rom_table_end from 0x07ff1400 to 0x08000000 
Adding high table area
Wrote coreboot table at: 07ff1400 - 07ff1590  checksum 3bbe
coreboot table: 400 bytes.
 0. FREE SPACE 83ffbff7a1e90170 840f45ffffff58bd
 3. COREBOOT   07ff1400 00002000
Got a payload
Loading segment from rom address 0xfffe8238
  parameter section (skipped)
Loading segment from rom address 0xfffe8254
  data (compression=1)
  New segment dstaddr 0x100000 memsize 0x36710 srcaddr 0xfffe82e2 filesize 0x3e82
  (cleaned up) New segment addr 0x100000 size 0x36710 offset 0xfffe82e2 filesize 0x3e82
Loading segment from rom address 0xfffe8270
  Entry Point 0x00100000
Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000036710 filesz: 0x0000000000003e82
Post relocation: addr: 0x0000000007f958f0 memsz: 0x0000000000036710 filesz: 0x0000000000003e82
using LZMA
lzma: Decoding error = 1
Clearing Segment: addr: 0x0000000007f958f0 memsz: 0x0000000000036710
dest 07f958f0, end 07fcc000, bouncebuffer 7f958f0
move suffix around: from 7fb98f0, to 124000, amount: 12710
Jumping to boot code at 100000
coreboot-2.3 Thu Dec  3 10:33:42 CET 2009 rebooting...
clocks_per_usec: 180
Enumerating buses...
APIC_CLUSTER: 0 enabled
Finding PCI configuration type.
PCI: Using configuration type 1
PCI_DOMAIN: 0000 enabled
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/7180] enabled
PCI: 00:01.0 [8086/7181] disabled
PCI: 00:07.0 [8086/7110] enabled
PCI: 00:07.1 [8086/7111] enabled
PCI: 00:07.2 [8086/7112] enabled
PCI: 00:07.3 [8086/7113] enabled
PNP: 03f0.0 enabled
PNP: 03f0.3 enabled
PNP: 03f0.4 enabled
PNP: 03f0.5 enabled
PNP: 03f0.7 enabled
PNP: 03f0.8 enabled
PCI: pci_scan_bus returning with max=000
done
Allocating resources...
Reading resources...
APIC: 00 missing read_resources
CPU: 00 missing read_resources
PNP: 03f0.0 missing read_resources
PNP: 03f0.3 missing read_resources
PNP: 03f0.4 missing read_resources
PNP: 03f0.5 missing read_resources
PNP: 03f0.7 missing read_resources
PNP: 03f0.8 missing read_resources
Done reading resources.
skipping PNP: 03f0.0@60 fixed resource, size=0!
skipping PNP: 03f0.0@70 fixed resource, size=0!
skipping PNP: 03f0.0@74 fixed resource, size=0!
skipping PNP: 03f0.3@60 fixed resource, size=0!
skipping PNP: 03f0.3@70 fixed resource, size=0!
skipping PNP: 03f0.4@60 fixed resource, size=0!
skipping PNP: 03f0.4@70 fixed resource, size=0!
skipping PNP: 03f0.5@60 fixed resource, size=0!
skipping PNP: 03f0.5@70 fixed resource, size=0!
skipping PNP: 03f0.7@60 fixed resource, size=0!
skipping PNP: 03f0.7@62 fixed resource, size=0!
skipping PNP: 03f0.7@70 fixed resource, size=0!
skipping PNP: 03f0.7@72 fixed resource, size=0!
Setting resources...
Setting RAM size to 128 MB
PCI: 00:00.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem
PNP: 03f0.0 missing set_resources
PNP: 03f0.3 missing set_resources
PNP: 03f0.4 missing set_resources
PNP: 03f0.5 missing set_resources
PNP: 03f0.7 missing set_resources
PCI: 00:07.1 20 <- [0x0000001020 - 0x000000102f] size 0x00000010 gran 0x04 io
PCI: 00:07.2 20 <- [0x0000001000 - 0x000000101f] size 0x00000020 gran 0x05 io
Done setting resources.
Done allocating resources.
Enabling resources...
PCI: 00:00.0 cmd <- 06
PCI: 00:07.0 cmd <- 07
PCI: 00:07.1 cmd <- 05
PCI: 00:07.2 cmd <- 01
PCI: 00:07.3 cmd <- 01
done.
Initializing devices...
Devices initialized
Initializing CBMEM area to 0x7ff0000 (65536 bytes)
Adding CBMEM entry as no. 1
Moving GDT to 07ff0200...ok
High Tables Base is 7ff0000.
Copying Interrupt Routing Table to 0x000f0000... done.
Adding CBMEM entry as no. 2
Copying Interrupt Routing Table to 0x07ff0400... done.
PIRQ table: 112 bytes.
Adding CBMEM entry as no. 3
Writing high table forward entry at 0x00000500
Wrote coreboot table at: 00000500 - 00000518  checksum e3df
New low_table_end: 0x00000518
Now going to write high coreboot table at 0x07ff1400
rom_table_end = 0x07ff1400
Adjust low_table_end from 0x00000518 to 0x00001000 
Adjust rom_table_end from 0x07ff1400 to 0x08000000 
Adding high table area
Wrote coreboot table at: 07ff1400 - 07ff1590  checksum 3bbe
coreboot table: 400 bytes.
 0. FREE SPACE 83ffbff7a1e90170 840f45ffffff58bd
 2. IRQ TABLE  07ff0400 00001000
 3. COREBOOT   07ff1400 00002000
Got a payload
Loading segment from rom address 0xfffe8238
  parameter section (skipped)
Loading segment from rom address 0xfffe8254
  data (compression=1)
  New segment dstaddr 0x100000 memsize 0x36710 srcaddr 0xfffe82e2 filesize 0x3e82
  (cleaned up) New segment addr 0x100000 size 0x36710 offset 0xfffe82e2 filesize 0x3e82
Loading segment from rom address 0xfffe8270
  Entry Point 0x00100000
Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000036710 filesz: 0x0000000000003e82
Post relocation: addr: 0x0000000007f958f0 memsz: 0x0000000000036710 filesz: 0x0000000000003e82
using LZMA
lzma: Decoding error = 1
Clearing Segment: addr: 0x0000000007f958f0 memsz: 0x0000000000036710
dest 07f958f0, end 07fcc000, bouncebuffer 7f958f0
move suffix around: from 7fb98f0, to 124000, amount: 12710
Jumping to boot code at 100000
coreboot-2.3 Thu Dec  3 10:33:42 CET 2009 rebooting...
clocks_per_usec: 180
Enumerating buses...
APIC_CLUSTER: 0 enabled
Finding PCI configuration type.
PCI: Using configuration type 1
PCI_DOMAIN: 0000 enabled
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/7180] enabled
PCI: 00:01.0 [8086/7181] disabled
PCI: 00:07.0 [8086/7110] enabled
PCI: 00:07.1 [8086/7111] enabled
PCI: 00:07.2 [8086/7112] enabled
PCI: 00:07.3 [8086/7113] enabled
PNP: 03f0.0 enabled
PNP: 03f0.3 enabled
PNP: 03f0.4 enabled
PNP: 03f0.5 enabled
PNP: 03f0.7 enabled
PNP: 03f0.8 enabled
PCI: pci_scan_bus returning with max=000
done
Allocating resources...
Reading resources...
APIC: 00 missing read_resources
CPU: 00 missing read_resources
PNP: 03f0.0 missing read_resources
PNP: 03f0.3 missing read_resources
PNP: 03f0.4 missing read_resources
PNP: 03f0.5 missing read_resources
PNP: 03f0.7 missing read_resources
PNP: 03f0.8 missing read_resources
Done reading resources.
skipping PNP: 03f0.0@60 fixed resource, size=0!
skipping PNP: 03f0.0@70 fixed resource, size=0!
skipping PNP: 03f0.0@74 fixed resource, size=0!
skipping PNP: 03f0.3@60 fixed resource, size=0!
skipping PNP: 03f0.3@70 fixed resource, size=0!
skipping PNP: 03f0.4@60 fixed resource, size=0!
skipping PNP: 03f0.4@70 fixed resource, size=0!
skipping PNP: 03f0.5@60 fixed resource, size=0!
skipping PNP: 03f0.5@70 fixed resource, size=0!
skipping PNP: 03f0.7@60 fixed resource, size=0!
skipping PNP: 03f0.7@62 fixed resource, size=0!
skipping PNP: 03f0.7@70 fixed resource, size=0!
skipping PNP: 03f0.7@72 fixed resource, size=0!
Setting resources...
Setting RAM size to 128 MB
PCI: 00:00.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem
PNP: 03f0.0 missing set_resources
PNP: 03f0.3 missing set_resources
PNP: 03f0.4 missing set_resources
PNP: 03f0.5 missing set_resources
PNP: 03f0.7 missing set_resources
PCI: 00:07.1 20 <- [0x0000001020 - 0x000000102f] size 0x00000010 gran 0x04 io
PCI: 00:07.2 20 <- [0x0000001000 - 0x000000101f] size 0x00000020 gran 0x05 io
Done setting resources.
Done allocating resources.
Enabling resources...
PCI: 00:00.0 cmd <- 06
PCI: 00:07.0 cmd <- 07
PCI: 00:07.1 cmd <- 05
PCI: 00:07.2 cmd <- 01
PCI: 00:07.3 cmd <- 01
done.
Initializing devices...
Devices initialized
Initializing CBMEM area to 0x7ff0000 (65536 bytes)
Adding CBMEM entry as no. 1
Moving GDT to 07ff0200...ok
High Tables Base is 7ff0000.
Copying Interrupt Routing Table to 0x000f0000... done.
Adding CBMEM entry as no. 2
Copying Interrupt Routing Table to 0x07ff0400... done.
PIRQ table: 112 bytes.
Adding CBMEM entry as no. 3
Writing high table forward entry at 0x00000500
Wrote coreboot table at: 00000500 - 00000518  checksum e3df
New low_table_end: 0x00000518
Now going to write high coreboot table at 0x07ff1400
rom_table_end = 0x07ff1400
Adjust low_table_end from 0x00000518 to 0x00001000 
Adjust rom_table_end from 0x07ff1400 to 0x08000000 
Adding high table area
Wrote coreboot table at: 07ff1400 - 07ff1590  checksum 3bbe
coreboot table: 400 bytes.
 0. FREE SPACE 83ffbff7a1e90170 840f45ffffff58bd
 2. IRQ TABLE  07ff0400 00001000
 3. COREBOOT   07ff1400 00002000
Got a payload
Loading segment from rom address 0xfffe8238
  parameter section (skipped)
Loading segment from rom address 0xfffe8254
  data (compression=1)
  New segment dstaddr 0x100000 memsize 0x36710 srcaddr 0xfffe82e2 filesize 0x3e82
  (cleaned up) New segment addr 0x100000 size 0x36710 offset 0xfffe82e2 filesize 0x3e82
Loading segment from rom address 0xfffe8270
  Entry Point 0x00100000
Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000036710 filesz: 0x0000000000003e82
Post relocation: addr: 0x0000000007f958f0 memsz: 0x0000000000036710 filesz: 0x0000000000003e82
using LZMA
lzma: Decoding error = 1
Clearing Segment: addr: 0x0000000007f958f0 memsz: 0x0000000000036710
dest 07f958f0, end 07fcc000, bouncebuffer 7f958f0
move suffix around: from 7fb98f0, to 124000, amount: 12710
Jumping to boot code at 100000