On Thu, Sep 19, 2019 at 11:12 AM Nico Huber <nico.h@gmx.de> wrote:
>
> On 12.09.19 18:42, Patrick Georgi wrote:
> > On Thu, Sep 12, 2019 at 07:20:49PM +0300, Kyösti Mälkki wrote:
> >> Would "some people" or these "advocates" be willing to elaborate?
> > I CC'd Nico and Martin because I seem to remember that we talked
> > about AGESA (and its quality and/or life cycle). Nico, for example,
> > seems to advocate scrapping AGESA to replace it with a rewrite ;-)
>
> Ah, yes. I might have said something. When talking about AGESA ports,
> I most probably meant the hook-up in coreboot, not the vendorcode/.
> I usually don't look at the latter.
>
> I would love to see a clean rewrite and assume that I proposed this
> when somebody asked what could/should be done. However, I don't see
> it as a requirement. Also, we have much more worrisome code in the
> tree (e.g. KGPE-D16 and surrounding code, suffering from undefined
> behavior, #including of .c files etc.).
>
> Nico

Interesting. In terms of lines of code, probably 75% of AGESA glue
logic in ports has already been removed. But I agree, aside from
release requirements, there is lots left that could be done. There is
essentially no interest for new board ports on AGESA/binaryPI, these
platforms have mostly survived in the tree due to commercial support
to maintain them.

Kyösti Mälkki
_______________________________________________
coreboot mailing list -- coreboot@coreboot.org
To unsubscribe send an email to coreboot-leave@coreboot.org