Hi Nico, All,

I tried an FSP.fd with debug infro I got from Intel. 
For this purpose I had to change the "FSP location in CBFS" to 0xFFFB0000 (default was 0xFFFC0000) 
Following is the information I got via UART:

============= PEIM FSP v1.0 (VLYVIEW0 v0.0.3.5) =============
Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE
Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
The 0th FV start address is 0x000FFFE0400, size is 0x00017C00, handle is 0x0
Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38
Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6
Install PPI: DBE23AA9-A345-4B97-85B6-B226F1617389

Install PPI: 06E81C58-4AD7-44BC-8390-F10265F72480
Install PPI: 01F34D25-4DE2-23AD-3FF3-36353FF323F1

Install PPI: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: FFFE0FE4
The 1th FV start address is 0x000FFFB0000, size is 0x0002F400, handle is 0xFFFB0000

Install PPI: A55D6970-1306-440C-8C72-8F51FAFB2926

PcdMrcInitTsegSize = 8
PcdMrcInitMmioSize = 800
PcdMrcInitSPDAddr1 = A0
PcdMrcInitSPDAddr2 = A2
Setting BootMode to 0
Install PPI: 1F4C6F90-B06B-48D8-A201-BAE5F1CD7D56
Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE
About to call MrcInit();
BayleyBay Platform Type
AutoSelfRefreshEnable =  0x2
RID = 0x11.
Reg_EFF_DualCH_EN = 0x100301C0.
CurrentMrcData.BootMode = 4
C0.D0: SPD not present.
C1.D0: SPD not present.
=============================================================================
What should be my next step ?
Do you think the above info is what I need in order to configure FSP ?

Thank you,
Zvika 

On Sat, Feb 9, 2019 at 5:33 PM Gregg Levine <gregg.drwho8@gmail.com> wrote:
Hello!
Nico you said here, "Also, generally, you need a build of FSP with
debugging enabled. The  public builds usually are not."

I agree that the public builds usually are not so enabled. What would
need to be done to enable such a function?

Obviously to further dig into these issues, I'm going to need to be
more involved, but, ah, that's not doable this month.
-----
Gregg C Levine gregg.drwho8@gmail.com"This signature fought the Time
Wars, time and again."
On Sat, Feb 9, 2019 at 7:25 AM Nico Huber <nico.h@gmx.de> wrote:
>
> Hi Zvika,
>
> On 09.02.19 12:23, Zvi Vered wrote:
> > I noticed that starting from version 4.9, I can set the debug level of FSP.
> >
> > I downloaded  FSP for Bay trail and used Intel's BCT to modify it.
> > But coreboot hangs after calling to the FSP binary.
> >
> > How can I use the "FSP debug level" ?
>
> This option is only implemented for the Broadwell-DE FSP. I've pushed a
> patch to move it accordingly[1], sorry for the confusion.
>
> Also, generally, you need a build of FSP with debugging enabled. The
> public builds usually are not.
>
> Nico
>
> [1] https://review.coreboot.org/c/coreboot/+/31300
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