ù LinuxBIOS-1.1.5.0-Fallback Di Okt 21 13:16:18 CEST 2003 starting... setting up resource map.... done. Enabling routing table for node 00000000 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done SMBus controller enabled Ram1.00 setting up CPU00 northbridge registers done. Ram2.00 disabling dimm01 disabling dimm01 133Mhz disabling dimm01 Interleaved RAM: 0x00040000 KB Ram3 Initializing memory: done Ram4 Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.5.0-Fallback Di Okt 21 13:16:18 CEST 2003 booting... Finding PCI configuration type. PCI: Using configuration type 1 Enumerating: AMD K8 Northbridge malloc Enter, size 256, free_mem_ptr 00015a44 malloc 0x00015a44 path (00015a44) PCI: 00:18.0 parent: (0000ea20) Root Device path (00015a44) PCI: 00:18.0 identical parent: (0000ea20) Root Device path (00015a44) PCI: 00:18.0 identical parent: (0000ea20) Root Device malloc Enter, size 256, free_mem_ptr 00015b44 malloc 0x00015b44 path (00015b44) PCI: 00:18.1 parent: (0000ea20) Root Device malloc Enter, size 256, free_mem_ptr 00015c44 malloc 0x00015c44 path (00015c44) PCI: 00:18.2 parent: (0000ea20) Root Device malloc Enter, size 256, free_mem_ptr 00015d44 malloc 0x00015d44 path (00015d44) PCI: 00:18.3 parent: (0000ea20) Root Device Enumerating: AMD K8 malloc Enter, size 256, free_mem_ptr 00015e44 malloc 0x00015e44 path (00015e44) PCI: 00:00.0 parent: (00015a44) PCI: 00:18.0 malloc Enter, size 256, free_mem_ptr 00015f44 malloc 0x00015f44 path (00015f44) PCI: 00:01.0 parent: (00015a44) PCI: 00:18.0 Enumerating: AMD 8111 malloc Enter, size 256, free_mem_ptr 00016044 malloc 0x00016044 path (00016044) PCI: 00:00.0 parent: (00015a44) PCI: 00:18.0 malloc Enter, size 256, free_mem_ptr 00016144 malloc 0x00016144 path (00016144) PCI: 00:01.0 parent: (00015a44) PCI: 00:18.0 malloc Enter, size 256, free_mem_ptr 00016244 malloc 0x00016244 path (00016244) PCI: 00:01.1 parent: (00015a44) PCI: 00:18.0 malloc Enter, size 256, free_mem_ptr 00016344 malloc 0x00016344 path (00016344) PCI: 00:01.2 parent: (00015a44) PCI: 00:18.0 malloc Enter, size 256, free_mem_ptr 00016444 malloc 0x00016444 path (00016444) PCI: 00:01.3 parent: (00015a44) PCI: 00:18.0 malloc Enter, size 256, free_mem_ptr 00016544 malloc 0x00016544 path (00016544) PCI: 00:01.5 parent: (00015a44) PCI: 00:18.0 malloc Enter, size 256, free_mem_ptr 00016644 malloc 0x00016644 path (00016644) PCI: 00:01.6 parent: (00015a44) PCI: 00:18.0 malloc Enter, size 256, free_mem_ptr 00016744 malloc 0x00016744 path (00016744) PCI: 00:00.0 parent: (00016044) PCI: 00:00.0 malloc Enter, size 256, free_mem_ptr 00016844 malloc 0x00016844 path (00016844) PCI: 00:00.1 parent: (00016044) PCI: 00:00.0 malloc Enter, size 256, free_mem_ptr 00016944 malloc 0x00016944 path (00016944) PCI: 00:00.2 parent: (00016044) PCI: 00:00.0 malloc Enter, size 256, free_mem_ptr 00016a44 malloc 0x00016a44 path (00016a44) PCI: 00:01.0 parent: (00016044) PCI: 00:00.0 Enumerating buses...PCI: pci_scan_bus for bus 0 Read config 32 bus 0,devfn 0xc0,reg 0x0,val 0x11001022 Read config 8 bus 0,devfn 0xc0,reg 0xe,val 0x80 Read config 32 bus 0,devfn 0xc0,reg 0x8,val 0x6000000 PCI: 00:18.0 [1022/1100] enabled Read config 32 bus 0,devfn 0xc1,reg 0x0,val 0x11011022 Read config 8 bus 0,devfn 0xc1,reg 0xe,val 0x80 Read config 32 bus 0,devfn 0xc1,reg 0x8,val 0x6000000 PCI: 00:18.1 [1022/1101] enabled Read config 32 bus 0,devfn 0xc2,reg 0x0,val 0x11021022 Read config 8 bus 0,devfn 0xc2,reg 0xe,val 0x80 Read config 32 bus 0,devfn 0xc2,reg 0x8,val 0x6000000 PCI: 00:18.2 [1022/1102] enabled Read config 32 bus 0,devfn 0xc3,reg 0x0,val 0x11031022 Read config 8 bus 0,devfn 0xc3,reg 0xe,val 0x80 Read config 32 bus 0,devfn 0xc3,reg 0x8,val 0x6000000 PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled Read config 32 bus 0,devfn 0xc4,reg 0x0,val 0xffffffff PCI: devfn 0xc4, bad id 0xffffffff Read config 32 bus 0,devfn 0xc5,reg 0x0,val 0xffffffff PCI: devfn 0xc5, bad id 0xffffffff Read config 32 bus 0,devfn 0xc6,reg 0x0,val 0xffffffff PCI: devfn 0xc6, bad id 0xffffffff Read config 32 bus 0,devfn 0xc7,reg 0x0,val 0xffffffff PCI: devfn 0xc7, bad id 0xffffffff Read config 32 bus 0,devfn 0xc8,reg 0x0,val 0xffffffff PCI: devfn 0xc8, bad id 0xffffffff Read config 32 bus 0,devfn 0xd0,reg 0x0,val 0xffffffff PCI: devfn 0xd0, bad id 0xffffffff Read config 32 bus 0,devfn 0xd8,reg 0x0,val 0xffffffff PCI: devfn 0xd8, bad id 0xffffffff Read config 32 bus 0,devfn 0xe0,reg 0x0,val 0xffffffff PCI: devfn 0xe0, bad id 0xffffffff Read config 32 bus 0,devfn 0xe8,reg 0x0,val 0xffffffff PCI: devfn 0xe8, bad id 0xffffffff Read config 32 bus 0,devfn 0xf0,reg 0x0,val 0xffffffff PCI: devfn 0xf0, bad id 0xffffffff Read config 32 bus 0,devfn 0xf8,reg 0x0,val 0xffffffff PCI: devfn 0xf8, bad id 0xffffffff amdk8_scan_chains max: 0 starting... Read config 32 bus 0,devfn 0xc0,reg 0x98,val 0x7 Read config 32 bus 0,devfn 0xc0,reg 0x98,val 0x7 Read config 32 bus 0,devfn 0xc1,reg 0xe0,val 0xff000003 Read config 32 bus 0,devfn 0xc0,reg 0x94,val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0xe0,val 0xff000003 Write config 32 bus 0, devfn 0xc0, reg 0x94, val 0xff0100 Write config 32 bus 0, devfn 0xc1, reg 0xe0, val 0xff010003 Hyper transport scan link: 0 max: 1 Read config 32 bus 1,devfn 0x0,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x8,reg 0x0,val 0x74541022 Read config 8 bus 1,devfn 0x8,reg 0xe,val 0x0 Read config 8 bus 1,devfn 0x8,reg 0x34,val 0xa0 Read config 8 bus 1,devfn 0x8,reg 0xa0,val 0x2 Capability: 0x02 @ 0xa0 Read config 8 bus 1,devfn 0x8,reg 0xa1,val 0xc0 Read config 8 bus 1,devfn 0x8,reg 0xc0,val 0x8 Capability: 0x08 @ 0xc0 Read config 16 bus 1,devfn 0x8,reg 0xc2,val 0x61 flags: 0x0061 Read config 16 bus 1,devfn 0x8,reg 0xc2,val 0x61 Write config 16 bus 1, devfn 0x8, reg 0xc2, val 0x60 Collapsing PCI: 01:01.0 [1022/7454] Read config 32 bus 1,devfn 0x10,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x18,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x20,reg 0x0,val 0x74601022 Read config 8 bus 1,devfn 0x20,reg 0xe,val 0x1 Read config 8 bus 1,devfn 0x20,reg 0x34,val 0xc0 Read config 8 bus 1,devfn 0x20,reg 0xc0,val 0x8 Capability: 0x08 @ 0xc0 Read config 16 bus 1,devfn 0x20,reg 0xc2,val 0x84 flags: 0x0084 Read config 16 bus 1,devfn 0x20,reg 0xc2,val 0x84 Write config 16 bus 1, devfn 0x20, reg 0xc2, val 0x80 Collapsing PCI: 01:04.0 [1022/7460] Read config 32 bus 1,devfn 0x28,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x30,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x38,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x40,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x48,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x50,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x58,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x60,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x68,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x70,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x78,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x80,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x88,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x90,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x98,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0xa0,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0xa8,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0xb0,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0xb8,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0xc0,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0xc8,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0xd0,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0xd8,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0xe0,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0xe8,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0xf0,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0xf8,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x0,reg 0x0,val 0x74541022 Read config 8 bus 1,devfn 0x0,reg 0xe,val 0x0 Read config 32 bus 1,devfn 0x0,reg 0x8,val 0x6000013 Read config 8 bus 1,devfn 0x0,reg 0x34,val 0xa0 Read config 8 bus 1,devfn 0x0,reg 0xa0,val 0x2 Capability: 0x02 @ 0xa0 Read config 8 bus 1,devfn 0x0,reg 0xa1,val 0xc0 Read config 8 bus 1,devfn 0x0,reg 0xc0,val 0x8 Capability: 0x08 @ 0xc0 Read config 16 bus 1,devfn 0x0,reg 0xc2,val 0x60 flags: 0x0060 Read config 16 bus 1,devfn 0x0,reg 0xc2,val 0x60 Write config 16 bus 1, devfn 0x0, reg 0xc2, val 0x61 PCI: 01:01.0 count: 0003 static_count: 0002 Read config 16 bus 1,devfn 0x8,reg 0xce,val 0x35 Read config 16 bus 0,devfn 0xc0,reg 0x8a,val 0x8075 Read config 8 bus 1,devfn 0x8,reg 0xc6,val 0x11 Read config 8 bus 0,devfn 0xc0,reg 0x86,val 0x11 Read config 8 bus 1,devfn 0x8,reg 0xcd,val 0x0 Write config 8 bus 1, devfn 0x8, reg 0xcd, val 0x4 HyperT FreqP old 0 new 4 Read config 8 bus 1,devfn 0x8,reg 0xc7,val 0x0 Write config 8 bus 1, devfn 0x8, reg 0xc7, val 0x11 HyperT widthP old 0 new 11 Read config 8 bus 0,devfn 0xc0,reg 0x89,val 0x0 Write config 8 bus 0, devfn 0xc0, reg 0x89, val 0x4 HyperT freqU old 0 new 4 Read config 8 bus 0,devfn 0xc0,reg 0x87,val 0x0 Write config 8 bus 0, devfn 0xc0, reg 0x87, val 0x11 HyperT widthU old 0 new 11 PCI: 01:01.0 [1022/7454] enabled next_unitid: 0004 Read config 32 bus 1,devfn 0x0,reg 0x0,val 0x74601022 Read config 8 bus 1,devfn 0x0,reg 0xe,val 0x1 Read config 32 bus 1,devfn 0x0,reg 0x8,val 0x6040007 Read config 8 bus 1,devfn 0x0,reg 0x34,val 0xc0 Read config 8 bus 1,devfn 0x0,reg 0xc0,val 0x8 Capability: 0x08 @ 0xc0 Read config 16 bus 1,devfn 0x0,reg 0xc2,val 0x80 flags: 0x0080 Read config 16 bus 1,devfn 0x0,reg 0xc2,val 0x80 Write config 16 bus 1, devfn 0x0, reg 0xc2, val 0x84 PCI: 01:04.0 count: 0004 static_count: 0002 Read config 16 bus 1,devfn 0x20,reg 0xce,val 0x1 Read config 16 bus 1,devfn 0x8,reg 0xd2,val 0x35 Read config 8 bus 1,devfn 0x20,reg 0xc6,val 0x0 Read config 8 bus 1,devfn 0x8,reg 0xca,val 0x0 Read config 8 bus 1,devfn 0x20,reg 0xcd,val 0x0 Read config 8 bus 1,devfn 0x20,reg 0xc7,val 0x0 Read config 8 bus 1,devfn 0x8,reg 0xd1,val 0x0 Read config 8 bus 1,devfn 0x8,reg 0xcb,val 0x0 PCI: 01:04.0 [1022/7460] enabled next_unitid: 0008 Read config 32 bus 1,devfn 0x0,reg 0x0,val 0xffffffff HyperT reset needed LinuxBIOS-1.1.5.0-Fallback Di Okt 21 13:16:18 CEST 2003 starting... setting up resource map.... done. Enabling routing table for node 00000000 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done SMBus controller enabled Ram1.00 setting up CPU00 northbridge registers done. Ram2.00 disabling dimm01 disabling dimm01 133Mhz disabling dimm01 Interleaved RAM: 0x00040000 KB Ram3 Initializing memory: done Ram4 Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.5.0-Fallback Di Okt 21 13:16:18 CEST 2003 booting... Finding PCI configuration type. PCI: Using configuration type 1 Enumerating: AMD K8 Northbridge malloc Enter, size 256, free_mem_ptr 00015a44 malloc 0x00015a44 path (00015a44) PCI: 00:18.0 parent: (0000ea20) Root Device path (00015a44) PCI: 00:18.0 identical parent: (0000ea20) Root Device path (00015a44) PCI: 00:18.0 identical parent: (0000ea20) Root Device malloc Enter, size 256, free_mem_ptr 00015b44 malloc 0x00015b44 path (00015b44) PCI: 00:18.1 parent: (0000ea20) Root Device malloc Enter, size 256, free_mem_ptr 00015c44 malloc 0x00015c44 path (00015c44) PCI: 00:18.2 parent: (0000ea20) Root Device malloc Enter, size 256, free_mem_ptr 00015d44 malloc 0x00015d44 path (00015d44) PCI: 00:18.3 parent: (0000ea20) Root Device Enumerating: AMD K8 malloc Enter, size 256, free_mem_ptr 00015e44 malloc 0x00015e44 path (00015e44) PCI: 00:00.0 parent: (00015a44) PCI: 00:18.0 malloc Enter, size 256, free_mem_ptr 00015f44 malloc 0x00015f44 path (00015f44) PCI: 00:01.0 parent: (00015a44) PCI: 00:18.0 Enumerating: AMD 8111 malloc Enter, size 256, free_mem_ptr 00016044 malloc 0x00016044 path (00016044) PCI: 00:00.0 parent: (00015a44) PCI: 00:18.0 malloc Enter, size 256, free_mem_ptr 00016144 malloc 0x00016144 path (00016144) PCI: 00:01.0 parent: (00015a44) PCI: 00:18.0 malloc Enter, size 256, free_mem_ptr 00016244 malloc 0x00016244 path (00016244) PCI: 00:01.1 parent: (00015a44) PCI: 00:18.0 malloc Enter, size 256, free_mem_ptr 00016344 malloc 0x00016344 path (00016344) PCI: 00:01.2 parent: (00015a44) PCI: 00:18.0 malloc Enter, size 256, free_mem_ptr 00016444 malloc 0x00016444 path (00016444) PCI: 00:01.3 parent: (00015a44) PCI: 00:18.0 malloc Enter, size 256, free_mem_ptr 00016544 malloc 0x00016544 path (00016544) PCI: 00:01.5 parent: (00015a44) PCI: 00:18.0 malloc Enter, size 256, free_mem_ptr 00016644 malloc 0x00016644 path (00016644) PCI: 00:01.6 parent: (00015a44) PCI: 00:18.0 malloc Enter, size 256, free_mem_ptr 00016744 malloc 0x00016744 path (00016744) PCI: 00:00.0 parent: (00016044) PCI: 00:00.0 malloc Enter, size 256, free_mem_ptr 00016844 malloc 0x00016844 path (00016844) PCI: 00:00.1 parent: (00016044) PCI: 00:00.0 malloc Enter, size 256, free_mem_ptr 00016944 malloc 0x00016944 path (00016944) PCI: 00:00.2 parent: (00016044) PCI: 00:00.0 malloc Enter, size 256, free_mem_ptr 00016a44 malloc 0x00016a44 path (00016a44) PCI: 00:01.0 parent: (00016044) PCI: 00:00.0 Enumerating buses...PCI: pci_scan_bus for bus 0 Read config 32 bus 0,devfn 0xc0,reg 0x0,val 0x11001022 Read config 8 bus 0,devfn 0xc0,reg 0xe,val 0x80 Read config 32 bus 0,devfn 0xc0,reg 0x8,val 0x6000000 PCI: 00:18.0 [1022/1100] enabled Read config 32 bus 0,devfn 0xc1,reg 0x0,val 0x11011022 Read config 8 bus 0,devfn 0xc1,reg 0xe,val 0x80 Read config 32 bus 0,devfn 0xc1,reg 0x8,val 0x6000000 PCI: 00:18.1 [1022/1101] enabled Read config 32 bus 0,devfn 0xc2,reg 0x0,val 0x11021022 Read config 8 bus 0,devfn 0xc2,reg 0xe,val 0x80 Read config 32 bus 0,devfn 0xc2,reg 0x8,val 0x6000000 PCI: 00:18.2 [1022/1102] enabled Read config 32 bus 0,devfn 0xc3,reg 0x0,val 0x11031022 Read config 8 bus 0,devfn 0xc3,reg 0xe,val 0x80 Read config 32 bus 0,devfn 0xc3,reg 0x8,val 0x6000000 PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled Read config 32 bus 0,devfn 0xc4,reg 0x0,val 0xffffffff PCI: devfn 0xc4, bad id 0xffffffff Read config 32 bus 0,devfn 0xc5,reg 0x0,val 0xffffffff PCI: devfn 0xc5, bad id 0xffffffff Read config 32 bus 0,devfn 0xc6,reg 0x0,val 0xffffffff PCI: devfn 0xc6, bad id 0xffffffff Read config 32 bus 0,devfn 0xc7,reg 0x0,val 0xffffffff PCI: devfn 0xc7, bad id 0xffffffff Read config 32 bus 0,devfn 0xc8,reg 0x0,val 0xffffffff PCI: devfn 0xc8, bad id 0xffffffff Read config 32 bus 0,devfn 0xd0,reg 0x0,val 0xffffffff PCI: devfn 0xd0, bad id 0xffffffff Read config 32 bus 0,devfn 0xd8,reg 0x0,val 0xffffffff PCI: devfn 0xd8, bad id 0xffffffff Read config 32 bus 0,devfn 0xe0,reg 0x0,val 0xffffffff PCI: devfn 0xe0, bad id 0xffffffff Read config 32 bus 0,devfn 0xe8,reg 0x0,val 0xffffffff PCI: devfn 0xe8, bad id 0xffffffff Read config 32 bus 0,devfn 0xf0,reg 0x0,val 0xffffffff PCI: devfn 0xf0, bad id 0xffffffff Read config 32 bus 0,devfn 0xf8,reg 0x0,val 0xffffffff PCI: devfn 0xf8, bad id 0xffffffff amdk8_scan_chains max: 0 starting... Read config 32 bus 0,devfn 0xc0,reg 0x98,val 0x7 Read config 32 bus 0,devfn 0xc0,reg 0x98,val 0x7 Read config 32 bus 0,devfn 0xc1,reg 0xe0,val 0xff000003 Read config 32 bus 0,devfn 0xc0,reg 0x94,val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0xe0,val 0xff000003 Write config 32 bus 0, devfn 0xc0, reg 0x94, val 0xff0100 Write config 32 bus 0, devfn 0xc1, reg 0xe0, val 0xff010003 Hyper transport scan link: 0 max: 1 Read config 32 bus 1,devfn 0x0,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x8,reg 0x0,val 0x74541022 Read config 8 bus 1,devfn 0x8,reg 0xe,val 0x0 Read config 8 bus 1,devfn 0x8,reg 0x34,val 0xa0 Read config 8 bus 1,devfn 0x8,reg 0xa0,val 0x2 Capability: 0x02 @ 0xa0 Read config 8 bus 1,devfn 0x8,reg 0xa1,val 0xc0 Read config 8 bus 1,devfn 0x8,reg 0xc0,val 0x8 Capability: 0x08 @ 0xc0 Read config 16 bus 1,devfn 0x8,reg 0xc2,val 0x61 flags: 0x0061 Read config 16 bus 1,devfn 0x8,reg 0xc2,val 0x61 Write config 16 bus 1, devfn 0x8, reg 0xc2, val 0x60 Collapsing PCI: 01:01.0 [1022/7454] Read config 32 bus 1,devfn 0x10,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x18,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x20,reg 0x0,val 0x74601022 Read config 8 bus 1,devfn 0x20,reg 0xe,val 0x1 Read config 8 bus 1,devfn 0x20,reg 0x34,val 0xc0 Read config 8 bus 1,devfn 0x20,reg 0xc0,val 0x8 Capability: 0x08 @ 0xc0 Read config 16 bus 1,devfn 0x20,reg 0xc2,val 0x84 flags: 0x0084 Read config 16 bus 1,devfn 0x20,reg 0xc2,val 0x84 Write config 16 bus 1, devfn 0x20, reg 0xc2, val 0x80 Collapsing PCI: 01:04.0 [1022/7460] Read config 32 bus 1,devfn 0x28,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x30,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x38,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x40,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x48,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x50,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x58,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x60,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x68,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x70,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x78,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x80,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x88,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x90,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x98,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0xa0,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0xa8,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0xb0,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0xb8,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0xc0,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0xc8,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0xd0,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0xd8,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0xe0,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0xe8,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0xf0,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0xf8,reg 0x0,val 0xffffffff Read config 32 bus 1,devfn 0x0,reg 0x0,val 0x74541022 Read config 8 bus 1,devfn 0x0,reg 0xe,val 0x0 Read config 32 bus 1,devfn 0x0,reg 0x8,val 0x6000013 Read config 8 bus 1,devfn 0x0,reg 0x34,val 0xa0 Read config 8 bus 1,devfn 0x0,reg 0xa0,val 0x2 Capability: 0x02 @ 0xa0 Read config 8 bus 1,devfn 0x0,reg 0xa1,val 0xc0 Read config 8 bus 1,devfn 0x0,reg 0xc0,val 0x8 Capability: 0x08 @ 0xc0 Read config 16 bus 1,devfn 0x0,reg 0xc2,val 0x60 flags: 0x0060 Read config 16 bus 1,devfn 0x0,reg 0xc2,val 0x60 Write config 16 bus 1, devfn 0x0, reg 0xc2, val 0x61 PCI: 01:01.0 count: 0003 static_count: 0002 Read config 16 bus 1,devfn 0x8,reg 0xce,val 0x35 Read config 16 bus 0,devfn 0xc0,reg 0x8a,val 0x8075 Read config 8 bus 1,devfn 0x8,reg 0xc6,val 0x11 Read config 8 bus 0,devfn 0xc0,reg 0x86,val 0x11 Read config 8 bus 1,devfn 0x8,reg 0xcd,val 0x4 Read config 8 bus 1,devfn 0x8,reg 0xc7,val 0x11 Read config 8 bus 0,devfn 0xc0,reg 0x89,val 0x4 Read config 8 bus 0,devfn 0xc0,reg 0x87,val 0x11 PCI: 01:01.0 [1022/7454] enabled next_unitid: 0004 Read config 32 bus 1,devfn 0x0,reg 0x0,val 0x74601022 Read config 8 bus 1,devfn 0x0,reg 0xe,val 0x1 Read config 32 bus 1,devfn 0x0,reg 0x8,val 0x6040007 Read config 8 bus 1,devfn 0x0,reg 0x34,val 0xc0 Read config 8 bus 1,devfn 0x0,reg 0xc0,val 0x8 Capability: 0x08 @ 0xc0 Read config 16 bus 1,devfn 0x0,reg 0xc2,val 0x80 flags: 0x0080 Read config 16 bus 1,devfn 0x0,reg 0xc2,val 0x80 Write config 16 bus 1, devfn 0x0, reg 0xc2, val 0x84 PCI: 01:04.0 count: 0004 static_count: 0002 Read config 16 bus 1,devfn 0x20,reg 0xce,val 0x1 Read config 16 bus 1,devfn 0x8,reg 0xd2,val 0x35 Read config 8 bus 1,devfn 0x20,reg 0xc6,val 0x0 Read config 8 bus 1,devfn 0x8,reg 0xca,val 0x0 Read config 8 bus 1,devfn 0x20,reg 0xcd,val 0x0 Read config 8 bus 1,devfn 0x20,reg 0xc7,val 0x0 Read config 8 bus 1,devfn 0x8,reg 0xd1,val 0x0 Read config 8 bus 1,devfn 0x8,reg 0xcb,val 0x0 PCI: 01:04.0 [1022/7460] enabled next_unitid: 0008 Read config 32 bus 1,devfn 0x0,reg 0x0,val 0xffffffff HyperT reset not needed PCI: pci_scan_bus for bus 1 Read config 32 bus 1,devfn 0x0,reg 0x0,val 0xffffffff PCI: devfn 0x0, bad id 0xffffffff Read config 32 bus 1,devfn 0x8,reg 0x0,val 0x74541022 Read config 8 bus 1,devfn 0x8,reg 0xe,val 0x0 Read config 32 bus 1,devfn 0x8,reg 0x8,val 0x6000013 PCI: 01:01.0 [1022/7454] ops Read config 32 bus 1,devfn 0x8,reg 0xa8,val 0x0 Write config 32 bus 1, devfn 0x8, reg 0xa8, val 0x100 Read config 32 bus 1,devfn 0x8,reg 0xc4,val 0x11110020 Write config 32 bus 1, devfn 0x8, reg 0xc4, val 0x1b110020 Read config 32 bus 1,devfn 0x8,reg 0xcc,val 0x350422 Write config 32 bus 1, devfn 0x8, reg 0xcc, val 0x350422 Read config 32 bus 1,devfn 0x8,reg 0x4,val 0x2100000 Write config 32 bus 1, devfn 0x8, reg 0x4, val 0x2100006 PCI: 01:01.0 [1022/7454] enabled Read config 32 bus 1,devfn 0x10,reg 0x0,val 0x74551022 Read config 8 bus 1,devfn 0x10,reg 0xe,val 0x1 Read config 32 bus 1,devfn 0x10,reg 0x8,val 0x6040013 PCI: 01:02.0 [1022/7455] bus ops PCI: 01:02.0 [1022/7455] enabled Read config 32 bus 1,devfn 0x18,reg 0x0,val 0xffffffff PCI: devfn 0x18, bad id 0xffffffff Read config 32 bus 1,devfn 0x20,reg 0x0,val 0x74601022 Read config 8 bus 1,devfn 0x20,reg 0xe,val 0x1 Read config 32 bus 1,devfn 0x20,reg 0x8,val 0x6040007 PCI: 01:04.0 [1022/7460] enabled Read config 32 bus 1,devfn 0x28,reg 0x0,val 0x74681022 Read config 8 bus 1,devfn 0x28,reg 0xe,val 0x80 Read config 32 bus 1,devfn 0x28,reg 0x8,val 0x6010005 PCI: 01:05.0 [1022/7468] bus ops Read config 16 bus 1,devfn 0x28,reg 0x48,val 0xffff PCI: 01:05.0 [1022/7468] enabled Read config 16 bus 1,devfn 0x28,reg 0x48,val 0xffff Read config 32 bus 1,devfn 0x29,reg 0x0,val 0x74691022 Read config 8 bus 1,devfn 0x29,reg 0xe,val 0x0 Read config 32 bus 1,devfn 0x29,reg 0x8,val 0x1018a03 PCI: 01:05.1 [1022/7469] ops PCI: 01:05.1 [1022/7469] enabled Read config 16 bus 1,devfn 0x28,reg 0x48,val 0xffff Read config 32 bus 1,devfn 0x2a,reg 0x0,val 0x746a1022 Read config 8 bus 1,devfn 0x2a,reg 0xe,val 0x0 Read config 32 bus 1,devfn 0x2a,reg 0x8,val 0xc050002 PCI: 01:05.2 [1022/746a] enabled Read config 16 bus 1,devfn 0x28,reg 0x48,val 0xffff Read config 32 bus 1,devfn 0x2b,reg 0x0,val 0x746b1022 Read config 8 bus 1,devfn 0x2b,reg 0xe,val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x8,val 0x5 PCI: 01:05.3 [1022/746b] ops Read config 16 bus 1,devfn 0x28,reg 0x48,val 0xffff PCI: 01:05.3 [1022/746b] enabled Read config 32 bus 1,devfn 0x2c,reg 0x0,val 0x0 PCI: devfn 0x2c, bad id 0x0 Read config 16 bus 1,devfn 0x28,reg 0x48,val 0xffff Read config 32 bus 1,devfn 0x2d,reg 0x0,val 0x746d1022 Read config 8 bus 1,devfn 0x2d,reg 0xe,val 0x0 Read config 32 bus 1,devfn 0x2d,reg 0x8,val 0x4010003 PCI: 01:05.5 [1022/746d] enabled Read config 16 bus 1,devfn 0x28,reg 0x48,val 0xffff Read config 32 bus 1,devfn 0x2e,reg 0x0,val 0x746e1022 Read config 8 bus 1,devfn 0x2e,reg 0xe,val 0x0 Read config 32 bus 1,devfn 0x2e,reg 0x8,val 0x7030003 PCI: 01:05.6 [1022/746e] enabled Read config 32 bus 1,devfn 0x2f,reg 0x0,val 0x0 PCI: devfn 0x2f, bad id 0x0 Read config 32 bus 1,devfn 0x30,reg 0x0,val 0xffffffff PCI: devfn 0x30, bad id 0xffffffff Read config 32 bus 1,devfn 0x38,reg 0x0,val 0xffffffff PCI: devfn 0x38, bad id 0xffffffff Read config 32 bus 1,devfn 0x40,reg 0x0,val 0xffffffff PCI: devfn 0x40, bad id 0xffffffff Read config 16 bus 1,devfn 0x10,reg 0x4,val 0x0 Write config 16 bus 1, devfn 0x10, reg 0x4, val 0x0 Write config 16 bus 1, devfn 0x10, reg 0x6, val 0xffff Read config 32 bus 1,devfn 0x10,reg 0x18,val 0x0 Write config 32 bus 1, devfn 0x10, reg 0x18, val 0xff0201 PCI: pci_scan_bus for bus 2 Read config 32 bus 2,devfn 0x0,reg 0x0,val 0x51571002 malloc Enter, size 256, free_mem_ptr 00016b44 malloc 0x00016b44 Read config 8 bus 2,devfn 0x0,reg 0xe,val 0x0 Read config 32 bus 2,devfn 0x0,reg 0x8,val 0x3000000 PCI: 02:00.0 [1002/5157] enabled Read config 32 bus 2,devfn 0x8,reg 0x0,val 0xffffffff PCI: devfn 0x8, bad id 0xffffffff Read config 32 bus 2,devfn 0x10,reg 0x0,val 0xffffffff PCI: devfn 0x10, bad id 0xffffffff Read config 32 bus 2,devfn 0x18,reg 0x0,val 0xffffffff PCI: devfn 0x18, bad id 0xffffffff Read config 32 bus 2,devfn 0x20,reg 0x0,val 0xffffffff PCI: devfn 0x20, bad id 0xffffffff Read config 32 bus 2,devfn 0x28,reg 0x0,val 0xffffffff PCI: devfn 0x28, bad id 0xffffffff Read config 32 bus 2,devfn 0x30,reg 0x0,val 0xffffffff PCI: devfn 0x30, bad id 0xffffffff Read config 32 bus 2,devfn 0x38,reg 0x0,val 0xffffffff PCI: devfn 0x38, bad id 0xffffffff Read config 32 bus 2,devfn 0x40,reg 0x0,val 0xffffffff PCI: devfn 0x40, bad id 0xffffffff Read config 32 bus 2,devfn 0x48,reg 0x0,val 0xffffffff PCI: devfn 0x48, bad id 0xffffffff Read config 32 bus 2,devfn 0x50,reg 0x0,val 0xffffffff PCI: devfn 0x50, bad id 0xffffffff Read config 32 bus 2,devfn 0x58,reg 0x0,val 0xffffffff PCI: devfn 0x58, bad id 0xffffffff Read config 32 bus 2,devfn 0x60,reg 0x0,val 0xffffffff PCI: devfn 0x60, bad id 0xffffffff Read config 32 bus 2,devfn 0x68,reg 0x0,val 0xffffffff PCI: devfn 0x68, bad id 0xffffffff Read config 32 bus 2,devfn 0x70,reg 0x0,val 0xffffffff PCI: devfn 0x70, bad id 0xffffffff Read config 32 bus 2,devfn 0x78,reg 0x0,val 0xffffffff PCI: devfn 0x78, bad id 0xffffffff Read config 32 bus 2,devfn 0x80,reg 0x0,val 0xffffffff PCI: devfn 0x80, bad id 0xffffffff Read config 32 bus 2,devfn 0x88,reg 0x0,val 0xffffffff PCI: devfn 0x88, bad id 0xffffffff Read config 32 bus 2,devfn 0x90,reg 0x0,val 0xffffffff PCI: devfn 0x90, bad id 0xffffffff Read config 32 bus 2,devfn 0x98,reg 0x0,val 0xffffffff PCI: devfn 0x98, bad id 0xffffffff Read config 32 bus 2,devfn 0xa0,reg 0x0,val 0xffffffff PCI: devfn 0xa0, bad id 0xffffffff Read config 32 bus 2,devfn 0xa8,reg 0x0,val 0xffffffff PCI: devfn 0xa8, bad id 0xffffffff Read config 32 bus 2,devfn 0xb0,reg 0x0,val 0xffffffff PCI: devfn 0xb0, bad id 0xffffffff Read config 32 bus 2,devfn 0xb8,reg 0x0,val 0xffffffff PCI: devfn 0xb8, bad id 0xffffffff Read config 32 bus 2,devfn 0xc0,reg 0x0,val 0xffffffff PCI: devfn 0xc0, bad id 0xffffffff Read config 32 bus 2,devfn 0xc8,reg 0x0,val 0xffffffff PCI: devfn 0xc8, bad id 0xffffffff Read config 32 bus 2,devfn 0xd0,reg 0x0,val 0xffffffff PCI: devfn 0xd0, bad id 0xffffffff Read config 32 bus 2,devfn 0xd8,reg 0x0,val 0xffffffff PCI: devfn 0xd8, bad id 0xffffffff Read config 32 bus 2,devfn 0xe0,reg 0x0,val 0xffffffff PCI: devfn 0xe0, bad id 0xffffffff Read config 32 bus 2,devfn 0xe8,reg 0x0,val 0xffffffff PCI: devfn 0xe8, bad id 0xffffffff Read config 32 bus 2,devfn 0xf0,reg 0x0,val 0xffffffff PCI: devfn 0xf0, bad id 0xffffffff Read config 32 bus 2,devfn 0xf8,reg 0x0,val 0xffffffff PCI: devfn 0xf8, bad id 0xffffffff PCI: pci_scan_bus returning with max=02 Write config 32 bus 1, devfn 0x10, reg 0x18, val 0x20201 Write config 16 bus 1, devfn 0x10, reg 0x4, val 0x0 pci_scan_bridge returns max 2 Read config 16 bus 1,devfn 0x20,reg 0x4,val 0x0 Write config 16 bus 1, devfn 0x20, reg 0x4, val 0x0 Write config 16 bus 1, devfn 0x20, reg 0x6, val 0xffff Read config 32 bus 1,devfn 0x20,reg 0x18,val 0x0 Write config 32 bus 1, devfn 0x20, reg 0x18, val 0xff0301 PCI: pci_scan_bus for bus 3 Read config 16 bus 1,devfn 0x28,reg 0x48,val 0xffff Read config 32 bus 3,devfn 0x0,reg 0x0,val 0x74641022 Read config 8 bus 3,devfn 0x0,reg 0xe,val 0x80 Read config 32 bus 3,devfn 0x0,reg 0x8,val 0xc03100b PCI: 03:00.0 [1022/7464] ops Read config 16 bus 1,devfn 0x28,reg 0x48,val 0xffff PCI: 03:00.0 [1022/7464] enabled Read config 16 bus 1,devfn 0x28,reg 0x48,val 0xffff Read config 32 bus 3,devfn 0x1,reg 0x0,val 0x74641022 Read config 8 bus 3,devfn 0x1,reg 0xe,val 0x0 Read config 32 bus 3,devfn 0x1,reg 0x8,val 0xc03100b PCI: 03:00.1 [1022/7464] ops Read config 16 bus 1,devfn 0x28,reg 0x48,val 0xffff PCI: 03:00.1 [1022/7464] enabled Read config 16 bus 1,devfn 0x28,reg 0x48,val 0xffff Read config 32 bus 3,devfn 0x2,reg 0x0,val 0x74631022 Read config 8 bus 3,devfn 0x2,reg 0xe,val 0x0 Read config 32 bus 3,devfn 0x2,reg 0x8,val 0xc032002 PCI: 03:00.2 [1022/7463] ops Read config 16 bus 1,devfn 0x28,reg 0x48,val 0xffff PCI: 03:00.2 [1022/7463] enabled Read config 32 bus 3,devfn 0x3,reg 0x0,val 0xffffffff PCI: devfn 0x3, bad id 0xffffffff Read config 32 bus 3,devfn 0x4,reg 0x0,val 0xffffffff PCI: devfn 0x4, bad id 0xffffffff Read config 32 bus 3,devfn 0x5,reg 0x0,val 0xffffffff PCI: devfn 0x5, bad id 0xffffffff Read config 32 bus 3,devfn 0x6,reg 0x0,val 0xffffffff PCI: devfn 0x6, bad id 0xffffffff Read config 32 bus 3,devfn 0x7,reg 0x0,val 0xffffffff PCI: devfn 0x7, bad id 0xffffffff Read config 16 bus 1,devfn 0x28,reg 0x48,val 0xffff Read config 32 bus 3,devfn 0x8,reg 0x0,val 0x74621022 Read config 8 bus 3,devfn 0x8,reg 0xe,val 0x0 Read config 32 bus 3,devfn 0x8,reg 0x8,val 0x2000003 PCI: 03:01.0 [1022/7462] enabled Read config 32 bus 3,devfn 0x10,reg 0x0,val 0xffffffff PCI: devfn 0x10, bad id 0xffffffff Read config 32 bus 3,devfn 0x18,reg 0x0,val 0xffffffff PCI: devfn 0x18, bad id 0xffffffff Read config 32 bus 3,devfn 0x20,reg 0x0,val 0xffffffff PCI: devfn 0x20, bad id 0xffffffff Read config 32 bus 3,devfn 0x28,reg 0x0,val 0x164514e4 malloc Enter, size 256, free_mem_ptr 00016c44 malloc 0x00016c44 Read config 8 bus 3,devfn 0x28,reg 0xe,val 0x0 Read config 32 bus 3,devfn 0x28,reg 0x8,val 0x2000015 PCI: 03:05.0 [14e4/1645] enabled Read config 32 bus 3,devfn 0x30,reg 0x0,val 0xffffffff PCI: devfn 0x30, bad id 0xffffffff Read config 32 bus 3,devfn 0x38,reg 0x0,val 0xffffffff PCI: devfn 0x38, bad id 0xffffffff Read config 32 bus 3,devfn 0x40,reg 0x0,val 0xffffffff PCI: devfn 0x40, bad id 0xffffffff Read config 32 bus 3,devfn 0x48,reg 0x0,val 0xffffffff PCI: devfn 0x48, bad id 0xffffffff Read config 32 bus 3,devfn 0x50,reg 0x0,val 0xffffffff PCI: devfn 0x50, bad id 0xffffffff Read config 32 bus 3,devfn 0x58,reg 0x0,val 0xffffffff PCI: devfn 0x58, bad id 0xffffffff Read config 32 bus 3,devfn 0x60,reg 0x0,val 0xffffffff PCI: devfn 0x60, bad id 0xffffffff Read config 32 bus 3,devfn 0x68,reg 0x0,val 0xffffffff PCI: devfn 0x68, bad id 0xffffffff Read config 32 bus 3,devfn 0x70,reg 0x0,val 0xffffffff PCI: devfn 0x70, bad id 0xffffffff Read config 32 bus 3,devfn 0x78,reg 0x0,val 0xffffffff PCI: devfn 0x78, bad id 0xffffffff Read config 32 bus 3,devfn 0x80,reg 0x0,val 0xffffffff PCI: devfn 0x80, bad id 0xffffffff Read config 32 bus 3,devfn 0x88,reg 0x0,val 0xffffffff PCI: devfn 0x88, bad id 0xffffffff Read config 32 bus 3,devfn 0x90,reg 0x0,val 0xffffffff PCI: devfn 0x90, bad id 0xffffffff Read config 32 bus 3,devfn 0x98,reg 0x0,val 0xffffffff PCI: devfn 0x98, bad id 0xffffffff Read config 32 bus 3,devfn 0xa0,reg 0x0,val 0xffffffff PCI: devfn 0xa0, bad id 0xffffffff Read config 32 bus 3,devfn 0xa8,reg 0x0,val 0xffffffff PCI: devfn 0xa8, bad id 0xffffffff Read config 32 bus 3,devfn 0xb0,reg 0x0,val 0xffffffff PCI: devfn 0xb0, bad id 0xffffffff Read config 32 bus 3,devfn 0xb8,reg 0x0,val 0xffffffff PCI: devfn 0xb8, bad id 0xffffffff Read config 32 bus 3,devfn 0xc0,reg 0x0,val 0xffffffff PCI: devfn 0xc0, bad id 0xffffffff Read config 32 bus 3,devfn 0xc8,reg 0x0,val 0xffffffff PCI: devfn 0xc8, bad id 0xffffffff Read config 32 bus 3,devfn 0xd0,reg 0x0,val 0xffffffff PCI: devfn 0xd0, bad id 0xffffffff Read config 32 bus 3,devfn 0xd8,reg 0x0,val 0xffffffff PCI: devfn 0xd8, bad id 0xffffffff Read config 32 bus 3,devfn 0xe0,reg 0x0,val 0xffffffff PCI: devfn 0xe0, bad id 0xffffffff Read config 32 bus 3,devfn 0xe8,reg 0x0,val 0xffffffff PCI: devfn 0xe8, bad id 0xffffffff Read config 32 bus 3,devfn 0xf0,reg 0x0,val 0xffffffff PCI: devfn 0xf0, bad id 0xffffffff Read config 32 bus 3,devfn 0xf8,reg 0x0,val 0xffffffff PCI: devfn 0xf8, bad id 0xffffffff PCI: pci_scan_bus returning with max=03 Write config 32 bus 1, devfn 0x20, reg 0x18, val 0x30301 Write config 16 bus 1, devfn 0x20, reg 0x4, val 0x0 pci_scan_bridge returns max 3 PCI: pci_scan_bus returning with max=03 Hyper transport scan link: 0 new max: 3 Write config 32 bus 0, devfn 0xc0, reg 0x94, val 0x30100 Write config 32 bus 0, devfn 0xc1, reg 0xe0, val 0x3010003 Hypertransport scan link done Read config 32 bus 0,devfn 0xc0,reg 0xb8,val 0x0 Read config 32 bus 0,devfn 0xc0,reg 0xd8,val 0x0 amdk8_scan_chains max: 3 done PCI: pci_scan_bus returning with max=03 Write config 32 bus 0, devfn 0xc1, reg 0xe0, val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0xe4, val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0xe8, val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0xec, val 0x0 done Allocating resources... root_dev_read_resources . Root is 0000ea20 root_dev_read_resources . link 0000eae0, resource 0000ea4c Root Device compute_allocate_io: base: 00000400 size: 00000000 align: 0 gran: 0 Read config 32 bus 0,devfn 0xc1,reg 0xc0,val 0x3 Read config 32 bus 0,devfn 0xc1,reg 0xc4,val 0x1fff000 PCI: 00:18.0 compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12 Read config 32 bus 1,devfn 0x8,reg 0x10,val 0x8 Write config 32 bus 1, devfn 0x8, reg 0x10, val 0xffffffff Read config 32 bus 1,devfn 0x8,reg 0x10,val 0xf000000c Write config 32 bus 1, devfn 0x8, reg 0x10, val 0x0 Read config 32 bus 1,devfn 0x8,reg 0x10,val 0xc Write config 32 bus 1, devfn 0x8, reg 0x10, val 0x8 Read config 32 bus 1,devfn 0x8,reg 0x14,val 0x0 Write config 32 bus 1, devfn 0x8, reg 0x14, val 0xffffffff Read config 32 bus 1,devfn 0x8,reg 0x14,val 0xffffffff Write config 32 bus 1, devfn 0x8, reg 0x14, val 0x0 Read config 32 bus 1,devfn 0x8,reg 0x14,val 0x0 Write config 32 bus 1, devfn 0x8, reg 0x14, val 0x0 Write config 32 bus 1, devfn 0x8, reg 0x14, val 0x0 Read config 32 bus 1,devfn 0x8,reg 0x18,val 0x0 Write config 32 bus 1, devfn 0x8, reg 0x18, val 0xffffffff Read config 32 bus 1,devfn 0x8,reg 0x18,val 0x0 Write config 32 bus 1, devfn 0x8, reg 0x18, val 0x0 Read config 32 bus 1,devfn 0x8,reg 0x18,val 0x0 Write config 32 bus 1, devfn 0x8, reg 0x18, val 0x0 Read config 32 bus 1,devfn 0x8,reg 0x1c,val 0x0 Write config 32 bus 1, devfn 0x8, reg 0x1c, val 0xffffffff Read config 32 bus 1,devfn 0x8,reg 0x1c,val 0x0 Write config 32 bus 1, devfn 0x8, reg 0x1c, val 0x0 Read config 32 bus 1,devfn 0x8,reg 0x1c,val 0x0 Write config 32 bus 1, devfn 0x8, reg 0x1c, val 0x0 Read config 32 bus 1,devfn 0x8,reg 0x20,val 0x0 Write config 32 bus 1, devfn 0x8, reg 0x20, val 0xffffffff Read config 32 bus 1,devfn 0x8,reg 0x20,val 0x0 Write config 32 bus 1, devfn 0x8, reg 0x20, val 0x0 Read config 32 bus 1,devfn 0x8,reg 0x20,val 0x0 Write config 32 bus 1, devfn 0x8, reg 0x20, val 0x0 Read config 32 bus 1,devfn 0x8,reg 0x24,val 0x0 Write config 32 bus 1, devfn 0x8, reg 0x24, val 0xffffffff Read config 32 bus 1,devfn 0x8,reg 0x24,val 0x0 Write config 32 bus 1, devfn 0x8, reg 0x24, val 0x0 Read config 32 bus 1,devfn 0x8,reg 0x24,val 0x0 Write config 32 bus 1, devfn 0x8, reg 0x24, val 0x0 Read config 32 bus 1,devfn 0x8,reg 0x30,val 0x0 PCI: 01:02.0 compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12 Read config 32 bus 2,devfn 0x0,reg 0x10,val 0x8 Write config 32 bus 2, devfn 0x0, reg 0x10, val 0xffffffff Read config 32 bus 2,devfn 0x0,reg 0x10,val 0xf8000008 Write config 32 bus 2, devfn 0x0, reg 0x10, val 0x0 Read config 32 bus 2,devfn 0x0,reg 0x10,val 0x8 Write config 32 bus 2, devfn 0x0, reg 0x10, val 0x8 Read config 32 bus 2,devfn 0x0,reg 0x14,val 0x1 Write config 32 bus 2, devfn 0x0, reg 0x14, val 0xffffffff Read config 32 bus 2,devfn 0x0,reg 0x14,val 0xffffff01 Write config 32 bus 2, devfn 0x0, reg 0x14, val 0x0 Read config 32 bus 2,devfn 0x0,reg 0x14,val 0x1 Write config 32 bus 2, devfn 0x0, reg 0x14, val 0x1 Read config 32 bus 2,devfn 0x0,reg 0x18,val 0x0 Write config 32 bus 2, devfn 0x0, reg 0x18, val 0xffffffff Read config 32 bus 2,devfn 0x0,reg 0x18,val 0xffff0000 Write config 32 bus 2, devfn 0x0, reg 0x18, val 0x0 Read config 32 bus 2,devfn 0x0,reg 0x18,val 0x0 Write config 32 bus 2, devfn 0x0, reg 0x18, val 0x0 Read config 32 bus 2,devfn 0x0,reg 0x1c,val 0x0 Write config 32 bus 2, devfn 0x0, reg 0x1c, val 0xffffffff Read config 32 bus 2,devfn 0x0,reg 0x1c,val 0x0 Write config 32 bus 2, devfn 0x0, reg 0x1c, val 0x0 Read config 32 bus 2,devfn 0x0,reg 0x1c,val 0x0 Write config 32 bus 2, devfn 0x0, reg 0x1c, val 0x0 Read config 32 bus 2,devfn 0x0,reg 0x20,val 0x0 Write config 32 bus 2, devfn 0x0, reg 0x20, val 0xffffffff Read config 32 bus 2,devfn 0x0,reg 0x20,val 0x0 Write config 32 bus 2, devfn 0x0, reg 0x20, val 0x0 Read config 32 bus 2,devfn 0x0,reg 0x20,val 0x0 Write config 32 bus 2, devfn 0x0, reg 0x20, val 0x0 Read config 32 bus 2,devfn 0x0,reg 0x24,val 0x0 Write config 32 bus 2, devfn 0x0, reg 0x24, val 0xffffffff Read config 32 bus 2,devfn 0x0,reg 0x24,val 0x0 Write config 32 bus 2, devfn 0x0, reg 0x24, val 0x0 Read config 32 bus 2,devfn 0x0,reg 0x24,val 0x0 Write config 32 bus 2, devfn 0x0, reg 0x24, val 0x0 Read config 32 bus 2,devfn 0x0,reg 0x30,val 0x0 PCI: 02:00.0 14 * [0x00000000 - 0x000000ff] io compute_allocate_io: base: 00000100 size: 00001000 align: 12 gran: 12 done PCI: 01:02.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 02:00.0 10 * [0x00000000 - 0x07ffffff] prefmem compute_allocate_prefmem: base: 08000000 size: 08000000 align: 27 gran: 20 done PCI: 01:02.0 compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 02:00.0 18 * [0x00000000 - 0x0000ffff] mem compute_allocate_mem: base: 00010000 size: 00100000 align: 20 gran: 20 done Read config 32 bus 1,devfn 0x10,reg 0x10,val 0x0 Write config 32 bus 1, devfn 0x10, reg 0x10, val 0xffffffff Read config 32 bus 1,devfn 0x10,reg 0x10,val 0x0 Write config 32 bus 1, devfn 0x10, reg 0x10, val 0x0 Read config 32 bus 1,devfn 0x10,reg 0x10,val 0x0 Write config 32 bus 1, devfn 0x10, reg 0x10, val 0x0 Read config 32 bus 1,devfn 0x10,reg 0x14,val 0x0 Write config 32 bus 1, devfn 0x10, reg 0x14, val 0xffffffff Read config 32 bus 1,devfn 0x10,reg 0x14,val 0x0 Write config 32 bus 1, devfn 0x10, reg 0x14, val 0x0 Read config 32 bus 1,devfn 0x10,reg 0x14,val 0x0 Write config 32 bus 1, devfn 0x10, reg 0x14, val 0x0 Read config 32 bus 1,devfn 0x10,reg 0x38,val 0x0 PCI: 01:04.0 compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12 Read config 32 bus 3,devfn 0x0,reg 0x10,val 0x0 Write config 32 bus 3, devfn 0x0, reg 0x10, val 0xffffffff Read config 32 bus 3,devfn 0x0,reg 0x10,val 0xfffff000 Write config 32 bus 3, devfn 0x0, reg 0x10, val 0x0 Read config 32 bus 3,devfn 0x0,reg 0x10,val 0x0 Write config 32 bus 3, devfn 0x0, reg 0x10, val 0x0 Read config 32 bus 3,devfn 0x0,reg 0x14,val 0x0 Write config 32 bus 3, devfn 0x0, reg 0x14, val 0xffffffff Read config 32 bus 3,devfn 0x0,reg 0x14,val 0x0 Write config 32 bus 3, devfn 0x0, reg 0x14, val 0x0 Read config 32 bus 3,devfn 0x0,reg 0x14,val 0x0 Write config 32 bus 3, devfn 0x0, reg 0x14, val 0x0 Read config 32 bus 3,devfn 0x0,reg 0x18,val 0x0 Write config 32 bus 3, devfn 0x0, reg 0x18, val 0xffffffff Read config 32 bus 3,devfn 0x0,reg 0x18,val 0x0 Write config 32 bus 3, devfn 0x0, reg 0x18, val 0x0 Read config 32 bus 3,devfn 0x0,reg 0x18,val 0x0 Write config 32 bus 3, devfn 0x0, reg 0x18, val 0x0 Read config 32 bus 3,devfn 0x0,reg 0x1c,val 0x0 Write config 32 bus 3, devfn 0x0, reg 0x1c, val 0xffffffff Read config 32 bus 3,devfn 0x0,reg 0x1c,val 0x0 Write config 32 bus 3, devfn 0x0, reg 0x1c, val 0x0 Read config 32 bus 3,devfn 0x0,reg 0x1c,val 0x0 Write config 32 bus 3, devfn 0x0, reg 0x1c, val 0x0 Read config 32 bus 3,devfn 0x0,reg 0x20,val 0x0 Write config 32 bus 3, devfn 0x0, reg 0x20, val 0xffffffff Read config 32 bus 3,devfn 0x0,reg 0x20,val 0x0 Write config 32 bus 3, devfn 0x0, reg 0x20, val 0x0 Read config 32 bus 3,devfn 0x0,reg 0x20,val 0x0 Write config 32 bus 3, devfn 0x0, reg 0x20, val 0x0 Read config 32 bus 3,devfn 0x0,reg 0x24,val 0x0 Write config 32 bus 3, devfn 0x0, reg 0x24, val 0xffffffff Read config 32 bus 3,devfn 0x0,reg 0x24,val 0x0 Write config 32 bus 3, devfn 0x0, reg 0x24, val 0x0 Read config 32 bus 3,devfn 0x0,reg 0x24,val 0x0 Write config 32 bus 3, devfn 0x0, reg 0x24, val 0x0 Read config 32 bus 3,devfn 0x0,reg 0x30,val 0x0 Read config 32 bus 3,devfn 0x1,reg 0x10,val 0x0 Write config 32 bus 3, devfn 0x1, reg 0x10, val 0xffffffff Read config 32 bus 3,devfn 0x1,reg 0x10,val 0xfffff000 Write config 32 bus 3, devfn 0x1, reg 0x10, val 0x0 Read config 32 bus 3,devfn 0x1,reg 0x10,val 0x0 Write config 32 bus 3, devfn 0x1, reg 0x10, val 0x0 Read config 32 bus 3,devfn 0x1,reg 0x14,val 0x0 Write config 32 bus 3, devfn 0x1, reg 0x14, val 0xffffffff Read config 32 bus 3,devfn 0x1,reg 0x14,val 0x0 Write config 32 bus 3, devfn 0x1, reg 0x14, val 0x0 Read config 32 bus 3,devfn 0x1,reg 0x14,val 0x0 Write config 32 bus 3, devfn 0x1, reg 0x14, val 0x0 Read config 32 bus 3,devfn 0x1,reg 0x18,val 0x0 Write config 32 bus 3, devfn 0x1, reg 0x18, val 0xffffffff Read config 32 bus 3,devfn 0x1,reg 0x18,val 0x0 Write config 32 bus 3, devfn 0x1, reg 0x18, val 0x0 Read config 32 bus 3,devfn 0x1,reg 0x18,val 0x0 Write config 32 bus 3, devfn 0x1, reg 0x18, val 0x0 Read config 32 bus 3,devfn 0x1,reg 0x1c,val 0x0 Write config 32 bus 3, devfn 0x1, reg 0x1c, val 0xffffffff Read config 32 bus 3,devfn 0x1,reg 0x1c,val 0x0 Write config 32 bus 3, devfn 0x1, reg 0x1c, val 0x0 Read config 32 bus 3,devfn 0x1,reg 0x1c,val 0x0 Write config 32 bus 3, devfn 0x1, reg 0x1c, val 0x0 Read config 32 bus 3,devfn 0x1,reg 0x20,val 0x0 Write config 32 bus 3, devfn 0x1, reg 0x20, val 0xffffffff Read config 32 bus 3,devfn 0x1,reg 0x20,val 0x0 Write config 32 bus 3, devfn 0x1, reg 0x20, val 0x0 Read config 32 bus 3,devfn 0x1,reg 0x20,val 0x0 Write config 32 bus 3, devfn 0x1, reg 0x20, val 0x0 Read config 32 bus 3,devfn 0x1,reg 0x24,val 0x0 Write config 32 bus 3, devfn 0x1, reg 0x24, val 0xffffffff Read config 32 bus 3,devfn 0x1,reg 0x24,val 0x0 Write config 32 bus 3, devfn 0x1, reg 0x24, val 0x0 Read config 32 bus 3,devfn 0x1,reg 0x24,val 0x0 Write config 32 bus 3, devfn 0x1, reg 0x24, val 0x0 Read config 32 bus 3,devfn 0x1,reg 0x30,val 0x0 Read config 32 bus 3,devfn 0x2,reg 0x10,val 0x0 Write config 32 bus 3, devfn 0x2, reg 0x10, val 0xffffffff Read config 32 bus 3,devfn 0x2,reg 0x10,val 0xffffff00 Write config 32 bus 3, devfn 0x2, reg 0x10, val 0x0 Read config 32 bus 3,devfn 0x2,reg 0x10,val 0x0 Write config 32 bus 3, devfn 0x2, reg 0x10, val 0x0 Read config 32 bus 3,devfn 0x2,reg 0x14,val 0x0 Write config 32 bus 3, devfn 0x2, reg 0x14, val 0xffffffff Read config 32 bus 3,devfn 0x2,reg 0x14,val 0xffffffe0 Write config 32 bus 3, devfn 0x2, reg 0x14, val 0x0 Read config 32 bus 3,devfn 0x2,reg 0x14,val 0x0 Write config 32 bus 3, devfn 0x2, reg 0x14, val 0x0 Read config 32 bus 3,devfn 0x2,reg 0x18,val 0x0 Write config 32 bus 3, devfn 0x2, reg 0x18, val 0xffffffff Read config 32 bus 3,devfn 0x2,reg 0x18,val 0x0 Write config 32 bus 3, devfn 0x2, reg 0x18, val 0x0 Read config 32 bus 3,devfn 0x2,reg 0x18,val 0x0 Write config 32 bus 3, devfn 0x2, reg 0x18, val 0x0 Read config 32 bus 3,devfn 0x2,reg 0x1c,val 0x0 Write config 32 bus 3, devfn 0x2, reg 0x1c, val 0xffffffff Read config 32 bus 3,devfn 0x2,reg 0x1c,val 0x0 Write config 32 bus 3, devfn 0x2, reg 0x1c, val 0x0 Read config 32 bus 3,devfn 0x2,reg 0x1c,val 0x0 Write config 32 bus 3, devfn 0x2, reg 0x1c, val 0x0 Read config 32 bus 3,devfn 0x2,reg 0x20,val 0x0 Write config 32 bus 3, devfn 0x2, reg 0x20, val 0xffffffff Read config 32 bus 3,devfn 0x2,reg 0x20,val 0x0 Write config 32 bus 3, devfn 0x2, reg 0x20, val 0x0 Read config 32 bus 3,devfn 0x2,reg 0x20,val 0x0 Write config 32 bus 3, devfn 0x2, reg 0x20, val 0x0 Read config 32 bus 3,devfn 0x2,reg 0x24,val 0x0 Write config 32 bus 3, devfn 0x2, reg 0x24, val 0xffffffff Read config 32 bus 3,devfn 0x2,reg 0x24,val 0x0 Write config 32 bus 3, devfn 0x2, reg 0x24, val 0x0 Read config 32 bus 3,devfn 0x2,reg 0x24,val 0x0 Write config 32 bus 3, devfn 0x2, reg 0x24, val 0x0 Read config 32 bus 3,devfn 0x2,reg 0x30,val 0x0 Read config 32 bus 3,devfn 0x8,reg 0x10,val 0x0 Write config 32 bus 3, devfn 0x8, reg 0x10, val 0xffffffff Read config 32 bus 3,devfn 0x8,reg 0x10,val 0xfffff000 Write config 32 bus 3, devfn 0x8, reg 0x10, val 0x0 Read config 32 bus 3,devfn 0x8,reg 0x10,val 0x0 Write config 32 bus 3, devfn 0x8, reg 0x10, val 0x0 Read config 32 bus 3,devfn 0x8,reg 0x14,val 0x0 Write config 32 bus 3, devfn 0x8, reg 0x14, val 0xffffffff Read config 32 bus 3,devfn 0x8,reg 0x14,val 0x0 Write config 32 bus 3, devfn 0x8, reg 0x14, val 0x0 Read config 32 bus 3,devfn 0x8,reg 0x14,val 0x0 Write config 32 bus 3, devfn 0x8, reg 0x14, val 0x0 Read config 32 bus 3,devfn 0x8,reg 0x18,val 0x0 Write config 32 bus 3, devfn 0x8, reg 0x18, val 0xffffffff Read config 32 bus 3,devfn 0x8,reg 0x18,val 0x0 Write config 32 bus 3, devfn 0x8, reg 0x18, val 0x0 Read config 32 bus 3,devfn 0x8,reg 0x18,val 0x0 Write config 32 bus 3, devfn 0x8, reg 0x18, val 0x0 Read config 32 bus 3,devfn 0x8,reg 0x1c,val 0x0 Write config 32 bus 3, devfn 0x8, reg 0x1c, val 0xffffffff Read config 32 bus 3,devfn 0x8,reg 0x1c,val 0x0 Write config 32 bus 3, devfn 0x8, reg 0x1c, val 0x0 Read config 32 bus 3,devfn 0x8,reg 0x1c,val 0x0 Write config 32 bus 3, devfn 0x8, reg 0x1c, val 0x0 Read config 32 bus 3,devfn 0x8,reg 0x20,val 0x0 Write config 32 bus 3, devfn 0x8, reg 0x20, val 0xffffffff Read config 32 bus 3,devfn 0x8,reg 0x20,val 0x0 Write config 32 bus 3, devfn 0x8, reg 0x20, val 0x0 Read config 32 bus 3,devfn 0x8,reg 0x20,val 0x0 Write config 32 bus 3, devfn 0x8, reg 0x20, val 0x0 Read config 32 bus 3,devfn 0x8,reg 0x24,val 0x0 Write config 32 bus 3, devfn 0x8, reg 0x24, val 0xffffffff Read config 32 bus 3,devfn 0x8,reg 0x24,val 0x0 Write config 32 bus 3, devfn 0x8, reg 0x24, val 0x0 Read config 32 bus 3,devfn 0x8,reg 0x24,val 0x0 Write config 32 bus 3, devfn 0x8, reg 0x24, val 0x0 Read config 32 bus 3,devfn 0x8,reg 0x30,val 0x0 Read config 32 bus 3,devfn 0x28,reg 0x10,val 0xe7bf0004 Write config 32 bus 3, devfn 0x28, reg 0x10, val 0xffffffff Read config 32 bus 3,devfn 0x28,reg 0x10,val 0xffff0004 Write config 32 bus 3, devfn 0x28, reg 0x10, val 0x0 Read config 32 bus 3,devfn 0x28,reg 0x10,val 0x4 Write config 32 bus 3, devfn 0x28, reg 0x10, val 0xe7bf0004 Read config 32 bus 3,devfn 0x28,reg 0x14,val 0xdfedffbf Write config 32 bus 3, devfn 0x28, reg 0x14, val 0xffffffff Read config 32 bus 3,devfn 0x28,reg 0x14,val 0xffffffff Write config 32 bus 3, devfn 0x28, reg 0x14, val 0x0 Read config 32 bus 3,devfn 0x28,reg 0x14,val 0x0 Write config 32 bus 3, devfn 0x28, reg 0x14, val 0xdfedffbf Write config 32 bus 3, devfn 0x28, reg 0x14, val 0x0 Read config 32 bus 3,devfn 0x28,reg 0x18,val 0x0 Write config 32 bus 3, devfn 0x28, reg 0x18, val 0xffffffff Read config 32 bus 3,devfn 0x28,reg 0x18,val 0x0 Write config 32 bus 3, devfn 0x28, reg 0x18, val 0x0 Read config 32 bus 3,devfn 0x28,reg 0x18,val 0x0 Write config 32 bus 3, devfn 0x28, reg 0x18, val 0x0 Read config 32 bus 3,devfn 0x28,reg 0x1c,val 0x0 Write config 32 bus 3, devfn 0x28, reg 0x1c, val 0xffffffff Read config 32 bus 3,devfn 0x28,reg 0x1c,val 0x0 Write config 32 bus 3, devfn 0x28, reg 0x1c, val 0x0 Read config 32 bus 3,devfn 0x28,reg 0x1c,val 0x0 Write config 32 bus 3, devfn 0x28, reg 0x1c, val 0x0 Read config 32 bus 3,devfn 0x28,reg 0x20,val 0x0 Write config 32 bus 3, devfn 0x28, reg 0x20, val 0xffffffff Read config 32 bus 3,devfn 0x28,reg 0x20,val 0x0 Write config 32 bus 3, devfn 0x28, reg 0x20, val 0x0 Read config 32 bus 3,devfn 0x28,reg 0x20,val 0x0 Write config 32 bus 3, devfn 0x28, reg 0x20, val 0x0 Read config 32 bus 3,devfn 0x28,reg 0x24,val 0x0 Write config 32 bus 3, devfn 0x28, reg 0x24, val 0xffffffff Read config 32 bus 3,devfn 0x28,reg 0x24,val 0x0 Write config 32 bus 3, devfn 0x28, reg 0x24, val 0x0 Read config 32 bus 3,devfn 0x28,reg 0x24,val 0x0 Write config 32 bus 3, devfn 0x28, reg 0x24, val 0x0 Read config 32 bus 3,devfn 0x28,reg 0x30,val 0x0 compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12 done PCI: 01:04.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 done PCI: 01:04.0 compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 03:05.0 10 * [0x00000000 - 0x0000ffff] mem PCI: 03:00.0 10 * [0x00010000 - 0x00010fff] mem PCI: 03:00.1 10 * [0x00011000 - 0x00011fff] mem PCI: 03:01.0 10 * [0x00012000 - 0x00012fff] mem PCI: 03:00.2 10 * [0x00013000 - 0x000130ff] mem PCI: 03:00.2 14 * [0x00014000 - 0x0001401f] mem compute_allocate_mem: base: 00014020 size: 00100000 align: 20 gran: 20 done Read config 32 bus 1,devfn 0x20,reg 0x10,val 0x0 Write config 32 bus 1, devfn 0x20, reg 0x10, val 0xffffffff Read config 32 bus 1,devfn 0x20,reg 0x10,val 0x0 Write config 32 bus 1, devfn 0x20, reg 0x10, val 0x0 Read config 32 bus 1,devfn 0x20,reg 0x10,val 0x0 Write config 32 bus 1, devfn 0x20, reg 0x10, val 0x0 Read config 32 bus 1,devfn 0x20,reg 0x14,val 0x0 Write config 32 bus 1, devfn 0x20, reg 0x14, val 0xffffffff Read config 32 bus 1,devfn 0x20,reg 0x14,val 0x0 Write config 32 bus 1, devfn 0x20, reg 0x14, val 0x0 Read config 32 bus 1,devfn 0x20,reg 0x14,val 0x0 Write config 32 bus 1, devfn 0x20, reg 0x14, val 0x0 Read config 32 bus 1,devfn 0x20,reg 0x38,val 0x0 Read config 32 bus 1,devfn 0x28,reg 0x10,val 0x0 Write config 32 bus 1, devfn 0x28, reg 0x10, val 0xffffffff Read config 32 bus 1,devfn 0x28,reg 0x10,val 0x0 Write config 32 bus 1, devfn 0x28, reg 0x10, val 0x0 Read config 32 bus 1,devfn 0x28,reg 0x10,val 0x0 Write config 32 bus 1, devfn 0x28, reg 0x10, val 0x0 Read config 32 bus 1,devfn 0x28,reg 0x14,val 0x0 Write config 32 bus 1, devfn 0x28, reg 0x14, val 0xffffffff Read config 32 bus 1,devfn 0x28,reg 0x14,val 0x0 Write config 32 bus 1, devfn 0x28, reg 0x14, val 0x0 Read config 32 bus 1,devfn 0x28,reg 0x14,val 0x0 Write config 32 bus 1, devfn 0x28, reg 0x14, val 0x0 Read config 32 bus 1,devfn 0x28,reg 0x18,val 0x0 Write config 32 bus 1, devfn 0x28, reg 0x18, val 0xffffffff Read config 32 bus 1,devfn 0x28,reg 0x18,val 0x0 Write config 32 bus 1, devfn 0x28, reg 0x18, val 0x0 Read config 32 bus 1,devfn 0x28,reg 0x18,val 0x0 Write config 32 bus 1, devfn 0x28, reg 0x18, val 0x0 Read config 32 bus 1,devfn 0x28,reg 0x1c,val 0x0 Write config 32 bus 1, devfn 0x28, reg 0x1c, val 0xffffffff Read config 32 bus 1,devfn 0x28,reg 0x1c,val 0x0 Write config 32 bus 1, devfn 0x28, reg 0x1c, val 0x0 Read config 32 bus 1,devfn 0x28,reg 0x1c,val 0x0 Write config 32 bus 1, devfn 0x28, reg 0x1c, val 0x0 Read config 32 bus 1,devfn 0x28,reg 0x20,val 0x0 Write config 32 bus 1, devfn 0x28, reg 0x20, val 0xffffffff Read config 32 bus 1,devfn 0x28,reg 0x20,val 0x0 Write config 32 bus 1, devfn 0x28, reg 0x20, val 0x0 Read config 32 bus 1,devfn 0x28,reg 0x20,val 0x0 Write config 32 bus 1, devfn 0x28, reg 0x20, val 0x0 Read config 32 bus 1,devfn 0x28,reg 0x24,val 0x0 Write config 32 bus 1, devfn 0x28, reg 0x24, val 0xffffffff Read config 32 bus 1,devfn 0x28,reg 0x24,val 0x0 Write config 32 bus 1, devfn 0x28, reg 0x24, val 0x0 Read config 32 bus 1,devfn 0x28,reg 0x24,val 0x0 Write config 32 bus 1, devfn 0x28, reg 0x24, val 0x0 Read config 32 bus 1,devfn 0x28,reg 0x30,val 0x0 Read config 32 bus 1,devfn 0x29,reg 0x10,val 0x0 Write config 32 bus 1, devfn 0x29, reg 0x10, val 0xffffffff Read config 32 bus 1,devfn 0x29,reg 0x10,val 0x0 Write config 32 bus 1, devfn 0x29, reg 0x10, val 0x0 Read config 32 bus 1,devfn 0x29,reg 0x10,val 0x0 Write config 32 bus 1, devfn 0x29, reg 0x10, val 0x0 Read config 32 bus 1,devfn 0x29,reg 0x14,val 0x0 Write config 32 bus 1, devfn 0x29, reg 0x14, val 0xffffffff Read config 32 bus 1,devfn 0x29,reg 0x14,val 0x0 Write config 32 bus 1, devfn 0x29, reg 0x14, val 0x0 Read config 32 bus 1,devfn 0x29,reg 0x14,val 0x0 Write config 32 bus 1, devfn 0x29, reg 0x14, val 0x0 Read config 32 bus 1,devfn 0x29,reg 0x18,val 0x0 Write config 32 bus 1, devfn 0x29, reg 0x18, val 0xffffffff Read config 32 bus 1,devfn 0x29,reg 0x18,val 0x0 Write config 32 bus 1, devfn 0x29, reg 0x18, val 0x0 Read config 32 bus 1,devfn 0x29,reg 0x18,val 0x0 Write config 32 bus 1, devfn 0x29, reg 0x18, val 0x0 Read config 32 bus 1,devfn 0x29,reg 0x1c,val 0x0 Write config 32 bus 1, devfn 0x29, reg 0x1c, val 0xffffffff Read config 32 bus 1,devfn 0x29,reg 0x1c,val 0x0 Write config 32 bus 1, devfn 0x29, reg 0x1c, val 0x0 Read config 32 bus 1,devfn 0x29,reg 0x1c,val 0x0 Write config 32 bus 1, devfn 0x29, reg 0x1c, val 0x0 Read config 32 bus 1,devfn 0x29,reg 0x20,val 0xcc01 Write config 32 bus 1, devfn 0x29, reg 0x20, val 0xffffffff Read config 32 bus 1,devfn 0x29,reg 0x20,val 0xfffffff1 Write config 32 bus 1, devfn 0x29, reg 0x20, val 0x0 Read config 32 bus 1,devfn 0x29,reg 0x20,val 0x1 Write config 32 bus 1, devfn 0x29, reg 0x20, val 0xcc01 Read config 32 bus 1,devfn 0x29,reg 0x24,val 0x0 Write config 32 bus 1, devfn 0x29, reg 0x24, val 0xffffffff Read config 32 bus 1,devfn 0x29,reg 0x24,val 0x0 Write config 32 bus 1, devfn 0x29, reg 0x24, val 0x0 Read config 32 bus 1,devfn 0x29,reg 0x24,val 0x0 Write config 32 bus 1, devfn 0x29, reg 0x24, val 0x0 Read config 32 bus 1,devfn 0x29,reg 0x30,val 0x0 Read config 32 bus 1,devfn 0x2a,reg 0x10,val 0x1 Write config 32 bus 1, devfn 0x2a, reg 0x10, val 0xffffffff Read config 32 bus 1,devfn 0x2a,reg 0x10,val 0xffffffe1 Write config 32 bus 1, devfn 0x2a, reg 0x10, val 0x0 Read config 32 bus 1,devfn 0x2a,reg 0x10,val 0x1 Write config 32 bus 1, devfn 0x2a, reg 0x10, val 0x1 Read config 32 bus 1,devfn 0x2a,reg 0x14,val 0x0 Write config 32 bus 1, devfn 0x2a, reg 0x14, val 0xffffffff Read config 32 bus 1,devfn 0x2a,reg 0x14,val 0x0 Write config 32 bus 1, devfn 0x2a, reg 0x14, val 0x0 Read config 32 bus 1,devfn 0x2a,reg 0x14,val 0x0 Write config 32 bus 1, devfn 0x2a, reg 0x14, val 0x0 Read config 32 bus 1,devfn 0x2a,reg 0x18,val 0x0 Write config 32 bus 1, devfn 0x2a, reg 0x18, val 0xffffffff Read config 32 bus 1,devfn 0x2a,reg 0x18,val 0x0 Write config 32 bus 1, devfn 0x2a, reg 0x18, val 0x0 Read config 32 bus 1,devfn 0x2a,reg 0x18,val 0x0 Write config 32 bus 1, devfn 0x2a, reg 0x18, val 0x0 Read config 32 bus 1,devfn 0x2a,reg 0x1c,val 0x0 Write config 32 bus 1, devfn 0x2a, reg 0x1c, val 0xffffffff Read config 32 bus 1,devfn 0x2a,reg 0x1c,val 0x0 Write config 32 bus 1, devfn 0x2a, reg 0x1c, val 0x0 Read config 32 bus 1,devfn 0x2a,reg 0x1c,val 0x0 Write config 32 bus 1, devfn 0x2a, reg 0x1c, val 0x0 Read config 32 bus 1,devfn 0x2a,reg 0x20,val 0x0 Write config 32 bus 1, devfn 0x2a, reg 0x20, val 0xffffffff Read config 32 bus 1,devfn 0x2a,reg 0x20,val 0x0 Write config 32 bus 1, devfn 0x2a, reg 0x20, val 0x0 Read config 32 bus 1,devfn 0x2a,reg 0x20,val 0x0 Write config 32 bus 1, devfn 0x2a, reg 0x20, val 0x0 Read config 32 bus 1,devfn 0x2a,reg 0x24,val 0x0 Write config 32 bus 1, devfn 0x2a, reg 0x24, val 0xffffffff Read config 32 bus 1,devfn 0x2a,reg 0x24,val 0x0 Write config 32 bus 1, devfn 0x2a, reg 0x24, val 0x0 Read config 32 bus 1,devfn 0x2a,reg 0x24,val 0x0 Write config 32 bus 1, devfn 0x2a, reg 0x24, val 0x0 Read config 32 bus 1,devfn 0x2a,reg 0x30,val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x10,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x10, val 0xffffffff Read config 32 bus 1,devfn 0x2b,reg 0x10,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x10, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x10,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x10, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x14,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x14, val 0xffffffff Read config 32 bus 1,devfn 0x2b,reg 0x14,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x14, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x14,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x14, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x18,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x18, val 0xffffffff Read config 32 bus 1,devfn 0x2b,reg 0x18,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x18, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x18,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x18, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x1c,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x1c, val 0xffffffff Read config 32 bus 1,devfn 0x2b,reg 0x1c,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x1c, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x1c,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x1c, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x20,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x20, val 0xffffffff Read config 32 bus 1,devfn 0x2b,reg 0x20,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x20, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x20,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x20, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x24,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x24, val 0xffffffff Read config 32 bus 1,devfn 0x2b,reg 0x24,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x24, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x24,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x24, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x30,val 0x0 Read config 32 bus 1,devfn 0x2d,reg 0x10,val 0x1 Write config 32 bus 1, devfn 0x2d, reg 0x10, val 0xffffffff Read config 32 bus 1,devfn 0x2d,reg 0x10,val 0xffffff01 Write config 32 bus 1, devfn 0x2d, reg 0x10, val 0x0 Read config 32 bus 1,devfn 0x2d,reg 0x10,val 0x1 Write config 32 bus 1, devfn 0x2d, reg 0x10, val 0x1 Read config 32 bus 1,devfn 0x2d,reg 0x14,val 0x1 Write config 32 bus 1, devfn 0x2d, reg 0x14, val 0xffffffff Read config 32 bus 1,devfn 0x2d,reg 0x14,val 0xffffffc1 Write config 32 bus 1, devfn 0x2d, reg 0x14, val 0x0 Read config 32 bus 1,devfn 0x2d,reg 0x14,val 0x1 Write config 32 bus 1, devfn 0x2d, reg 0x14, val 0x1 Read config 32 bus 1,devfn 0x2d,reg 0x18,val 0x0 Write config 32 bus 1, devfn 0x2d, reg 0x18, val 0xffffffff Read config 32 bus 1,devfn 0x2d,reg 0x18,val 0x0 Write config 32 bus 1, devfn 0x2d, reg 0x18, val 0x0 Read config 32 bus 1,devfn 0x2d,reg 0x18,val 0x0 Write config 32 bus 1, devfn 0x2d, reg 0x18, val 0x0 Read config 32 bus 1,devfn 0x2d,reg 0x1c,val 0x0 Write config 32 bus 1, devfn 0x2d, reg 0x1c, val 0xffffffff Read config 32 bus 1,devfn 0x2d,reg 0x1c,val 0x0 Write config 32 bus 1, devfn 0x2d, reg 0x1c, val 0x0 Read config 32 bus 1,devfn 0x2d,reg 0x1c,val 0x0 Write config 32 bus 1, devfn 0x2d, reg 0x1c, val 0x0 Read config 32 bus 1,devfn 0x2d,reg 0x20,val 0x0 Write config 32 bus 1, devfn 0x2d, reg 0x20, val 0xffffffff Read config 32 bus 1,devfn 0x2d,reg 0x20,val 0x0 Write config 32 bus 1, devfn 0x2d, reg 0x20, val 0x0 Read config 32 bus 1,devfn 0x2d,reg 0x20,val 0x0 Write config 32 bus 1, devfn 0x2d, reg 0x20, val 0x0 Read config 32 bus 1,devfn 0x2d,reg 0x24,val 0x0 Write config 32 bus 1, devfn 0x2d, reg 0x24, val 0xffffffff Read config 32 bus 1,devfn 0x2d,reg 0x24,val 0x0 Write config 32 bus 1, devfn 0x2d, reg 0x24, val 0x0 Read config 32 bus 1,devfn 0x2d,reg 0x24,val 0x0 Write config 32 bus 1, devfn 0x2d, reg 0x24, val 0x0 Read config 32 bus 1,devfn 0x2d,reg 0x30,val 0x0 Read config 32 bus 1,devfn 0x2e,reg 0x10,val 0x1 Write config 32 bus 1, devfn 0x2e, reg 0x10, val 0xffffffff Read config 32 bus 1,devfn 0x2e,reg 0x10,val 0xffffff01 Write config 32 bus 1, devfn 0x2e, reg 0x10, val 0x0 Read config 32 bus 1,devfn 0x2e,reg 0x10,val 0x1 Write config 32 bus 1, devfn 0x2e, reg 0x10, val 0x1 Read config 32 bus 1,devfn 0x2e,reg 0x14,val 0x1 Write config 32 bus 1, devfn 0x2e, reg 0x14, val 0xffffffff Read config 32 bus 1,devfn 0x2e,reg 0x14,val 0xffffff81 Write config 32 bus 1, devfn 0x2e, reg 0x14, val 0x0 Read config 32 bus 1,devfn 0x2e,reg 0x14,val 0x1 Write config 32 bus 1, devfn 0x2e, reg 0x14, val 0x1 Read config 32 bus 1,devfn 0x2e,reg 0x18,val 0x0 Write config 32 bus 1, devfn 0x2e, reg 0x18, val 0xffffffff Read config 32 bus 1,devfn 0x2e,reg 0x18,val 0x0 Write config 32 bus 1, devfn 0x2e, reg 0x18, val 0x0 Read config 32 bus 1,devfn 0x2e,reg 0x18,val 0x0 Write config 32 bus 1, devfn 0x2e, reg 0x18, val 0x0 Read config 32 bus 1,devfn 0x2e,reg 0x1c,val 0x0 Write config 32 bus 1, devfn 0x2e, reg 0x1c, val 0xffffffff Read config 32 bus 1,devfn 0x2e,reg 0x1c,val 0x0 Write config 32 bus 1, devfn 0x2e, reg 0x1c, val 0x0 Read config 32 bus 1,devfn 0x2e,reg 0x1c,val 0x0 Write config 32 bus 1, devfn 0x2e, reg 0x1c, val 0x0 Read config 32 bus 1,devfn 0x2e,reg 0x20,val 0x0 Write config 32 bus 1, devfn 0x2e, reg 0x20, val 0xffffffff Read config 32 bus 1,devfn 0x2e,reg 0x20,val 0x0 Write config 32 bus 1, devfn 0x2e, reg 0x20, val 0x0 Read config 32 bus 1,devfn 0x2e,reg 0x20,val 0x0 Write config 32 bus 1, devfn 0x2e, reg 0x20, val 0x0 Read config 32 bus 1,devfn 0x2e,reg 0x24,val 0x0 Write config 32 bus 1, devfn 0x2e, reg 0x24, val 0xffffffff Read config 32 bus 1,devfn 0x2e,reg 0x24,val 0x0 Write config 32 bus 1, devfn 0x2e, reg 0x24, val 0x0 Read config 32 bus 1,devfn 0x2e,reg 0x24,val 0x0 Write config 32 bus 1, devfn 0x2e, reg 0x24, val 0x0 Read config 32 bus 1,devfn 0x2e,reg 0x30,val 0x0 PCI: 01:02.0 1c * [0x00000000 - 0x00000fff] io PCI: 01:04.0 1c * [0x00001000 - 0x00000fff] io PCI: 01:05.5 10 * [0x00001000 - 0x000010ff] io PCI: 01:05.6 10 * [0x00001400 - 0x000014ff] io PCI: 01:05.6 14 * [0x00001800 - 0x0000187f] io PCI: 01:05.5 14 * [0x00001880 - 0x000018bf] io PCI: 01:05.2 10 * [0x000018c0 - 0x000018df] io PCI: 01:05.1 20 * [0x000018e0 - 0x000018ef] io compute_allocate_io: base: 000018f0 size: 00002000 align: 12 gran: 12 done Read config 32 bus 0,devfn 0xc1,reg 0x80,val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x84,val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x88,val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x8c,val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x90,val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x94,val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x98,val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x9c,val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0xa0,val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0xa4,val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0xa8,val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0xac,val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0xb0,val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0xb4,val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0xb8,val 0xfc0003 Read config 32 bus 0,devfn 0xc1,reg 0xbc,val 0xffff00 PCI: 00:18.0 compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20 Read config 32 bus 1,devfn 0x2b,reg 0x10,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x10, val 0xffffffff Read config 32 bus 1,devfn 0x2b,reg 0x10,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x10, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x10,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x10, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x14,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x14, val 0xffffffff Read config 32 bus 1,devfn 0x2b,reg 0x14,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x14, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x14,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x14, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x18,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x18, val 0xffffffff Read config 32 bus 1,devfn 0x2b,reg 0x18,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x18, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x18,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x18, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x1c,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x1c, val 0xffffffff Read config 32 bus 1,devfn 0x2b,reg 0x1c,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x1c, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x1c,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x1c, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x20,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x20, val 0xffffffff Read config 32 bus 1,devfn 0x2b,reg 0x20,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x20, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x20,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x20, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x24,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x24, val 0xffffffff Read config 32 bus 1,devfn 0x2b,reg 0x24,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x24, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x24,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x24, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x30,val 0x0 PCI: 01:01.0 10 * [0x00000000 - 0x0fffffff] prefmem PCI: 01:02.0 24 * [0x10000000 - 0x17ffffff] prefmem PCI: 01:02.0 20 * [0x18000000 - 0x180fffff] mem PCI: 01:04.0 20 * [0x18100000 - 0x181fffff] mem PCI: 01:04.0 24 * [0x18200000 - 0x181fffff] prefmem compute_allocate_mem: base: 18200000 size: 18200000 align: 28 gran: 20 done Read config 32 bus 0,devfn 0xc1,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0xc1,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0xc1,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0xc1,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0xc1,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0xc1,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0xc1,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x30,val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0xc2,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0xc2,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0xc2,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0xc2,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0xc2,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0xc2,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x30,val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0xc3,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0xc3,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0xc3,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0xc3,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0xc3,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0xc3,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x30,val 0x0 PCI: 00:18.0 c0 * [0x00001000 - 0x00002fff] io compute_allocate_io: base: 00003000 size: 00002c00 align: 12 gran: 0 done root_dev_read_resources . link 0000eae0, resource 0000ea64 Root Device compute_allocate_mem: base: 00000000 size: 00000000 align: 0 gran: 0 Read config 32 bus 0,devfn 0xc1,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0xc1,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0xc1,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0xc1,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0xc1,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0xc1,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0xc1,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x30,val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0xc2,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0xc2,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0xc2,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0xc2,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0xc2,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0xc2,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x30,val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0xc3,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0xc3,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0xc3,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0xc3,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0xc3,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0xc3,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x30,val 0x0 PCI: 00:18.0 b8 * [0x00000000 - 0x181fffff] mem compute_allocate_mem: base: 18200000 size: 18200000 align: 28 gran: 0 done root_dev_read_resources DONE Root Device compute_allocate_io: base: 00001000 size: 00002c00 align: 12 gran: 0 Read config 32 bus 0,devfn 0xc1,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0xc1,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0xc1,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0xc1,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0xc1,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0xc1,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0xc1,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x30,val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0xc2,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0xc2,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0xc2,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0xc2,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0xc2,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0xc2,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x30,val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0xc3,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0xc3,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0xc3,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0xc3,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0xc3,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0xc3,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x30,val 0x0 PCI: 00:18.0 c0 * [0x00001000 - 0x00002fff] io compute_allocate_io: base: 00003000 size: 00002000 align: 12 gran: 0 done Root Device compute_allocate_mem: base: e0000000 size: 18200000 align: 28 gran: 0 Read config 32 bus 0,devfn 0xc1,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0xc1,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0xc1,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0xc1,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0xc1,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0xc1,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0xc1,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc1, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0xc1,reg 0x30,val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0xc2,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0xc2,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0xc2,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0xc2,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0xc2,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0xc2,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc2, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0xc2,reg 0x30,val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0xc3,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0xc3,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0xc3,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0xc3,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0xc3,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0xc3,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0xc3,reg 0x30,val 0x0 PCI: 00:18.0 b8 * [0xe0000000 - 0xf81fffff] mem compute_allocate_mem: base: f8200000 size: 18200000 align: 28 gran: 0 done ASSIGN RESOURCES, bus 0 PCI: 00:18.0 compute_allocate_io: base: 00001000 size: 00002000 align: 12 gran: 12 Read config 32 bus 1,devfn 0x2b,reg 0x10,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x10, val 0xffffffff Read config 32 bus 1,devfn 0x2b,reg 0x10,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x10, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x10,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x10, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x14,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x14, val 0xffffffff Read config 32 bus 1,devfn 0x2b,reg 0x14,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x14, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x14,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x14, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x18,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x18, val 0xffffffff Read config 32 bus 1,devfn 0x2b,reg 0x18,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x18, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x18,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x18, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x1c,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x1c, val 0xffffffff Read config 32 bus 1,devfn 0x2b,reg 0x1c,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x1c, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x1c,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x1c, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x20,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x20, val 0xffffffff Read config 32 bus 1,devfn 0x2b,reg 0x20,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x20, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x20,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x20, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x24,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x24, val 0xffffffff Read config 32 bus 1,devfn 0x2b,reg 0x24,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x24, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x24,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x24, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x30,val 0x0 PCI: 01:02.0 1c * [0x00001000 - 0x00001fff] io PCI: 01:04.0 1c * [0x00002000 - 0x00001fff] io PCI: 01:05.5 10 * [0x00002000 - 0x000020ff] io PCI: 01:05.6 10 * [0x00002400 - 0x000024ff] io PCI: 01:05.6 14 * [0x00002800 - 0x0000287f] io PCI: 01:05.5 14 * [0x00002880 - 0x000028bf] io PCI: 01:05.2 10 * [0x000028c0 - 0x000028df] io PCI: 01:05.1 20 * [0x000028e0 - 0x000028ef] io compute_allocate_io: base: 000028f0 size: 00002000 align: 12 gran: 12 done Read config 32 bus 0,devfn 0xc1,reg 0xc0,val 0x3 Read config 32 bus 0,devfn 0xc1,reg 0xc4,val 0x1fff000 Write config 32 bus 0, devfn 0xc1, reg 0xc4, val 0x2000 Write config 32 bus 0, devfn 0xc1, reg 0xc0, val 0x1003 PCI: 00:18.0 c0 <- [0x00001000 - 0x00002fff] node 0 link 0 io PCI: 00:18.0 compute_allocate_mem: base: e0000000 size: 18200000 align: 28 gran: 20 Read config 32 bus 1,devfn 0x2b,reg 0x10,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x10, val 0xffffffff Read config 32 bus 1,devfn 0x2b,reg 0x10,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x10, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x10,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x10, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x14,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x14, val 0xffffffff Read config 32 bus 1,devfn 0x2b,reg 0x14,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x14, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x14,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x14, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x18,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x18, val 0xffffffff Read config 32 bus 1,devfn 0x2b,reg 0x18,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x18, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x18,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x18, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x1c,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x1c, val 0xffffffff Read config 32 bus 1,devfn 0x2b,reg 0x1c,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x1c, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x1c,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x1c, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x20,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x20, val 0xffffffff Read config 32 bus 1,devfn 0x2b,reg 0x20,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x20, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x20,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x20, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x24,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x24, val 0xffffffff Read config 32 bus 1,devfn 0x2b,reg 0x24,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x24, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x24,val 0x0 Write config 32 bus 1, devfn 0x2b, reg 0x24, val 0x0 Read config 32 bus 1,devfn 0x2b,reg 0x30,val 0x0 PCI: 01:01.0 10 * [0xe0000000 - 0xefffffff] prefmem PCI: 01:02.0 24 * [0xf0000000 - 0xf7ffffff] prefmem PCI: 01:02.0 20 * [0xf8000000 - 0xf80fffff] mem PCI: 01:04.0 20 * [0xf8100000 - 0xf81fffff] mem PCI: 01:04.0 24 * [0xf8200000 - 0xf81fffff] prefmem compute_allocate_mem: base: f8200000 size: 18200000 align: 28 gran: 20 done Read config 32 bus 0,devfn 0xc1,reg 0xb8,val 0xfc0003 Read config 32 bus 0,devfn 0xc1,reg 0xbc,val 0xffff00 Write config 32 bus 0, devfn 0xc1, reg 0xbc, val 0xf81f00 Write config 32 bus 0, devfn 0xc1, reg 0xb8, val 0xe00003 PCI: 00:18.0 b8 <- [0xe0000000 - 0xf81fffff] node 0 link 0 mem ASSIGN RESOURCES, bus 1 Write config 32 bus 1, devfn 0x8, reg 0x10, val 0xe0000000 Write config 32 bus 1, devfn 0x8, reg 0x14, val 0x0 PCI: 01:01.0 10 <- [0xe0000000 - 0xefffffff] prefmem Write config 8 bus 1, devfn 0x8, reg 0xd, val 0x40 Read config 8 bus 1,devfn 0x8,reg 0x3d,val 0x0 Write config 8 bus 1, devfn 0x8, reg 0xc, val 0x10 PCI: 01:02.0 compute_allocate_io: base: 00001000 size: 00001000 align: 12 gran: 12 PCI: 02:00.0 14 * [0x00001000 - 0x000010ff] io compute_allocate_io: base: 00001100 size: 00001000 align: 12 gran: 12 done Write config 8 bus 1, devfn 0x10, reg 0x1c, val 0x10 Write config 8 bus 1, devfn 0x10, reg 0x1d, val 0x1f Write config 16 bus 1, devfn 0x10, reg 0x30, val 0x0 Write config 16 bus 1, devfn 0x10, reg 0x32, val 0x0 PCI: 01:02.0 1c <- [0x00001000 - 0x00001fff] bus 2 io PCI: 01:02.0 compute_allocate_prefmem: base: f0000000 size: 08000000 align: 27 gran: 20 PCI: 02:00.0 10 * [0xf0000000 - 0xf7ffffff] prefmem compute_allocate_prefmem: base: f8000000 size: 08000000 align: 27 gran: 20 done Write config 16 bus 1, devfn 0x10, reg 0x24, val 0xf000 Write config 16 bus 1, devfn 0x10, reg 0x26, val 0xf7ff Write config 32 bus 1, devfn 0x10, reg 0x28, val 0x0 Write config 32 bus 1, devfn 0x10, reg 0x2c, val 0x0 PCI: 01:02.0 24 <- [0xf0000000 - 0xf7ffffff] bus 2 prefmem PCI: 01:02.0 compute_allocate_mem: base: f8000000 size: 00100000 align: 20 gran: 20 PCI: 02:00.0 18 * [0xf8000000 - 0xf800ffff] mem compute_allocate_mem: base: f8010000 size: 00100000 align: 20 gran: 20 done Write config 16 bus 1, devfn 0x10, reg 0x20, val 0xf800 Write config 16 bus 1, devfn 0x10, reg 0x22, val 0xf80f PCI: 01:02.0 20 <- [0xf8000000 - 0xf80fffff] bus 2 mem ASSIGN RESOURCES, bus 2 Write config 32 bus 2, devfn 0x0, reg 0x10, val 0xf0000000 PCI: 02:00.0 10 <- [0xf0000000 - 0xf7ffffff] prefmem Write config 32 bus 2, devfn 0x0, reg 0x14, val 0x1001 PCI: 02:00.0 14 <- [0x00001000 - 0x000010ff] io Write config 32 bus 2, devfn 0x0, reg 0x18, val 0xf8000000 PCI: 02:00.0 18 <- [0xf8000000 - 0xf800ffff] mem Write config 8 bus 2, devfn 0x0, reg 0xd, val 0x40 Read config 8 bus 2,devfn 0x0,reg 0x3d,val 0x1 Write config 8 bus 2, devfn 0x0, reg 0x3c, val 0x0 Write config 8 bus 2, devfn 0x0, reg 0xc, val 0x10 ASSIGNED RESOURCES, bus 2 Write config 8 bus 1, devfn 0x10, reg 0xd, val 0x40 Write config 8 bus 1, devfn 0x10, reg 0x1b, val 0x40 Read config 8 bus 1,devfn 0x10,reg 0x3d,val 0x0 Write config 8 bus 1, devfn 0x10, reg 0xc, val 0x10 PCI: 01:04.0 compute_allocate_io: base: 00002000 size: 00000000 align: 12 gran: 12 compute_allocate_io: base: 00002000 size: 00000000 align: 12 gran: 12 done Write config 8 bus 1, devfn 0x20, reg 0x1c, val 0x20 Write config 8 bus 1, devfn 0x20, reg 0x1d, val 0x1f Write config 16 bus 1, devfn 0x20, reg 0x30, val 0x0 Write config 16 bus 1, devfn 0x20, reg 0x32, val 0x0 PCI: 01:04.0 1c <- [0x00002000 - 0x00001fff] bus 3 io PCI: 01:04.0 compute_allocate_prefmem: base: f8200000 size: 00000000 align: 20 gran: 20 compute_allocate_prefmem: base: f8200000 size: 00000000 align: 20 gran: 20 done Write config 16 bus 1, devfn 0x20, reg 0x24, val 0xf820 Write config 16 bus 1, devfn 0x20, reg 0x26, val 0xf81f Write config 32 bus 1, devfn 0x20, reg 0x28, val 0x0 Write config 32 bus 1, devfn 0x20, reg 0x2c, val 0x0 PCI: 01:04.0 24 <- [0xf8200000 - 0xf81fffff] bus 3 prefmem PCI: 01:04.0 compute_allocate_mem: base: f8100000 size: 00100000 align: 20 gran: 20 PCI: 03:05.0 10 * [0xf8100000 - 0xf810ffff] mem PCI: 03:00.0 10 * [0xf8110000 - 0xf8110fff] mem PCI: 03:00.1 10 * [0xf8111000 - 0xf8111fff] mem PCI: 03:01.0 10 * [0xf8112000 - 0xf8112fff] mem PCI: 03:00.2 10 * [0xf8113000 - 0xf81130ff] mem PCI: 03:00.2 14 * [0xf8114000 - 0xf811401f] mem compute_allocate_mem: base: f8114020 size: 00100000 align: 20 gran: 20 done Write config 16 bus 1, devfn 0x20, reg 0x20, val 0xf810 Write config 16 bus 1, devfn 0x20, reg 0x22, val 0xf81f PCI: 01:04.0 20 <- [0xf8100000 - 0xf81fffff] bus 3 mem ASSIGN RESOURCES, bus 3 Write config 32 bus 3, devfn 0x0, reg 0x10, val 0xf8110000 PCI: 03:00.0 10 <- [0xf8110000 - 0xf8110fff] mem Write config 8 bus 3, devfn 0x0, reg 0xd, val 0x40 Read config 8 bus 3,devfn 0x0,reg 0x3d,val 0x4 Write config 8 bus 3, devfn 0x0, reg 0x3c, val 0x0 Write config 8 bus 3, devfn 0x0, reg 0xc, val 0x10 Write config 32 bus 3, devfn 0x1, reg 0x10, val 0xf8111000 PCI: 03:00.1 10 <- [0xf8111000 - 0xf8111fff] mem Write config 8 bus 3, devfn 0x1, reg 0xd, val 0x40 Read config 8 bus 3,devfn 0x1,reg 0x3d,val 0x4 Write config 8 bus 3, devfn 0x1, reg 0x3c, val 0x0 Write config 8 bus 3, devfn 0x1, reg 0xc, val 0x10 Write config 32 bus 3, devfn 0x2, reg 0x10, val 0xf8113000 PCI: 03:00.2 10 <- [0xf8113000 - 0xf81130ff] mem Write config 32 bus 3, devfn 0x2, reg 0x14, val 0xf8114000 PCI: 03:00.2 14 <- [0xf8114000 - 0xf811401f] mem Write config 8 bus 3, devfn 0x2, reg 0xd, val 0x40 Read config 8 bus 3,devfn 0x2,reg 0x3d,val 0x4 Write config 8 bus 3, devfn 0x2, reg 0x3c, val 0x0 Write config 8 bus 3, devfn 0x2, reg 0xc, val 0x10 Write config 32 bus 3, devfn 0x8, reg 0x10, val 0xf8112000 PCI: 03:01.0 10 <- [0xf8112000 - 0xf8112fff] mem Write config 8 bus 3, devfn 0x8, reg 0xd, val 0x40 Read config 8 bus 3,devfn 0x8,reg 0x3d,val 0x1 Write config 8 bus 3, devfn 0x8, reg 0x3c, val 0x0 Write config 8 bus 3, devfn 0x8, reg 0xc, val 0x10 Write config 32 bus 3, devfn 0x28, reg 0x10, val 0xf8100000 Write config 32 bus 3, devfn 0x28, reg 0x14, val 0x0 PCI: 03:05.0 10 <- [0xf8100000 - 0xf810ffff] mem Write config 8 bus 3, devfn 0x28, reg 0xd, val 0x40 Read config 8 bus 3,devfn 0x28,reg 0x3d,val 0x1 Write config 8 bus 3, devfn 0x28, reg 0x3c, val 0x0 Write config 8 bus 3, devfn 0x28, reg 0xc, val 0x10 ASSIGNED RESOURCES, bus 3 Write config 8 bus 1, devfn 0x20, reg 0xd, val 0x40 Write config 8 bus 1, devfn 0x20, reg 0x1b, val 0x40 Read config 8 bus 1,devfn 0x20,reg 0x3d,val 0x0 Write config 8 bus 1, devfn 0x20, reg 0xc, val 0x10 Write config 32 bus 1, devfn 0x28, reg 0x0, val 0x1 PCI: 01:05.0 00 <- [0x00000000 - 0xffffffff] io Write config 32 bus 1, devfn 0x28, reg 0x0, val 0x0 PCI: 01:05.0 00 <- [0x00000000 - 0xffffffff] mem Write config 8 bus 1, devfn 0x28, reg 0xd, val 0x40 Read config 8 bus 1,devfn 0x28,reg 0x3d,val 0x0 Write config 8 bus 1, devfn 0x28, reg 0xc, val 0x10 Write config 32 bus 1, devfn 0x29, reg 0x20, val 0x28e1 PCI: 01:05.1 20 <- [0x000028e0 - 0x000028ef] io Write config 8 bus 1, devfn 0x29, reg 0xd, val 0x40 Read config 8 bus 1,devfn 0x29,reg 0x3d,val 0x0 Write config 8 bus 1, devfn 0x29, reg 0xc, val 0x10 Write config 32 bus 1, devfn 0x2a, reg 0x10, val 0x28c1 PCI: 01:05.2 10 <- [0x000028c0 - 0x000028df] io Write config 8 bus 1, devfn 0x2a, reg 0xd, val 0x40 Read config 8 bus 1,devfn 0x2a,reg 0x3d,val 0x4 Write config 8 bus 1, devfn 0x2a, reg 0x3c, val 0x0 Write config 8 bus 1, devfn 0x2a, reg 0xc, val 0x10 Write config 8 bus 1, devfn 0x2b, reg 0xd, val 0x40 Read config 8 bus 1,devfn 0x2b,reg 0x3d,val 0x0 Write config 8 bus 1, devfn 0x2b, reg 0xc, val 0x10 Write config 32 bus 1, devfn 0x2d, reg 0x10, val 0x2001 PCI: 01:05.5 10 <- [0x00002000 - 0x000020ff] io Write config 32 bus 1, devfn 0x2d, reg 0x14, val 0x2881 PCI: 01:05.5 14 <- [0x00002880 - 0x000028bf] io Write config 8 bus 1, devfn 0x2d, reg 0xd, val 0x40 Read config 8 bus 1,devfn 0x2d,reg 0x3d,val 0x2 Write config 8 bus 1, devfn 0x2d, reg 0x3c, val 0x0 Write config 8 bus 1, devfn 0x2d, reg 0xc, val 0x10 Write config 32 bus 1, devfn 0x2e, reg 0x10, val 0x2401 PCI: 01:05.6 10 <- [0x00002400 - 0x000024ff] io Write config 32 bus 1, devfn 0x2e, reg 0x14, val 0x2801 PCI: 01:05.6 14 <- [0x00002800 - 0x0000287f] io Write config 8 bus 1, devfn 0x2e, reg 0xd, val 0x40 Read config 8 bus 1,devfn 0x2e,reg 0x3d,val 0x2 Write config 8 bus 1, devfn 0x2e, reg 0x3c, val 0x0 Write config 8 bus 1, devfn 0x2e, reg 0xc, val 0x10 ASSIGNED RESOURCES, bus 1 Write config 8 bus 0, devfn 0xc1, reg 0xd, val 0x40 Read config 8 bus 0,devfn 0xc1,reg 0x3d,val 0x0 Write config 8 bus 0, devfn 0xc1, reg 0xc, val 0x10 Write config 8 bus 0, devfn 0xc2, reg 0xd, val 0x40 Read config 8 bus 0,devfn 0xc2,reg 0x3d,val 0x0 Write config 8 bus 0, devfn 0xc2, reg 0xc, val 0x10 Write config 8 bus 0, devfn 0xc3, reg 0xd, val 0x40 Read config 8 bus 0,devfn 0xc3,reg 0x3d,val 0x0 Write config 8 bus 0, devfn 0xc3, reg 0xc, val 0x10 ASSIGNED RESOURCES, bus 0 Allocating VGA resource done. Enabling resourcess... Read config 16 bus 0,devfn 0xc0,reg 0x4,val 0x0 PCI: 00:18.0 cmd <- 00 Write config 16 bus 0, devfn 0xc0, reg 0x4, val 0x0 Read config 16 bus 1,devfn 0x8,reg 0x4,val 0x6 PCI: 01:01.0 cmd <- 06 Write config 16 bus 1, devfn 0x8, reg 0x4, val 0x6 Read config 16 bus 1,devfn 0x10,reg 0x3e,val 0x0 PCI: 01:02.0 bridge ctrl <- 003e Write config 16 bus 1, devfn 0x10, reg 0x3e, val 0x3e Read config 16 bus 1,devfn 0x10,reg 0x4,val 0x0 PCI: 01:02.0 cmd <- 07 Write config 16 bus 1, devfn 0x10, reg 0x4, val 0x7 Read config 16 bus 2,devfn 0x0,reg 0x4,val 0x80 PCI: 02:00.0 cmd <- 83 Write config 16 bus 2, devfn 0x0, reg 0x4, val 0x83 Read config 16 bus 1,devfn 0x20,reg 0x3e,val 0x0 PCI: 01:04.0 bridge ctrl <- 0000 Write config 16 bus 1, devfn 0x20, reg 0x3e, val 0x0 Read config 16 bus 1,devfn 0x20,reg 0x4,val 0x0 PCI: 01:04.0 cmd <- 07 Write config 16 bus 1, devfn 0x20, reg 0x4, val 0x7 Read config 16 bus 3,devfn 0x0,reg 0x4,val 0x0 PCI: 03:00.0 cmd <- 02 Write config 16 bus 3, devfn 0x0, reg 0x4, val 0x2 Read config 16 bus 3,devfn 0x1,reg 0x4,val 0x0 PCI: 03:00.1 cmd <- 02 Write config 16 bus 3, devfn 0x1, reg 0x4, val 0x2 Read config 16 bus 3,devfn 0x2,reg 0x4,val 0x0 PCI: 03:00.2 cmd <- 02 Write config 16 bus 3, devfn 0x2, reg 0x4, val 0x2 Read config 16 bus 3,devfn 0x8,reg 0x4,val 0x0 PCI: 03:01.0 cmd <- 02 Write config 16 bus 3, devfn 0x8, reg 0x4, val 0x2 Read config 16 bus 3,devfn 0x28,reg 0x4,val 0x0 PCI: 03:05.0 cmd <- 02 Write config 16 bus 3, devfn 0x28, reg 0x4, val 0x2 Read config 16 bus 1,devfn 0x28,reg 0x4,val 0xf PCI: 01:05.0 cmd <- 0f Write config 16 bus 1, devfn 0x28, reg 0x4, val 0xf Read config 16 bus 1,devfn 0x29,reg 0x4,val 0x0 PCI: 01:05.1 cmd <- 01 Write config 16 bus 1, devfn 0x29, reg 0x4, val 0x1 Read config 16 bus 1,devfn 0x2a,reg 0x4,val 0x0 PCI: 01:05.2 cmd <- 01 Write config 16 bus 1, devfn 0x2a, reg 0x4, val 0x1 Read config 16 bus 1,devfn 0x2b,reg 0x4,val 0x0 PCI: 01:05.3 cmd <- 00 Write config 16 bus 1, devfn 0x2b, reg 0x4, val 0x0 Read config 16 bus 1,devfn 0x2d,reg 0x4,val 0x0 PCI: 01:05.5 cmd <- 01 Write config 16 bus 1, devfn 0x2d, reg 0x4, val 0x1 Read config 16 bus 1,devfn 0x2e,reg 0x4,val 0x0 PCI: 01:05.6 cmd <- 01 Write config 16 bus 1, devfn 0x2e, reg 0x4, val 0x1 Read config 16 bus 0,devfn 0xc1,reg 0x4,val 0x0 PCI: 00:18.1 cmd <- 00 Write config 16 bus 0, devfn 0xc1, reg 0x4, val 0x0 Read config 16 bus 0,devfn 0xc2,reg 0x4,val 0x0 PCI: 00:18.2 cmd <- 00 Write config 16 bus 0, devfn 0xc2, reg 0x4, val 0x0 Read config 16 bus 0,devfn 0xc3,reg 0x4,val 0x0 PCI: 00:18.3 cmd <- 00 Write config 16 bus 0, devfn 0xc3, reg 0x4, val 0x0 done. Initializing devices... PCI: 00:18.3 init NB: Function 3 Misc Control.. Read config 32 bus 0,devfn 0xc3,reg 0x44,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0x44, val 0x2000040 Read config 32 bus 0,devfn 0xc3,reg 0xd4,val 0x0 Write config 32 bus 0, devfn 0xc3, reg 0xd4, val 0x4e20707