Index: src/mainboard/asrock/e350m1/acpi_tables.c
===================================================================
--- src/mainboard/asrock/e350m1/acpi_tables.c	(revision 6600)
+++ src/mainboard/asrock/e350m1/acpi_tables.c	(working copy)
@@ -64,7 +64,7 @@
   current = acpi_create_madt_lapics(current);
 
   /* Write SB800 IOAPIC, only one */
-  current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
+  current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
              IO_APIC_ADDR, 0);
 
   current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
@@ -129,6 +129,31 @@
   acpi_write_rsdp(rsdp, rsdt, NULL);
   acpi_write_rsdt(rsdt);
 
+  /* DSDT */
+  current   = ( current + 0x07) & -0x08;
+  printk(BIOS_DEBUG, "ACPI:    * DSDT at %lx\n", current);
+  dsdt = (acpi_header_t *)current; // it will used by fadt
+  memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+  current += dsdt->length;
+  memcpy(dsdt, &AmlCode, dsdt->length);
+  printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+
+  /* FACS */ // it needs 64 bit alignment
+  current   = ( current + 0x07) & -0x08;
+  printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
+  facs = (acpi_facs_t *) current; // it will be used by fadt
+  current += sizeof(acpi_facs_t);
+  acpi_create_facs(facs);
+
+  /* FDAT */
+  current   = ( current + 0x07) & -0x08;
+  printk(BIOS_DEBUG, "ACPI:    * FADT at %lx\n", current);
+  fadt = (acpi_fadt_t *) current;
+  current += sizeof(acpi_fadt_t);
+
+  acpi_create_fadt(fadt, facs, dsdt);
+  acpi_add_table(rsdp, fadt);
+
   /*
    * We explicitly add these tables later on:
    */
@@ -193,31 +218,6 @@
 
   printk(BIOS_DEBUG, "ACPI:    * SSDT for PState at %lx\n", current);
 
-  /* DSDT */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:    * DSDT at %lx\n", current);
-  dsdt = (acpi_header_t *)current; // it will used by fadt
-  memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
-  current += dsdt->length;
-  memcpy(dsdt, &AmlCode, dsdt->length);
-  printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
-
-  /* FACS */ // it needs 64 bit alignment
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
-  facs = (acpi_facs_t *) current; // it will be used by fadt
-  current += sizeof(acpi_facs_t);
-  acpi_create_facs(facs);
-
-  /* FDAT */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:    * FADT at %lx\n", current);
-  fadt = (acpi_fadt_t *) current;
-  current += sizeof(acpi_fadt_t);
-
-  acpi_create_fadt(fadt, facs, dsdt);
-  acpi_add_table(rsdp, fadt);
-
 #if DUMP_ACPI_TABLES == 1
   printk(BIOS_DEBUG, "rsdp\n");
   dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
Index: src/mainboard/asrock/e350m1/agesawrapper.c
===================================================================
--- src/mainboard/asrock/e350m1/agesawrapper.c	(revision 6600)
+++ src/mainboard/asrock/e350m1/agesawrapper.c	(working copy)
@@ -85,38 +85,39 @@
   PCI_ADDR                      PciAddress;
   AMD_CONFIG_PARAMS             StdHeader;
   
-  /* Enable MMIO on AMD CPU Address Map Controller */
-  
-  /* Start to set MMIO 0000A0000-0000BFFFF to Node0 Link0 */
+  /* Enable legacy video routing: D18F1xF4 VGA Enable */
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
+  PciData = 1;
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+
+  /* The platform BIOS needs to ensure the memory ranges of SB800 legacy
+   * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
+   * set to non-posted regions.
+   */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
-  PciData = 0x00000B00;
+  PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
+  PciData |= 1 << 7;    // set NP (non-posted) bit
   LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
-  PciData = 0x00000A03;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  
-  /* Set TOM-DFFFFFFF to Node0 Link0. */
+  PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+   
+  /* Map the remaining PCI hole as posted MMIO */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
-  PciData = 0x00DFFF00;
+  PciData = 0x00FECF00; // last address before non-posted range
   LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
   LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
   MsrReg = (MsrReg >> 8) | 3;
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
   PciData = (UINT32)MsrReg;
   LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-  /* Set E0000000-FFFFFFFF to Node0 Link0 with NP set. */
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xBC);
-  PciData = 0x00FFFF00 | 0x80;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xB8);
-  PciData = (PCIE_BASE_ADDRESS >> 8) | 03;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  /* Start to set PCIIO 0000-FFFF to Node0 Link0 with ISA&VGA set. */
+   
+  /* Send all IO (0000-FFFF) to southbridge. */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
   PciData = 0x0000F000;
   LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
-  PciData = 0x00000013;
+  PciData = 0x00000003;
   LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
   Status = AGESA_SUCCESS;
   return (UINT32)Status;
@@ -137,7 +138,8 @@
    Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
    Address MSR register.
   */
-  MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (8 << 2) | 1;
+
+  MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
   LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
   
   /*
@@ -155,13 +157,6 @@
   PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
   LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
   
-
-  /* Set ROM cache onto WP to decrease post time */
-  MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5;
-  LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
-  MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800;
-  LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
-
   Status = AGESA_SUCCESS;
   return (UINT32)Status;
 }
@@ -442,33 +437,32 @@
   )
 {
   AGESA_STATUS Status;
-  AMD_LATE_PARAMS AmdLateParams;
+  AMD_INTERFACE_PARAMS AmdParamStruct = {0};
+  AMD_LATE_PARAMS *AmdLateParams;
 
-  LibAmdMemFill (&AmdLateParams,
-                 0,
-                 sizeof (AMD_LATE_PARAMS),
-                 &(AmdLateParams.StdHeader));
+  return 0; // this causes bad ACPI SSDT, need to debug
 
-  AmdLateParams.StdHeader.AltImageBasePtr = 0;
-  AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdLateParams.StdHeader.Func = 0;
-  AmdLateParams.StdHeader.ImageBasePtr = 0;
-
-  Status = AmdInitLate (&AmdLateParams);
+  AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
+  AmdParamStruct.AllocationMethod = PostMemDram;
+  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+  AmdCreateStruct (&AmdParamStruct);
+  AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr;
+  Status = AmdInitLate (AmdLateParams);
   if (Status != AGESA_SUCCESS) {
     agesawrapper_amdreadeventlog();
     ASSERT(Status == AGESA_SUCCESS);
   }
 
-  DmiTable       = AmdLateParams.DmiTable;
-  AcpiPstate     = AmdLateParams.AcpiPState;
-  AcpiSrat       = AmdLateParams.AcpiSrat;
-  AcpiSlit       = AmdLateParams.AcpiSlit;
+  DmiTable    = AmdLateParams->DmiTable;
+  AcpiPstate  = AmdLateParams->AcpiPState;
+  AcpiSrat    = AmdLateParams->AcpiSrat;
+  AcpiSlit    = AmdLateParams->AcpiSlit;
 
-  AcpiWheaMce    = AmdLateParams.AcpiWheaMce;
-  AcpiWheaCmc    = AmdLateParams.AcpiWheaCmc;
-  AcpiAlib       = AmdLateParams.AcpiAlib;
+  AcpiWheaMce = AmdLateParams->AcpiWheaMce;
+  AcpiWheaCmc = AmdLateParams->AcpiWheaCmc;
+  AcpiAlib    = AmdLateParams->AcpiAlib;
 
+  AmdReleaseStruct (&AmdParamStruct);
   return (UINT32)Status;
 }
 
Index: src/mainboard/asrock/e350m1/BiosCallOuts.c
===================================================================
--- src/mainboard/asrock/e350m1/BiosCallOuts.c	(revision 6600)
+++ src/mainboard/asrock/e350m1/BiosCallOuts.c	(working copy)
@@ -512,6 +512,9 @@
       Data8 &= ~(UINT8)BIT6;
       Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
   }
+
+  // disable memory clear for boot time reduction
+  MemData->ParameterListPtr->EnableMemClr = FALSE;
   return Status;
 }
 /*  Call the host environment interface to provide a user hook opportunity. */
Index: src/mainboard/asrock/e350m1/buildOpts.c
===================================================================
--- src/mainboard/asrock/e350m1/buildOpts.c	(revision 6600)
+++ src/mainboard/asrock/e350m1/buildOpts.c	(working copy)
@@ -80,16 +80,16 @@
 #define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT     TRUE
 
 #define BLDOPT_REMOVE_UDIMMS_SUPPORT          FALSE
-//#define BLDOPT_REMOVE_RDIMMS_SUPPORT        TRUE
+#define BLDOPT_REMOVE_RDIMMS_SUPPORT        TRUE
 #define BLDOPT_REMOVE_LRDIMMS_SUPPORT         FALSE
 #define BLDOPT_REMOVE_ECC_SUPPORT             FALSE
 //#define BLDOPT_REMOVE_DCT_INTERLEAVE        TRUE
 #define BLDOPT_REMOVE_BANK_INTERLEAVE         FALSE
-//#define BLDOPT_REMOVE_NODE_INTERLEAVE       TRUE
+#define BLDOPT_REMOVE_NODE_INTERLEAVE       TRUE
 #define BLDOPT_REMOVE_PARALLEL_TRAINING       FALSE
 #define BLDOPT_REMOVE_DQS_TRAINING            FALSE
-//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT    TRUE
-//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT     TRUE
+#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT    TRUE
+#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT     TRUE
 #define BLDOPT_REMOVE_ACPI_PSTATES          FALSE
   #define BLDCFG_REMOVE_ACPI_PSTATES_PPC        FALSE
   #define BLDCFG_REMOVE_ACPI_PSTATES_PCT        FALSE
@@ -97,17 +97,17 @@
   #define BLDCFG_REMOVE_ACPI_PSTATES_PSS        FALSE
   #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS       FALSE
   #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT     FALSE
-//#define BLDOPT_REMOVE_SRAT            TRUE
-//#define BLDOPT_REMOVE_SLIT            TRUE
-//#define BLDOPT_REMOVE_WHEA            TRUE
-//#define BLDOPT_REMOVE_DMI             TRUE
-//#define BLDOPT_REMOVE_HT_ASSIST         TRUE
-//#define BLDOPT_REMOVE_ATM_MODE          TRUE
+#define BLDOPT_REMOVE_SRAT            TRUE
+#define BLDOPT_REMOVE_SLIT            TRUE
+#define BLDOPT_REMOVE_WHEA            TRUE
+#define BLDOPT_REMOVE_DMI             TRUE
+#define BLDOPT_REMOVE_HT_ASSIST         TRUE
+#define BLDOPT_REMOVE_ATM_MODE          TRUE
 //#define BLDOPT_REMOVE_MSG_BASED_C1E       TRUE
 //#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE  
 #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT     FALSE
 //#define BLDOPT_REMOVE_C6_STATE          TRUE
-//#define BLDOPT_REMOVE_GFX_RECOVERY        TRUE
+#define BLDOPT_REMOVE_GFX_RECOVERY        TRUE
 #define BLDOPT_REMOVE_EARLY_SAMPLES            TRUE
 
 /*
@@ -123,7 +123,7 @@
 #define AGESA_ENTRY_INIT_S3SAVE                   TRUE
 #define AGESA_ENTRY_INIT_RESUME                   TRUE
 #define AGESA_ENTRY_INIT_LATE_RESTORE             FALSE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES         TRUE
+#define AGESA_ENTRY_INIT_GENERAL_SERVICES         FALSE
 
 /* 
  * Agesa configuration values selection.  
Index: src/mainboard/asrock/e350m1/devicetree.cb
===================================================================
--- src/mainboard/asrock/e350m1/devicetree.cb	(revision 6600)
+++ src/mainboard/asrock/e350m1/devicetree.cb	(working copy)
@@ -96,15 +96,15 @@
 								irq 0x70 = 5
 							end
 						end
-					end #LPC
-  					device pci 14.4 on end # PCI 0x4384
-	  				device pci 14.5 on end # USB 2
-					device pci 15.0 on end # PCIe PortA
-					device pci 15.1 on end # PCIe PortB
-					device pci 15.2 on end # PCIe PortC
-					device pci 15.3 on end # PCIe PortD
-					register "gpp_configuration" = "4" #1:1:1:1
-		  			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
+					end #LPC
+  					device pci 14.4 on  end # PCI 0x4384
+	  				device pci 14.5 on  end # USB 2
+					device pci 15.0 off end # PCIe PortA
+					device pci 15.1 off end # PCIe PortB
+					device pci 15.2 off end # PCIe PortC
+					device pci 15.3 off end # PCIe PortD
+					register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
+		  			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
 				end	#southbridge/amd/cimx_wrapper/sb800
 #                       end #  device pci 18.0
 # These seem unnecessary
Index: src/mainboard/asrock/e350m1/dsdt.asl
===================================================================
--- src/mainboard/asrock/e350m1/dsdt.asl	(revision 6600)
+++ src/mainboard/asrock/e350m1/dsdt.asl	(working copy)
@@ -36,7 +36,7 @@
 	Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
 	Name(PBLN, 0x0)	/* Length of BIOS area */
 
-	Name(PCBA, 0xE0000000)	/* Base address of PCIe config space */
+	Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)	/* Base address of PCIe config space */
 	Name(HPBA, 0xFED00000)	/* Base address of HPET table */
 
 	Name(SSFG, 0x0D)		/* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
@@ -1379,7 +1379,7 @@
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_HID, EISAID("PNP0B00"))   /* AT Real Time Clock (not PIIX4 compatible) */
 					Name(_CRS, ResourceTemplate() {
 						IRQNoFlags(){8}
 						IO(Decode16,0x0070, 0x0070, 0, 2)
@@ -1483,9 +1483,8 @@
 					0xF300			/* length */
 				)
 
-#if 0
-				Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
 				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) 	/* VGA memory space */
+#if 0
 				Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1)	/* Assume C0000-E0000 empty */
 				Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS)   /* BIOS ROM area */
 
Index: src/mainboard/asrock/e350m1/fadt.c
===================================================================
--- src/mainboard/asrock/e350m1/fadt.c	(revision 6600)
+++ src/mainboard/asrock/e350m1/fadt.c	(working copy)
@@ -53,7 +53,7 @@
 	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
 	memcpy(header->signature, "FACP", 4);
 	header->length = 244;
-	header->revision = 1;
+	header->revision = 3;
 	memcpy(header->oem_id, OEM_ID, 6);
 	memcpy(header->oem_table_id, "COREBOOT", 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);
Index: src/mainboard/asrock/e350m1/get_bus_conf.c
===================================================================
--- src/mainboard/asrock/e350m1/get_bus_conf.c	(revision 6600)
+++ src/mainboard/asrock/e350m1/get_bus_conf.c	(working copy)
@@ -42,25 +42,12 @@
   0x0000ff0,
 };
 
-/*
-* HT Chain device num, actually it is unit id base of every ht device in chain,
-* assume every chain only have 4 ht device at most
-*/
-u32 hcdnx[] = {
-  0x20202020,
-};
-
 u32 bus_type[256];
-
 u32 sbdn_sb800;
 
-//KZ [092110]extern void get_pci1234(void);
-
 static u32 get_bus_conf_done = 0;
 
 
-
-
 void get_bus_conf(void)
 {
   u32 apicid_base;
@@ -138,9 +125,6 @@
 
   /* I/O APICs:   APIC ID Version State   Address */
   bus_isa = 10;
-  apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
-//#if CONFIG_LOGICAL_CPUS==1
-//  apicid_base = get_apicid_base(1);
-//#endif
-  apicid_sb800 = apicid_base + 0;
+  apicid_base = CONFIG_MAX_CPUS;
+  apicid_sb800 = apicid_base;
 }
Index: src/mainboard/asrock/e350m1/Kconfig
===================================================================
--- src/mainboard/asrock/e350m1/Kconfig	(revision 6600)
+++ src/mainboard/asrock/e350m1/Kconfig	(working copy)
@@ -22,8 +22,6 @@
 config BOARD_SPECIFIC_OPTIONS # dummy
         def_bool y
   select ARCH_X86
-        select DIMM_DDR3
-        select DIMM_UNREGISTERED
   select CPU_AMD_AGESA_WRAPPER_FAMILY14
   select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14_ROOT_COMPLEX
   select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
@@ -42,7 +40,6 @@
   select AMDMCT
         select HAVE_ACPI_TABLES
   select BOARD_ROMSIZE_KB_4096
-  select ENABLE_APIC_EXT_ID
   select TINY_BOOTBLOCK
         select GFXUMA
 
@@ -86,18 +83,6 @@
         int
         default 2
 
-config SB_HT_CHAIN_ON_BUS0
-        int
-        default 1
-
-config HT_CHAIN_END_UNITID_BASE
-        hex
-        default 0x1
-
-config HT_CHAIN_UNITID_BASE
-        hex
-        default 0x0
-
 config IRQ_SLOT_COUNT
         int
         default 11
Index: src/mainboard/asrock/e350m1/mptable.c
===================================================================
--- src/mainboard/asrock/e350m1/mptable.c	(revision 6600)
+++ src/mainboard/asrock/e350m1/mptable.c	(working copy)
@@ -66,13 +66,13 @@
     
   dword = 0;
   dword = pm_ioread(0x34) & 0xF0;
-  dword |= (pm_ioread(0x35) & 0xFF) << 8;
-  dword |= (pm_ioread(0x36) & 0xFF) << 16;
-  dword |= (pm_ioread(0x37) & 0xFF) << 24;
-  smp_write_ioapic(mc, apicid_sb800, 0x11, dword);
-
-  for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
-    outb(byte | 0x80, 0xC00);
+  dword |= (pm_ioread(0x35) & 0xFF) << 8;
+  dword |= (pm_ioread(0x36) & 0xFF) << 16;
+  dword |= (pm_ioread(0x37) & 0xFF) << 24;
+  smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
+
+  for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+    outb(byte | 0x80, 0xC00);
     outb(intr_data[byte], 0xC01);
   }
 
Index: src/mainboard/asrock/e350m1/romstage.c
===================================================================
--- src/mainboard/asrock/e350m1/romstage.c	(revision 6600)
+++ src/mainboard/asrock/e350m1/romstage.c	(working copy)
@@ -44,9 +44,52 @@
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-  u32 val;
-  u8 reg8;
+  u32 val;
+  u8 reg8;
+
+  // all cores: allow caching of flash chip code and data
+  // (there are no cache-as-ram reliability concerns with family 14h)
+  __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
+  __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
+
+  // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
+  __writemsr (0xc0010062, 0);
+
+  if (boot_cpu())
+    {
+    u8 reg8;
+    // SB800: program AcpiMmioEn to enable MMIO access to MiscCntrl register
+    outb(0x24, 0xCD6);
+    reg8 = inb(0xCD7);
+    reg8 |= 1;
+    reg8 &= ~(1 << 1);
+    outb(reg8, 0xCD7);
+  
+    // program SB800 MiscCntrl
+    *(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
+    *(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */
+    }
 
+  // early enable of PrefetchEnSPIFromHost
+  if (boot_cpu())
+    {
+    __outdword (0xcf8, 0x8000a3b8);
+    __outdword (0xcfc, __indword (0xcfc) | 0 << 24);
+    }
+
+  // early enable of SPI 33 MHz fast mode read
+  if (boot_cpu())
+    {
+    volatile u32 *spiBase = (void *) 0xa0000000;
+    u32 save;
+    __outdword (0xcf8, 0x8000a3a0);
+    save = __indword (0xcfc);
+    __outdword (0xcfc, (u32) spiBase | 2); // set temp MMIO base
+    spiBase [3] = (spiBase [3] & ~(3 << 14)) | (1 << 14);
+    spiBase [0] |= 1 << 18; // fast read enable
+    __outdword (0xcfc, save); // clear temp base
+    }
+
   if (!cpu_init_detectedx && boot_cpu()) {
     post_code(0x30);
     sb_poweron_init();
@@ -55,18 +98,7 @@
     w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
     console_init();
   }
-	//reg8 = pmio_read(0x24);
-  outb(0x24, 0xCD6);
-  reg8 = inb(0xCD7);
-	reg8 |= 1;
-	reg8 &= ~(1 << 1);
-	//pmio_write(0x24, reg8);
-	outb(0x24, 0xCD6);
-	outb(reg8, 0xCD7);
 
-	*(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
-	*(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */
-
   /* Halt if there was a built in self test failure */
   post_code(0x34);
   report_bist_failure(bist);
