Hi

That MTRR setup looks suboptimal for sure, but not fatally flawed.
What's located at 0x77000000 till 0x80000000? I suspect it's just dram but maybe allocated for different purposes like TSEG, GFX stolen memory, ....
If you mark it as such during resource allocation the MTRR solution will be more optimised (see soc/intel/common/block/systemagent/systemagent.c).

Kind regards

Arthur

On Mon, Oct 25, 2021 at 5:05 PM Samek, Jan <jan.samek@siemens.com> wrote:
Hello coreboot Community,

After a long time, there's an update to this Tiger Lake issue:

For now, the masks in mca_configure() are used as a workaround to ignore the MCEs:

    --- a/src/soc/intel/common/block/cpu/cpulib.c
    +++ b/src/soc/intel/common/block/cpu/cpulib.c
    @@ -346,7 +346,7 @@ void mca_configure(void)
            for (i = 0; i < num_banks; i++) {
                    /* Initialize machine checks */
                    wrmsr(IA32_MC_CTL(i),
    -                       (msr_t) {.lo = 0xffffffff, .hi = 0xffffffff});
    +                       (msr_t) {.lo = 0, .hi = 0});  /* FIXME: MCEs temp. disabled */
            }

It was found by Werner that these MCEs are set by FSP-M. With possibility being wrong FSP parameters, SPD data etc. There was also a need to disable MCE checking in FSP-S UPD to get through the silicon init.

Nevertheless what after discussion with Intel and Werner, what seems to be the root cause, might be the MTRR setup. From what I see from the logs, the values indeed look somehow strange to me. Sorry, I have no clue yet how to set up MTRRs correctly or how they should look like.

    ...
    BS: BS_WRITE_TABLES run times (exec / console): 7 / 307 ms
    MTRR: Physical address space:
    0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
    0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
    0x00000000000c0000 - 0x0000000077000000 size 0x76f40000 type 6
    0x0000000077000000 - 0x0000000080000000 size 0x09000000 type 0
    0x0000000080000000 - 0x0000000090000000 size 0x10000000 type 1
    0x0000000090000000 - 0x0000000100000000 size 0x70000000 type 0
    0x0000000100000000 - 0x0000000480400000 size 0x380400000 type 6
    MTRR: Fixed MSR 0x250 0x0606060606060606
    MTRR: Fixed MSR 0x258 0x0606060606060606
    MTRR: Fixed MSR 0x259 0x0000000000000000
    MTRR: Fixed MSR 0x268 0x0606060606060606
    MTRR: Fixed MSR 0x269 0x0606060606060606
    MTRR: Fixed MSR 0x26a 0x0606060606060606
    MTRR: Fixed MSR 0x26b 0x0606060606060606
    MTRR: Fixed MSR 0x26c 0x0606060606060606
    MTRR: Fixed MSR 0x26d 0x0606060606060606
    MTRR: Fixed MSR 0x26e 0x0606060606060606
    MTRR: Fixed MSR 0x26f 0x0606060606060606
    call enable_fixed_mtrr()
    CPU physical address size: 39 bits
    MTRR: default type WB/UC MTRR counts: 6/7.
    MTRR: WB selected as default type.
    MTRR: 0 base 0x0000000077000000 mask 0x0000007fff000000 type 0
    MTRR: 1 base 0x0000000078000000 mask 0x0000007ff8000000 type 0
    MTRR: 2 base 0x0000000080000000 mask 0x0000007ff0000000 type 1
    MTRR: 3 base 0x0000000090000000 mask 0x0000007ff0000000 type 0
    MTRR: 4 base 0x00000000a0000000 mask 0x0000007fe0000000 type 0
    MTRR: 5 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0
    MTRR: Fixed MSR 0x250 0x0606060606060606
    MTRR: Fixed MSR 0x258 0x0606060606060606
    MTRR: Fixed MSR 0x259 0x0000000000000000
    MTRR: Fixed MSR 0x268 0x0606060606060606
    MTRR: Fixed MSR 0x269 0x0606060606060606
    MTRR: Fixed MSR 0x26a 0x0606060606060606
    MTRR: Fixed MSR 0x26b 0x0606060606060606
    MTRR: Fixed MSR 0x26c 0x0606060606060606
    MTRR: Fixed MSR 0x26d 0x0606060606060606
    MTRR: Fixed MSR 0x26e 0x0606060606060606
    MTRR: Fixed MSR 0x26f 0x0606060606060606
    MTRR: Fixed MSR 0x250 0x0606060606060606
    MTRR: Fixed MSR 0x250 0x0606060606060606
    MTRR: Fixed MSR 0x258 0x0606060606060606
    MTRR: Fixed MSR 0x259 0x0000000000000000
    MTRR: Fixed MSR 0x268 0x0606060606060606
    MTRR: Fixed MSR 0x269 0x0606060606060606
    MTRR: Fixed MSR 0x26a 0x0606060606060606
    MTRR: Fixed MSR 0x26b 0x0606060606060606
    MTRR: Fixed MSR 0x26c 0x0606060606060606
    MTRR: Fixed MSR 0x26d 0x0606060606060606
    MTRR: Fixed MSR 0x26e 0x0606060606060606
    MTRR: Fixed MSR 0x26f 0x0606060606060606
    MTRR: Fixed MSR 0x258 0x0606060606060606
    call enable_fixed_mtrr()
    MTRR: Fixed MSR 0x259 0x0000000000000000
    MTRR: Fixed MSR 0x268 0x0606060606060606
    MTRR: Fixed MSR 0x269 0x0606060606060606
    MTRR: Fixed MSR 0x26a 0x0606060606060606
    MTRR: Fixed MSR 0x26b 0x0606060606060606
    MTRR: Fixed MSR 0x26c 0x0606060606060606
    MTRR: Fixed MSR 0x26d 0x0606060606060606
    MTRR: Fixed MSR 0x26e 0x0606060606060606
    MTRR: Fixed MSR 0x26f 0x0606060606060606
    CPU physical address size: 39 bits
    call enable_fixed_mtrr()
    MTRR: Fixed MSR 0x250 0x0606060606060606
    call enable_fixed_mtrr()
    MTRR: Fixed MSR 0x258 0x0606060606060606
    MTRR: Fixed MSR 0x259 0x0000000000000000
    MTRR: Fixed MSR 0x268 0x0606060606060606
    MTRR: Fixed MSR 0x269 0x0606060606060606
    MTRR: Fixed MSR 0x26a 0x0606060606060606
    MTRR: Fixed MSR 0x26b 0x0606060606060606
    MTRR: Fixed MSR 0x26c 0x0606060606060606
    MTRR: Fixed MSR 0x26d 0x0606060606060606
    MTRR: Fixed MSR 0x26e 0x0606060606060606
    MTRR: Fixed MSR 0x26f 0x0606060606060606
    CPU physical address size: 39 bits
    call enable_fixed_mtrr()

    MTRR check
    Fixed MTRRs   : Enabled
    Variable MTRRs: Enabled

    MTRR: Fixed MSR 0x250 0x0606060606060606
    POST: 0x93
    MTRR: Fixed MSR 0x258 0x0606060606060606
    MTRR: Fixed MSR 0x259 0x0000000000000000
    MTRR: Fixed MSR 0x268 0x0606060606060606
    MTRR: Fixed MSR 0x269 0x0606060606060606
    MTRR: Fixed MSR 0x26a 0x0606060606060606
    MTRR: Fixed MSR 0x26b 0x0606060606060606
    MTRR: Fixed MSR 0x26c 0x0606060606060606
    MTRR: Fixed MSR 0x26d 0x0606060606060606
    MTRR: Fixed MSR 0x26e 0x0606060606060606
    MTRR: Fixed MSR 0x26f 0x0606060606060606
    BS: BS_WRITE_TABLES exit times (exec / console): 213 / 151 ms
    ...

Is this expected for MTRRs to look like this or is there something completely garbled?

The full log with MTRR debug info and maximum log level is attached.

Sorry for playing a blind guessing game here, the upstreaming of sources is still not solved on our side.

Thanks for any clues.

Regards,
Jan
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