I am not sure you have access to some kind of XDP or Jtag, but an general idea is after romcc complied the code may looks different. You may use objdump to double check that, such as compare the disasemble on DUT and disasemble from objdump.

I have not been able to work on that platform before, just a general idea.

On Wed, Feb 13, 2019, 3:32 PM Jonathan Zhang <jon.zhixiong.zhang@gmail.com> wrote:
Hi, I am working on porting coreboot to Skylake SP and OCP Tiogapass
with FSP 2.0. I have a strange issue that I hope to get some wisdom.
The boot hangs when executing this line "sub %ecx, %ebx" in
src/arch/x86/walkcbfs.S; the post code showing up is 0xb1.

When I add a spinloop before this statement "sub %ecx, %ebx", the
postcode stays at 0x21, which means code execution till this point is
smooth.

My codebase is based on current tip of upstream code. In the .config
file, following are set (greping  BOOTBLOCK):
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000
CONFIG_BOOTBLOCK_CPU_INIT="soc/intel/fsp_skylake_fsp/bootblock/bootblock.c"
CONFIG_ARCH_BOOTBLOCK_X86_32=y
CONFIG_BOOTBLOCK_SIMPLE=y
CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c"
CONFIG_BOOTBLOCK_CONSOLE=y
CONFIG_C_ENVIRONMENT_BOOTBLOCK=y

Any pointer is appreciated. Let me know if you need any additional information.

Thank you,
Jonathan
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