Index: src/southbridge/nvidia/ck804/Kconfig
===================================================================
--- src/southbridge/nvidia/ck804/Kconfig	(revision 5993)
+++ src/southbridge/nvidia/ck804/Kconfig	(working copy)
@@ -29,6 +29,14 @@
 	bool
 	default n if SOUTHBRIDGE_NVIDIA_CK804
 
+config CK804_PCI_E_X
+	int
+	default 4 if SOUTHBRIDGE_NVIDIA_CK804
+
+config CK804B_PCI_E_X
+	int
+	default 4 if SOUTHBRIDGE_NVIDIA_CK804
+
 config CK804_NUM
 	int
 	default 1 if SOUTHBRIDGE_NVIDIA_CK804
Index: src/southbridge/nvidia/ck804/ck804_early_setup.c
===================================================================
--- src/southbridge/nvidia/ck804/ck804_early_setup.c	(revision 5996)
+++ src/southbridge/nvidia/ck804/ck804_early_setup.c	(working copy)
@@ -56,30 +56,24 @@
 #define SYSCTRL_REG_POS 0x64
 
 /*
+ * Values for CONFIG_CK804_PCI_E_X and CONFIG_CK804B_PCI_E_X.
+ * Apparently some sort of lane configuration.
+ *
  *	16 1 1 2 :0
  *	 8 8 2 2 :1
  *	 8 8 4   :2
  *	 8 4 4 4 :3
  *	16 4     :4
-*/
+ */
 
-#ifndef CK804_PCI_E_X
-#define CK804_PCI_E_X 4
-#endif
-
 #if CONFIG_CK804_NUM > 1
 #define CK804B_ANACTRL_IO_BASE (ANACTRL_IO_BASE + 0x8000)
 #define CK804B_SYSCTRL_IO_BASE (SYSCTRL_IO_BASE + 0x8000)
 #ifndef CK804B_BUSN
 #define CK804B_BUSN 0x80
 #endif
-#ifndef CK804B_PCI_E_X
-#define CK804B_PCI_E_X 4
 #endif
-#endif
 
-#define CK804_CHIP_REV 3
-
 #if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
 #define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
 #else
@@ -258,9 +252,9 @@
 
 	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000,
 
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804_PCI_E_X << 4) | (1 << 8),
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804_PCI_E_X << 4) | (1 << 8),
 #if CONFIG_CK804_NUM > 1
-	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804B_PCI_E_X << 4) | (1 << 8),
+	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804B_PCI_E_X << 4) | (1 << 8),
 #endif
 
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)),
Index: src/southbridge/nvidia/ck804/ck804_early_setup_car.c
===================================================================
--- src/southbridge/nvidia/ck804/ck804_early_setup_car.c	(revision 5993)
+++ src/southbridge/nvidia/ck804/ck804_early_setup_car.c	(working copy)
@@ -54,23 +54,16 @@
 #define SYSCTRL_REG_POS 0x64
 
 /*
+ * Values for CONFIG_CK804_PCI_E_X and CONFIG_CK804B_PCI_E_X.
+ * Apparently some sort of lane configuration.
+ *
  *	16 1 1 2 :0
  *	 8 8 2 2 :1
  *	 8 8 4   :2
  *	 8 4 4 4 :3
  *	16 4     :4
-*/
+ */
 
-#ifndef CK804_PCI_E_X
-#define CK804_PCI_E_X 4
-#endif
-
-#ifndef CK804B_PCI_E_X
-#define CK804B_PCI_E_X 4
-#endif
-
-#define CK804_CHIP_REV 3
-
 #if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
 #define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
 #else
@@ -199,7 +192,7 @@
 
 		RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000,
 
-		RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804_PCI_E_X << 4) | (1 << 8),
+		RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804_PCI_E_X << 4) | (1 << 8),
 
 //SYSCTRL
 		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)),
@@ -275,7 +268,7 @@
 /* This line doesn't exist in the non-CAR version. */
 		RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000,
 
-		RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804B_PCI_E_X << 4) | (1 << 8),
+		RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804B_PCI_E_X << 4) | (1 << 8),
 
 #if CONFIG_CK804_USE_NIC
 		RES_PCI_IO, PCI_ADDR(0, 0xa, 0, 0xf8), 0xffffffbf, 0x00000040,