0 src/soc/intel/common/block/cse/cse.c:604: post_code(0); 0 src/vendorcode/google/chromeos/cr50_enable_update.c:136: post_code(0); 0x00 src/soc/amd/common/psp_verstage/include/psp_verstage.h:18: #define POSTCODE_ENTERED_PSP_VERSTAGE 0x00 0x00 src/soc/amd/common/psp_verstage/psp_verstage.c:214: svc_write_postcode(POSTCODE_ENTERED_PSP_VERSTAGE); 0x01 src/commonlib/include/commonlib/console/post_codes.h:37: #define POST_RESET_VECTOR_CORRECT 0x01 0x01 src/cpu/x86/entry16.S:46: post_code(POST_RESET_VECTOR_CORRECT) 0x01 src/soc/amd/common/psp_verstage/include/psp_verstage.h:19: #define POSTCODE_CONSOLE_INIT 0x01 0x01 src/soc/amd/common/psp_verstage/psp_verstage.c:219: svc_write_postcode(POSTCODE_CONSOLE_INIT); 0x02 src/soc/amd/common/psp_verstage/include/psp_verstage.h:20: #define POSTCODE_EARLY_INIT 0x02 0x02 src/soc/amd/common/psp_verstage/psp_verstage.c:223: svc_write_postcode(POSTCODE_EARLY_INIT); 0x03 src/soc/amd/common/psp_verstage/include/psp_verstage.h:21: #define POSTCODE_LATE_INIT 0x03 0x03 src/soc/amd/common/psp_verstage/psp_verstage.c:275: svc_write_postcode(POSTCODE_LATE_INIT); 0x04 src/soc/amd/common/psp_verstage/include/psp_verstage.h:22: #define POSTCODE_VERSTAGE_MAIN 0x04 0x04 src/soc/amd/common/psp_verstage/psp_verstage.c:283: post_code(POSTCODE_VERSTAGE_MAIN); 0x05 src/cpu/qemu-x86/bootblock.c:9: post_code(0x05); 0x05 src/soc/amd/common/psp_verstage/include/psp_verstage.h:23: #define POSTCODE_VERSTAGE_S0I3_RESUME 0x05 0x05 src/soc/amd/common/psp_verstage/psp_verstage.c:179: post_code(POSTCODE_VERSTAGE_S0I3_RESUME); 0x0e src/soc/amd/common/psp_verstage/include/psp_verstage.h:25: #define POSTCODE_SAVE_BUFFERS 0x0E 0x0e src/soc/amd/common/psp_verstage/psp_verstage.c:260: post_code(POSTCODE_SAVE_BUFFERS); 0x0e src/soc/amd/common/psp_verstage/psp_verstage.c:309: post_code(POSTCODE_SAVE_BUFFERS); 0x0f src/soc/amd/common/psp_verstage/include/psp_verstage.h:26: #define POSTCODE_UPDATE_BOOT_REGION 0x0F 0x0f src/soc/amd/common/psp_verstage/psp_verstage.c:294: post_code(POSTCODE_UPDATE_BOOT_REGION); 0x10 src/commonlib/include/commonlib/console/post_codes.h:45: #define POST_ENTER_PROTECTED_MODE 0x10 0x10 src/cpu/x86/entry32.S:34: post_code(POST_ENTER_PROTECTED_MODE) 0x11 src/commonlib/include/commonlib/console/post_codes.h:52: #define POST_PREPARE_RAMSTAGE 0x11 0x12 src/commonlib/include/commonlib/console/post_codes.h:60: #define POST_RAMSTAGE_IS_PREPARED 0x12 0x13 src/arch/x86/c_start.S:50: post_code(POST_ENTRY_C_START) /* post 13 */ 0x13 src/commonlib/include/commonlib/console/post_codes.h:67: #define POST_ENTRY_C_START 0x13 0x20 src/cpu/intel/car/core2/cache_as_ram.S:18: post_code(0x20) 0x20 src/cpu/intel/car/non-evict/cache_as_ram.S:23: post_code(0x20) 0x20 src/cpu/intel/car/p3/cache_as_ram.S:16: post_code(0x20) 0x20 src/cpu/intel/car/p4-netburst/cache_as_ram.S:22: post_code(0x20) 0x20 src/cpu/qemu-x86/cache_as_ram_bootblock.S:18: post_code(0x20) 0x20 src/drivers/intel/fsp1_1/cache_as_ram.S:37: post_code(0x20) 0x20 src/soc/intel/common/block/cpu/car/cache_as_ram.S:81: post_code(0x20) 0x20 src/soc/intel/quark/romstage/fsp_params.c:20: post_code(0x20); 0x21 src/cpu/intel/car/non-evict/cache_as_ram.S:36: post_code(0x21) 0x21 src/cpu/intel/car/p3/cache_as_ram.S:44: post_code(0x21) 0x21 src/cpu/intel/car/p4-netburst/cache_as_ram.S:55: post_code(0x21) 0x21 src/cpu/qemu-x86/cache_as_ram_bootblock.S:32: post_code(0x21) 0x21 src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S:22: post_code(0x21) 0x21 src/soc/intel/common/block/cpu/car/cache_as_ram.S:101: post_code(0x21) 0x22 src/cpu/intel/car/core2/cache_as_ram.S:31: post_code(0x22) 0x22 src/cpu/intel/car/core2/cache_as_ram.S:60: post_code(0x22) 0x22 src/cpu/intel/car/non-evict/cache_as_ram.S:43: post_code(0x22) 0x22 src/cpu/intel/car/p3/cache_as_ram.S:52: post_code(0x22) 0x22 src/cpu/intel/car/p4-netburst/cache_as_ram.S:63: post_code(0x22) 0x22 src/soc/intel/common/block/cpu/car/cache_as_ram.S:114: post_code(0x22) 0x23 src/cpu/intel/car/core2/cache_as_ram.S:85: post_code(0x23) 0x23 src/cpu/intel/car/non-evict/cache_as_ram.S:89: post_code(0x23) 0x23 src/cpu/intel/car/p4-netburst/cache_as_ram.S:107: post_code(0x23) 0x23 src/soc/intel/common/block/cpu/car/cache_as_ram.S:132: post_code(0x23) 0x24 src/cpu/intel/car/core2/cache_as_ram.S:93: post_code(0x24) 0x24 src/cpu/intel/car/non-evict/cache_as_ram.S:97: post_code(0x24) 0x24 src/cpu/intel/car/p4-netburst/cache_as_ram.S:121: post_code(0x24) 0x24 src/device/pci_device.c:1396: post_code(0x24); 0x24 src/soc/intel/common/block/cpu/car/cache_as_ram.S:160: post_code(0x24) 0x25 src/cpu/intel/car/core2/cache_as_ram.S:101: post_code(0x25) 0x25 src/cpu/intel/car/non-evict/cache_as_ram.S:118: post_code(0x25) 0x25 src/cpu/intel/car/p4-netburst/cache_as_ram.S:156: post_code(0x25) 0x25 src/device/pci_device.c:1437: post_code(0x25); 0x25 src/soc/intel/common/block/cpu/car/cache_as_ram.S:219: post_code(0x25) 0x26 src/cpu/intel/car/core2/cache_as_ram.S:129: post_code(0x26) 0x26 src/cpu/intel/car/non-evict/cache_as_ram.S:189: post_code(0x26) 0x26 src/cpu/intel/car/p4-netburst/cache_as_ram.S:171: post_code(0x26) 0x26 src/soc/intel/common/block/cpu/car/cache_as_ram.S:331: post_code(0x26) 0x26 src/soc/intel/common/block/cpu/car/cache_as_ram.S:422: post_code(0x26) 0x26 src/soc/intel/common/block/cpu/car/cache_as_ram.S:453: post_code(0x26) 0x27 src/cpu/intel/car/p4-netburst/cache_as_ram.S:187: post_code(0x27) 0x27 src/soc/intel/common/block/cpu/car/cache_as_ram.S:335: post_code(0x27) 0x27 src/soc/intel/common/block/cpu/car/cache_as_ram.S:426: post_code(0x27) 0x27 src/soc/intel/common/block/cpu/car/cache_as_ram.S:640: post_code(0x27) 0x28 src/cpu/intel/car/core2/cache_as_ram.S:148: post_code(0x28) 0x28 src/cpu/intel/car/non-evict/cache_as_ram.S:200: post_code(0x28) 0x28 src/cpu/intel/car/p4-netburst/cache_as_ram.S:194: post_code(0x28) 0x28 src/soc/intel/common/block/cpu/car/cache_as_ram.S:343: post_code(0x28) 0x28 src/soc/intel/common/block/cpu/car/cache_as_ram.S:441: post_code(0x28) 0x28 src/soc/intel/common/block/cpu/car/cache_as_ram.S:651: post_code(0x28) 0x29 src/cpu/intel/car/core2/cache_as_ram.S:182: post_code(0x29) 0x29 src/cpu/intel/car/non-evict/cache_as_ram.S:235: post_code(0x29) 0x29 src/cpu/intel/car/p3/cache_as_ram.S:158: post_code(0x29) 0x29 src/cpu/intel/car/p4-netburst/cache_as_ram.S:202: post_code(0x29) 0x29 src/cpu/qemu-x86/cache_as_ram_bootblock.S:106: post_code(0x29) 0x29 src/soc/intel/common/block/cpu/car/cache_as_ram.S:271: post_code(0x29) 0x2a src/cpu/intel/car/p3/cache_as_ram.S:70: post_code(0x2a) 0x2a src/cpu/intel/car/p4-netburst/cache_as_ram.S:213: post_code(0x2a) 0x2a src/drivers/intel/fsp1_1/cache_as_ram.S:184: post_code(0x2a) 0x2a src/soc/intel/common/block/cpu/car/cache_as_ram.S:298: post_code(0x2a) 0x2b src/cpu/intel/car/p3/cache_as_ram.S:86: post_code(0x2b) 0x2b src/cpu/intel/car/p4-netburst/cache_as_ram.S:229: post_code(0x2b) 0x2b src/soc/intel/quark/bootblock/esram_init.S:482: post_code(0x2b) 0x2c src/cpu/intel/car/p3/cache_as_ram.S:94: post_code(0x2c) 0x2c src/cpu/intel/car/p4-netburst/cache_as_ram.S:272: post_code(0x2c) 0x2d src/cpu/intel/car/p3/cache_as_ram.S:116: post_code(0x2d) 0x2d src/cpu/intel/car/p4-netburst/cache_as_ram.S:299: post_code(0x2d) 0x2e src/cpu/intel/car/p3/cache_as_ram.S:135: post_code(0x2e) 0x2e src/cpu/intel/car/p4-netburst/cache_as_ram.S:339: post_code(0x2e) 0x2f src/cpu/intel/car/p4-netburst/cache_as_ram.S:382: post_code(0x2f) 0x30 src/cpu/intel/car/non-evict/exit_car.S:15: post_code(0x30) 0x30 src/cpu/intel/car/p4-netburst/exit_car.S:13: post_code(0x30) 0x30 src/drivers/intel/fsp1_1/romstage.c:101: post_code(0x30); 0x30 src/mainboard/amd/thatcher/bootblock.c:13: post_code(0x30); 0x30 src/mainboard/asus/a88xm-e/romstage.c:10: post_code(0x30); 0x30 src/mainboard/asus/f2a85-m/romstage.c:13: post_code(0x30); 0x30 src/mainboard/msi/ms7721/romstage.c:8: post_code(0x30); 0x30 src/northbridge/intel/pineview/romstage.c:37: post_code(0x30); 0x30 src/soc/intel/broadwell/romstage.c:24: post_code(0x30); 0x31 src/cpu/intel/car/non-evict/exit_car.S:22: post_code(0x31) 0x31 src/cpu/intel/car/p4-netburst/exit_car.S:20: post_code(0x31) 0x31 src/drivers/intel/fsp1_1/romstage.c:123: post_code(0x31); 0x31 src/mainboard/amd/thatcher/bootblock.c:14: post_code(0x31); 0x31 src/northbridge/intel/pineview/romstage.c:58: post_code(0x31); 0x32 src/cpu/intel/car/non-evict/exit_car.S:38: post_code(0x32) 0x32 src/cpu/intel/car/p4-netburst/exit_car.S:28: post_code(0x32) 0x32 src/drivers/intel/fsp1_1/romstage.c:27: post_code(0x32); 0x32 src/soc/intel/broadwell/raminit.c:189: post_code(0x32); 0x33 src/drivers/intel/fsp1_1/romstage.c:35: post_code(0x33); 0x34 src/commonlib/include/commonlib/console/post_codes.h:75: #define POST_MEM_PREINIT_PREP_START 0x34 0x34 src/drivers/intel/fsp1_1/raminit.c:53: post_code(POST_MEM_PREINIT_PREP_START); 0x34 src/drivers/intel/fsp2_0/memory_init.c:235: post_code(POST_MEM_PREINIT_PREP_START); 0x36 src/commonlib/include/commonlib/console/post_codes.h:83: #define POST_MEM_PREINIT_PREP_END 0x36 0x36 src/drivers/intel/fsp1_1/raminit.c:91: post_code(POST_MEM_PREINIT_PREP_END); 0x36 src/drivers/intel/fsp2_0/memory_init.c:290: post_code(POST_MEM_PREINIT_PREP_END); 0x37 src/drivers/intel/fsp1_1/raminit.c:113: post_code(0x37); 0x37 src/soc/amd/stoneyridge/romstage.c:36: post_code(0x37); 0x38 src/drivers/intel/fsp1_1/romstage.c:129: post_code(0x38); 0x38 src/northbridge/intel/sandybridge/romstage.c:72: post_code(0x38); 0x38 src/soc/amd/stoneyridge/romstage.c:39: post_code(0x38); 0x39 src/commonlib/include/commonlib/console/post_codes.h:90: #define POST_CONSOLE_READY 0x39 0x39 src/lib/hardwaremain.c:450: post_code(POST_CONSOLE_READY); 0x39 src/northbridge/intel/sandybridge/romstage.c:76: post_code(0x39); 0x3a src/northbridge/intel/haswell/romstage.c:38: post_code(0x3a); 0x3a src/northbridge/intel/sandybridge/raminit.c:479: post_code(0x3a); 0x3a src/northbridge/intel/sandybridge/raminit_mrc.c:340: post_code(0x3a); 0x3b src/northbridge/intel/haswell/haswell_mrc/raminit.c:416: post_code(0x3b); 0x3b src/northbridge/intel/sandybridge/romstage.c:85: post_code(0x3b); 0x3c src/northbridge/intel/sandybridge/romstage.c:88: post_code(0x3c); 0x3d src/northbridge/intel/sandybridge/romstage.c:94: post_code(0x3d); 0x3f src/northbridge/intel/haswell/romstage.c:65: post_code(0x3f); 0x3f src/northbridge/intel/sandybridge/romstage.c:98: post_code(0x3f); 0x40 src/commonlib/include/commonlib/console/post_codes.h:98: #define POST_CONSOLE_BOOT_MSG 0x40 0x40 src/soc/amd/cezanne/romstage.c:17: post_code(0x40); 0x40 src/soc/amd/picasso/romstage.c:18: post_code(0x40); 0x40 src/soc/amd/sabrina/romstage.c:19: post_code(0x40); 0x40 src/soc/amd/stoneyridge/romstage.c:72: post_code(0x40); 0x41 src/soc/amd/cezanne/romstage.c:21: post_code(0x41); 0x41 src/soc/amd/sabrina/romstage.c:23: post_code(0x41); 0x41 src/soc/amd/stoneyridge/romstage.c:75: post_code(0x41); 0x42 src/soc/amd/picasso/romstage.c:22: post_code(0x42); 0x42 src/soc/amd/stoneyridge/romstage.c:111: post_code(0x42); 0x43 src/soc/amd/picasso/romstage.c:27: post_code(0x43); 0x43 src/soc/amd/stoneyridge/romstage.c:114: post_code(0x43); 0x44 src/soc/amd/picasso/romstage.c:32: post_code(0x44); 0x44 src/soc/amd/stoneyridge/romstage.c:123: post_code(0x44); 0x45 src/soc/amd/stoneyridge/romstage.c:142: post_code(0x45); 0x46 src/soc/amd/stoneyridge/chip.c:152: post_code(0x46); 0x46 src/soc/amd/stoneyridge/chip.c:160: post_code(0x46); 0x47 src/soc/amd/stoneyridge/chip.c:156: post_code(0x47); 0x4F src/drivers/intel/fsp1_1/fsp_util.c:126: post_code(0x4F); 0x50 src/soc/amd/picasso/romstage.c:35: post_code(0x50); /* Should never see this post code. */ 0x50 src/soc/amd/stoneyridge/romstage.c:145: post_code(0x50); /* Should never see this post code. */ 0x55 src/device/pci_device.c:1489: post_code(0x55); 0x60 src/commonlib/include/commonlib/console/post_codes.h:105: #define POST_ENABLING_CACHE 0x60 0x60 src/soc/amd/stoneyridge/romstage.c:105: post_code(0x60); 0x61 src/soc/amd/stoneyridge/romstage.c:108: post_code(0x61); 0x6e src/arch/x86/c_start.S:103: post_code(POST_PRE_HARDWAREMAIN) /* post 6e */ 0x6e src/commonlib/include/commonlib/console/post_codes.h:112: #define POST_PRE_HARDWAREMAIN 0x6e 0x6f src/commonlib/include/commonlib/console/post_codes.h:120: #define POST_ENTRY_HARDWAREMAIN 0x6f 0x6f src/lib/hardwaremain.c:461: post_code(POST_ENTRY_HARDWAREMAIN); 0x70 src/commonlib/include/commonlib/console/post_codes.h:127: #define POST_BS_PRE_DEVICE 0x70 0x71 src/commonlib/include/commonlib/console/post_codes.h:134: #define POST_BS_DEV_INIT_CHIPS 0x71 0x72 src/commonlib/include/commonlib/console/post_codes.h:141: #define POST_BS_DEV_ENUMERATE 0x72 0x73 src/commonlib/include/commonlib/console/post_codes.h:148: #define POST_BS_DEV_RESOURCES 0x73 0x74 src/commonlib/include/commonlib/console/post_codes.h:155: #define POST_BS_DEV_ENABLE 0x74 0x75 src/commonlib/include/commonlib/console/post_codes.h:162: #define POST_BS_DEV_INIT 0x75 0x75 src/device/device.c:546: post_code(POST_BS_DEV_INIT); 0x76 src/commonlib/include/commonlib/console/post_codes.h:169: #define POST_BS_POST_DEVICE 0x76 0x77 src/commonlib/include/commonlib/console/post_codes.h:176: #define POST_BS_OS_RESUME_CHECK 0x77 0x78 src/commonlib/include/commonlib/console/post_codes.h:183: #define POST_BS_OS_RESUME 0x78 0x79 src/commonlib/include/commonlib/console/post_codes.h:190: #define POST_BS_WRITE_TABLES 0x79 0x7a src/commonlib/include/commonlib/console/post_codes.h:197: #define POST_BS_PAYLOAD_LOAD 0x7a 0x7b src/commonlib/include/commonlib/console/post_codes.h:204: #define POST_BS_PAYLOAD_BOOT 0x7b 0x88 src/commonlib/include/commonlib/console/post_codes.h:211: #define POST_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE 0x88 0x88 src/drivers/intel/fsp2_0/notify.c:40: .post_code_before = POST_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE, 0x89 src/commonlib/include/commonlib/console/post_codes.h:218: #define POST_FSP_NOTIFY_AFTER_END_OF_FIRMWARE 0x89 0x89 src/drivers/intel/fsp2_0/notify.c:41: .post_code_after = POST_FSP_NOTIFY_AFTER_END_OF_FIRMWARE, 0x90 src/commonlib/include/commonlib/console/post_codes.h:225: #define POST_FSP_TEMP_RAM_INIT 0x90 0x90 src/drivers/intel/fsp1_1/cache_as_ram.S:98: post_code(POST_FSP_TEMP_RAM_INIT) 0x90 src/soc/amd/stoneyridge/bootblock.c:109: post_code(0x90); 0x91 src/commonlib/include/commonlib/console/post_codes.h:232: #define POST_FSP_TEMP_RAM_EXIT 0x91 0x92 src/commonlib/include/commonlib/console/post_codes.h:239: #define POST_FSP_MEMORY_INIT 0x92 0x92 src/drivers/intel/fsp1_1/raminit.c:110: post_code(POST_FSP_MEMORY_INIT); 0x92 src/drivers/intel/fsp2_0/memory_init.c:296: post_code(POST_FSP_MEMORY_INIT); 0x93 src/commonlib/include/commonlib/console/post_codes.h:246: #define POST_FSP_SILICON_INIT 0x93 0x93 src/cpu/x86/mtrr/mtrr.c:862: post_code(0x93); 0x93 src/drivers/intel/fsp1_1/ramstage.c:98: post_code(POST_FSP_SILICON_INIT); 0x93 src/drivers/intel/fsp2_0/silicon_init.c:134: post_code(POST_FSP_SILICON_INIT); 0x94 src/commonlib/include/commonlib/console/post_codes.h:253: #define POST_FSP_NOTIFY_BEFORE_ENUMERATE 0x94 0x94 src/drivers/intel/fsp1_1/fsp_util.c:141: post_code(POST_FSP_NOTIFY_BEFORE_ENUMERATE); 0x94 src/drivers/intel/fsp2_0/notify.c:24: .post_code_before = POST_FSP_NOTIFY_BEFORE_ENUMERATE, 0x95 src/commonlib/include/commonlib/console/post_codes.h:260: #define POST_FSP_NOTIFY_BEFORE_FINALIZE 0x95 0x95 src/drivers/intel/fsp1_1/fsp_util.c:138: post_code(POST_FSP_NOTIFY_BEFORE_FINALIZE); 0x95 src/drivers/intel/fsp2_0/notify.c:32: .post_code_before = POST_FSP_NOTIFY_BEFORE_FINALIZE, 0x96 src/commonlib/include/commonlib/console/post_codes.h:267: #define POST_OS_ENTER_PTS 0x96 0x96 src/soc/intel/common/acpi/platform.asl:25: DBG0 = POST_OS_ENTER_PTS 0x97 src/commonlib/include/commonlib/console/post_codes.h:274: #define POST_OS_ENTER_WAKE 0x97 0x97 src/soc/intel/common/acpi/platform.asl:45: DBG0 = POST_OS_ENTER_WAKE 0x98 src/commonlib/include/commonlib/console/post_codes.h:281: #define POST_FSP_MEMORY_EXIT 0x98 0x98 src/drivers/intel/fsp2_0/memory_init.c:305: post_code(POST_FSP_MEMORY_EXIT); 0x99 src/commonlib/include/commonlib/console/post_codes.h:288: #define POST_FSP_SILICON_EXIT 0x99 0x99 src/drivers/intel/fsp2_0/silicon_init.c:144: post_code(POST_FSP_SILICON_EXIT); 0x9a src/arch/x86/tables.c:20: post_code(0x9a); 0x9b src/arch/x86/tables.c:52: post_code(0x9b); 0x9c src/arch/x86/tables.c:81: post_code(0x9c); 0xa0 src/commonlib/include/commonlib/console/post_codes.h:295: #define POST_FSP_MULTI_PHASE_SI_INIT_ENTRY 0xa0 0xa0 src/drivers/amd/agesa/cache_as_ram.S:33: post_code(0xa0) 0xa0 src/drivers/intel/fsp2_0/silicon_init.c:171: post_code(POST_FSP_MULTI_PHASE_SI_INIT_ENTRY); 0xa0 src/soc/amd/common/block/cpu/car/cache_as_ram.S:30: post_code(0xa0) 0xa0 src/soc/amd/common/block/cpu/noncar/pre_c.S:26: post_code(0xa0) 0xa1 src/commonlib/include/commonlib/console/post_codes.h:302: #define POST_FSP_MULTI_PHASE_SI_INIT_EXIT 0xa1 0xa1 src/drivers/intel/fsp2_0/silicon_init.c:196: post_code(POST_FSP_MULTI_PHASE_SI_INIT_EXIT); 0xa2 src/commonlib/include/commonlib/console/post_codes.h:309: #define POST_FSP_NOTIFY_AFTER_ENUMERATE 0xa2 0xa2 src/drivers/amd/agesa/cache_as_ram.S:59: post_code(0xa2) 0xa2 src/drivers/intel/fsp2_0/notify.c:25: .post_code_after = POST_FSP_NOTIFY_AFTER_ENUMERATE, 0xa2 src/soc/amd/common/block/cpu/car/cache_as_ram.S:44: post_code(0xa2) 0xa2 src/soc/amd/common/block/cpu/noncar/pre_c.S:48: post_code(0xa2) 0xa3 src/commonlib/include/commonlib/console/post_codes.h:316: #define POST_FSP_NOTIFY_AFTER_FINALIZE 0xa3 0xa3 src/drivers/intel/fsp2_0/notify.c:33: .post_code_after = POST_FSP_NOTIFY_AFTER_FINALIZE, 0xb0 src/soc/amd/common/block/cpu/noncar/pre_c.S:9: post_code(0xb0) 0xc0 src/soc/amd/common/psp_verstage/include/psp_verstage.h:28: #define POSTCODE_DEFAULT_BUFFER_SIZE_NOTICE 0xC0 0xc1 src/soc/amd/common/psp_verstage/include/psp_verstage.h:29: #define POSTCODE_WORKBUF_RESIZE_WARNING 0xC1 0xc2 src/soc/amd/common/psp_verstage/include/psp_verstage.h:30: #define POSTCODE_WORKBUF_SAVE_ERROR 0xC2 0xc2 src/soc/amd/common/psp_verstage/psp_verstage.c:163: return POSTCODE_WORKBUF_SAVE_ERROR; 0xc3 src/soc/amd/common/psp_verstage/include/psp_verstage.h:31: #define POSTCODE_WORKBUF_BUFFER_SIZE_ERROR 0xC3 0xc4 src/soc/amd/common/psp_verstage/include/psp_verstage.h:32: #define POSTCODE_ROMSIG_MISMATCH_ERROR 0xC4 0xc4 src/soc/amd/common/psp_verstage/psp_verstage.c:100: return POSTCODE_ROMSIG_MISMATCH_ERROR; 0xc5 src/soc/amd/common/psp_verstage/include/psp_verstage.h:33: #define POSTCODE_PSP_COOKIE_MISMATCH_ERROR 0xC5 0xc5 src/soc/amd/common/psp_verstage/psp_verstage.c:111: return POSTCODE_PSP_COOKIE_MISMATCH_ERROR; 0xc6 src/soc/amd/common/psp_verstage/include/psp_verstage.h:34: #define POSTCODE_BDT1_COOKIE_MISMATCH_ERROR 0xC6 0xc6 src/soc/amd/common/psp_verstage/psp_verstage.c:115: return POSTCODE_BDT1_COOKIE_MISMATCH_ERROR; 0xc7 src/soc/amd/common/psp_verstage/include/psp_verstage.h:35: #define POSTCODE_UPDATE_PSP_BIOS_DIR_ERROR 0xC7 0xc7 src/soc/amd/common/psp_verstage/psp_verstage.c:126: return POSTCODE_UPDATE_PSP_BIOS_DIR_ERROR; 0xc8 src/soc/amd/common/psp_verstage/include/psp_verstage.h:36: #define POSTCODE_FMAP_REGION_MISSING 0xC8 0xc9 src/soc/amd/common/psp_verstage/include/psp_verstage.h:37: #define POSTCODE_AMD_FW_MISSING 0xC9 0xc9 src/soc/amd/common/psp_verstage/psp_verstage.c:95: return POSTCODE_AMD_FW_MISSING; 0xca src/soc/amd/common/psp_verstage/include/psp_verstage.h:38: #define POSTCODE_CMOS_RECOVERY 0xCA 0xca src/soc/amd/common/psp_verstage/psp_verstage.c:62: return POSTCODE_CMOS_RECOVERY; 0xcb src/soc/amd/common/psp_verstage/include/psp_verstage.h:39: #define POSTCODE_EARLY_INIT_ERROR 0xCB 0xcb src/soc/amd/common/psp_verstage/psp_verstage.c:231: svc_write_postcode(POSTCODE_EARLY_INIT_ERROR); 0xcc src/soc/amd/common/psp_verstage/include/psp_verstage.h:40: #define POSTCODE_INIT_TPM_FAILED 0xCC 0xcc src/soc/amd/common/psp_verstage/psp_verstage.c:189: reboot_into_recovery(vboot_get_context(), POSTCODE_INIT_TPM_FAILED); 0xcc src/soc/amd/common/psp_verstage/psp_verstage.c:195: reboot_into_recovery(vboot_get_context(), POSTCODE_INIT_TPM_FAILED); 0xe0 src/arch/x86/postcar_loader.c:139: die_with_post_code(POST_INVALID_ROM, 0xe0 src/arch/x86/postcar_loader.c:144: die_with_post_code(POST_INVALID_ROM, 0xe0 src/commonlib/include/commonlib/console/post_codes.h:323: #define POST_INVALID_ROM 0xe0 0xe0 src/lib/prog_loaders.c:130: die_with_post_code(POST_INVALID_ROM, "Ramstage was not loaded!\n"); 0xe0 src/lib/prog_loaders.c:173: die_with_post_code(POST_INVALID_ROM, 0xe0 src/lib/prog_loaders.c:181: die_with_post_code(POST_INVALID_ROM, "Payload not loaded.\n"); 0xe0 src/lib/prog_loaders.c:45: die_with_post_code(POST_INVALID_ROM, 0xe0 src/security/vboot/vboot_logic.c:358: die_with_post_code(POST_INVALID_ROM, 0xe1 src/commonlib/include/commonlib/console/post_codes.h:330: #define POST_INVALID_CBFS 0xe1 0xe1 src/drivers/intel/fsp1_1/car.c:33: die_with_post_code(POST_INVALID_CBFS, "Unable to locate fsp.bin"); 0xe1 src/soc/intel/quark/romstage/fsp_params.c:78: die_with_post_code(POST_INVALID_CBFS, 0xe2 src/commonlib/include/commonlib/console/post_codes.h:338: #define POST_INVALID_VENDOR_BINARY 0xe2 0xe2 src/drivers/intel/fsp1_1/raminit.c:228: die_with_post_code(POST_INVALID_VENDOR_BINARY, 0xe2 src/drivers/intel/fsp1_1/raminit.c:235: die_with_post_code(POST_INVALID_VENDOR_BINARY, 0xe2 src/drivers/intel/fsp2_0/memory_init.c:271: die_with_post_code(POST_INVALID_VENDOR_BINARY, 0xe2 src/drivers/intel/fsp2_0/silicon_init.c:109: die_with_post_code(POST_INVALID_VENDOR_BINARY, 0xe2 src/drivers/intel/fsp2_0/util.c:185: die_with_post_code(POST_INVALID_VENDOR_BINARY, 0xe2 src/northbridge/intel/haswell/haswell_mrc/raminit.c:160: die_with_post_code(POST_INVALID_VENDOR_BINARY, 0xe2 src/northbridge/intel/sandybridge/raminit_mrc.c:171: die_with_post_code(POST_INVALID_VENDOR_BINARY, 0xe3 src/commonlib/include/commonlib/console/post_codes.h:346: #define POST_RAM_FAILURE 0xe3 0xe3 src/drivers/intel/fsp1_1/raminit.c:118: die_with_post_code(POST_RAM_FAILURE, 0xe3 src/drivers/intel/fsp1_1/raminit.c:175: die_with_post_code(POST_RAM_FAILURE, 0xe3 src/drivers/intel/fsp2_0/memory_init.c:311: die_with_post_code(POST_RAM_FAILURE, 0xe3 src/ec/google/wilco/commands.c:182: { .post_code = POST_RAM_FAILURE, .ec_err = DLED_MEMORY, }, 0xe4 src/commonlib/include/commonlib/console/post_codes.h:353: #define POST_HW_INIT_FAILURE 0xe4 0xe4 src/drivers/intel/fsp2_0/silicon_init.c:55: postcode = POST_HW_INIT_FAILURE; /* else generic */ 0xe4 src/soc/amd/cezanne/cpu.c:58: die_with_post_code(POST_HW_INIT_FAILURE, 0xe4 src/soc/amd/picasso/cpu.c:62: die_with_post_code(POST_HW_INIT_FAILURE, 0xe4 src/soc/amd/sabrina/cpu.c:60: die_with_post_code(POST_HW_INIT_FAILURE, 0xe4 src/soc/amd/stoneyridge/cpu.c:55: die_with_post_code(POST_HW_INIT_FAILURE, 0xe4 src/soc/intel/cannonlake/bootblock/pch.c:94: die_with_post_code(POST_HW_INIT_FAILURE, 0xe4 src/soc/intel/common/block/graphics/graphics.c:120: die_with_post_code(POST_HW_INIT_FAILURE, 0xe4 src/soc/intel/common/block/graphics/graphics.c:143: die_with_post_code(POST_HW_INIT_FAILURE, 0xe4 src/soc/intel/common/block/p2sb/p2sblib.c:53: die_with_post_code(POST_HW_INIT_FAILURE, 0xe4 src/soc/intel/common/block/p2sb/p2sblib.c:62: die_with_post_code(POST_HW_INIT_FAILURE, 0xe4 src/soc/intel/common/block/pmc/pmc.c:65: die_with_post_code(POST_HW_INIT_FAILURE, 0xe4 src/soc/intel/quark/i2c.c:29: die_with_post_code(POST_HW_INIT_FAILURE, 0xe5 src/commonlib/include/commonlib/console/post_codes.h:360: #define POST_VIDEO_FAILURE 0xe5 0xe5 src/drivers/intel/fsp2_0/silicon_init.c:53: postcode = POST_VIDEO_FAILURE; 0xe5 src/ec/google/wilco/commands.c:183: { .post_code = POST_VIDEO_FAILURE, .ec_err = DLED_PANEL, }, 0xea src/lib/ramtest.c:111: post_code(0xea); 0xea src/lib/ramtest.c:201: post_code(0xea); 0xed src/commonlib/include/commonlib/console/post_codes.h:367: #define POST_TPM_FAILURE 0xed 0xed src/security/tpm/tspi/tspi.c:84: post_code(POST_TPM_FAILURE); 0xee src/arch/x86/c_start.S:118: post_code(POST_DEAD_CODE) /* post ee */ 0xee src/commonlib/include/commonlib/console/post_codes.h:376: #define POST_DEAD_CODE 0xee 0xee src/cpu/intel/car/core2/cache_as_ram.S:186: post_code(POST_DEAD_CODE) 0xee src/cpu/intel/car/non-evict/cache_as_ram.S:239: post_code(POST_DEAD_CODE) 0xee src/cpu/intel/car/p3/cache_as_ram.S:162: post_code(POST_DEAD_CODE) 0xee src/cpu/intel/car/p4-netburst/cache_as_ram.S:386: post_code(POST_DEAD_CODE) 0xee src/cpu/qemu-x86/cache_as_ram_bootblock.S:110: post_code(POST_DEAD_CODE) 0xee src/drivers/amd/agesa/cache_as_ram.S:66: post_code(POST_DEAD_CODE) 0xee src/drivers/intel/fsp1_1/cache_as_ram.S:227: post_code(POST_DEAD_CODE) 0xee src/soc/amd/common/block/cpu/car/cache_as_ram.S:50: post_code(POST_DEAD_CODE) 0xee src/soc/amd/common/block/cpu/noncar/pre_c.S:54: post_code(POST_DEAD_CODE) 0xee src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S:101: post_code(POST_DEAD_CODE) 0xee src/soc/intel/common/block/cpu/car/cache_as_ram.S:304: post_code(POST_DEAD_CODE) 0xef src/commonlib/include/commonlib/console/post_codes.h:384: #define POST_RESUME_FAILURE 0xef 0xef src/drivers/intel/fsp1_1/romstage.c:59: post_code(POST_RESUME_FAILURE); 0xef src/northbridge/intel/haswell/haswell_mrc/raminit.c:128: post_code(POST_RESUME_FAILURE); 0xef src/soc/intel/baytrail/romstage/raminit.c:149: post_code(POST_RESUME_FAILURE); 0xef src/soc/intel/broadwell/raminit.c:105: post_code(POST_RESUME_FAILURE); 0xf0 src/mainboard/google/auron/ec.c:20: post_code(0xf0); 0xf0 src/mainboard/google/cyan/ec.c:18: post_code(0xf0); 0xf0 src/mainboard/google/link/ec.c:18: post_code(0xf0); 0xf0 src/mainboard/google/rambi/ec.c:20: post_code(0xf0); 0xf0 src/mainboard/google/slippy/ec.c:20: post_code(0xf0); 0xf0 src/mainboard/intel/strago/ec.c:18: post_code(0xf0); 0xf0 src/soc/amd/common/psp_verstage/include/psp_verstage.h:43: #define POSTCODE_UNMAP_SPI_ROM 0xF0 0xf0 src/soc/amd/common/psp_verstage/psp_verstage.c:315: post_code(POSTCODE_UNMAP_SPI_ROM); 0xf1 src/mainboard/google/auron/ec.c:29: post_code(0xf1); 0xf1 src/mainboard/google/cyan/ec.c:22: post_code(0xf1); 0xf1 src/mainboard/google/link/ec.c:22: post_code(0xf1); 0xf1 src/mainboard/google/rambi/ec.c:24: post_code(0xf1); 0xf1 src/mainboard/google/slippy/ec.c:29: post_code(0xf1); 0xf1 src/mainboard/intel/strago/ec.c:22: post_code(0xf1); 0xf1 src/soc/amd/common/psp_verstage/include/psp_verstage.h:44: #define POSTCODE_UNMAP_FCH_DEVICES 0xF1 0xf1 src/soc/amd/common/psp_verstage/psp_verstage.c:265: post_code(POSTCODE_UNMAP_FCH_DEVICES); 0xf1 src/soc/amd/common/psp_verstage/psp_verstage.c:322: post_code(POSTCODE_UNMAP_FCH_DEVICES); 0xf2 src/soc/amd/common/psp_verstage/include/psp_verstage.h:45: #define POSTCODE_LEAVING_VERSTAGE 0xF2 0xf2 src/soc/amd/common/psp_verstage/psp_verstage.c:268: post_code(POSTCODE_LEAVING_VERSTAGE); 0xf2 src/soc/amd/common/psp_verstage/psp_verstage.c:325: post_code(POSTCODE_LEAVING_VERSTAGE); 0xf3 src/commonlib/include/commonlib/console/post_codes.h:392: #define POST_JUMPING_TO_PAYLOAD 0xf3 0xf8 src/commonlib/include/commonlib/console/post_codes.h:400: #define POST_ENTER_ELF_BOOT 0xf8 0xf8 src/drivers/pc80/rtc/post.c:65: case POST_ENTER_ELF_BOOT: 0xf8 src/lib/prog_loaders.c:194: post_code(POST_ENTER_ELF_BOOT); 0xfd src/arch/x86/acpi_s3.c:30: post_code(POST_OS_RESUME); 0xfd src/commonlib/include/commonlib/console/post_codes.h:407: #define POST_OS_RESUME 0xfd 0xfd src/drivers/pc80/rtc/post.c:64: case POST_OS_RESUME: 0xfe src/commonlib/include/commonlib/console/post_codes.h:414: #define POST_OS_BOOT 0xfe 0xfe src/drivers/pc80/rtc/post.c:63: case POST_OS_BOOT: 0xfe src/soc/amd/common/block/cpu/smm/finalize.c:52: post_code(POST_OS_BOOT); 0xfe src/soc/intel/alderlake/finalize.c:103: post_code(POST_OS_BOOT); 0xfe src/soc/intel/broadwell/finalize.c:61: post_code(POST_OS_BOOT); 0xfe src/soc/intel/cannonlake/finalize.c:104: post_code(POST_OS_BOOT); 0xfe src/soc/intel/elkhartlake/finalize.c:49: post_code(POST_OS_BOOT); 0xfe src/soc/intel/icelake/finalize.c:70: post_code(POST_OS_BOOT); 0xfe src/soc/intel/jasperlake/finalize.c:84: post_code(POST_OS_BOOT); 0xfe src/soc/intel/skylake/finalize.c:112: post_code(POST_OS_BOOT); 0xfe src/soc/intel/tigerlake/finalize.c:72: post_code(POST_OS_BOOT); 0xfe src/soc/intel/xeon_sp/finalize.c:46: post_code(POST_OS_BOOT); 0xfe src/southbridge/intel/common/finalize.c:53: post_code(POST_OS_BOOT); 0xfe src/southbridge/intel/i82801gx/lpc.c:448: outb(POST_OS_BOOT, 0x80); 0xff src/commonlib/include/commonlib/console/post_codes.h:431: #define POST_DIE 0xff