Index: coreboot/src/southbridge/nvidia/ck804/ck804_early_setup_car.c
===================================================================
--- coreboot.orig/src/southbridge/nvidia/ck804/ck804_early_setup_car.c	2010-07-06 14:11:19.000000000 -0600
+++ coreboot/src/southbridge/nvidia/ck804/ck804_early_setup_car.c	2010-07-06 14:24:00.000000000 -0600
@@ -33,10 +33,10 @@
 	outl(val, control);
 }
 
-#define ANACTRL_IO_BASE 0x3000
+#define ANACTRL_IO_BASE 0x8800
 #define ANACTRL_REG_POS 0x68
 
-#define SYSCTRL_IO_BASE 0x2000
+#define SYSCTRL_IO_BASE 0x8400
 #define SYSCTRL_REG_POS 0x64
 
 /*
@@ -333,7 +333,7 @@
 		id = pci_read_config32(dev, PCI_VENDOR_ID);
 		if (id == 0x005e10de) {
 			busn[ck804_num] = i * 0x40;
-			io_base[ck804_num] = i * 0x4000;
+			io_base[ck804_num] = i * 0x1000;
 			ck804_num++;
 		}
 	}
Index: coreboot/src/mainboard/tyan/s2895/resourcemap.c
===================================================================
--- coreboot.orig/src/mainboard/tyan/s2895/resourcemap.c	2010-07-06 14:10:49.000000000 -0600
+++ coreboot/src/mainboard/tyan/s2895/resourcemap.c	2010-07-06 14:13:22.000000000 -0600
@@ -181,7 +181,7 @@
 	 *	   This field defines the end of PCI I/O region n
 	 * [31:25] Reserved
 	 */
-	PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000,
+	PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00008000,
 	PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x01fff001, // need to talk to ANALOG of second CK804 to release PCI E reset
 	PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
 	PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -212,7 +212,7 @@
 	 * [31:25] Reserved
 	 */
 	PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
-	PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00008033,
+	PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00009033,
 	PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
 	PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,