AreYouLoco, I am really glad to see there is someone else who is interested in this. If necessary, I will provide the coreboot config in a few hours, but it was nothing special.
It was built from master and I have simply selected mainboard vendor/model, checked Use CMOS for configuration values and increased Size of CBFS up to 0x300000.
I believe that src/mainboard/lenovo/t420/devicetree.cb (around line 85) has a statement related to that controller, but I will have to take a closer look at the coreboot source-code.
device pci 1c.4 on
chip drivers/ricoh/rce822
register "sdwppol" = "1"
register "disable_mask" = "0x87"
device pci 00.0 on end
end
end # PCIe Port #5 (Ricoh SD & FW)