Add support for ASUS K8X-X SE motherboard.

The good:
SeaBIOS can start, run option roms, and boot off DVD, IDE, or CBFS.
IRQ tables are fairly refined.
MP-Table is complete and reflects actual hardware setup.

The bad:
ACPI tables are incomplete and inaccurate.
IRQs do not work, neither as VirtualWire, nor through the APIC.
Linux cannot complete booting.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

Index: src/mainboard/asus/Kconfig
===================================================================
--- src/mainboard/asus/Kconfig	(revision 6369)
+++ src/mainboard/asus/Kconfig	(working copy)
@@ -27,6 +27,8 @@
 	bool "A8V-E SE"
 config BOARD_ASUS_A8V_E_DELUXE
 	bool "A8V-E Deluxe"
+config BOARD_ASUS_K8V_X_SE
+	bool "K8V-X SE"
+	depends on EXPERT
+	help
+	  This board was never finished due to time constraints.
+	  IRQs only work partially. SeaBIOS can start an OS from
+	  an IDE drive, but linux will get stuck while booting.
+	  YOU HAVE BEEN WARNED!!!
 config BOARD_ASUS_M2N_E
 	bool "M2N-E"
 config BOARD_ASUS_M2V
@@ -59,6 +61,7 @@
 source "src/mainboard/asus/a8n_e/Kconfig"
 source "src/mainboard/asus/a8v-e_se/Kconfig"
 source "src/mainboard/asus/a8v-e_deluxe/Kconfig"
+source "src/mainboard/asus/k8v-x_se/Kconfig"
 source "src/mainboard/asus/m2n-e/Kconfig"
 source "src/mainboard/asus/m2v/Kconfig"
 source "src/mainboard/asus/m2v-mx_se/Kconfig"
Index: src/mainboard/asus/k8v-x_se/Kconfig
===================================================================
--- src/mainboard/asus/k8v-x_se/Kconfig	(revision 0)
+++ src/mainboard/asus/k8v-x_se/Kconfig	(revision 0)
@@ -0,0 +1,81 @@
+if BOARD_ASUS_K8V_X_SE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_X86
+	select CPU_AMD_SOCKET_754
+	select NORTHBRIDGE_AMD_AMDK8
+	select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
+	select SOUTHBRIDGE_VIA_VT8237R
+	select SOUTHBRIDGE_VIA_K8T800
+	select SUPERIO_WINBOND_W83627EHG
+	select CACHE_AS_RAM
+	select HAVE_OPTION_TABLE
+	select HAVE_PIRQ_TABLE
+	select HAVE_ACPI_TABLES
+	select HAVE_MP_TABLE
+	select BOARD_ROMSIZE_KB_512
+	select RAMINIT_SYSINFO
+	select QRANK_DIMM_SUPPORT
+
+config MAINBOARD_DIR
+	string
+	default asus/k8v-x_se
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xcc000
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x4000
+
+config DCACHE_RAM_GLOBAL_VAR_SIZE
+	hex
+	default 0x1000
+
+config APIC_ID_OFFSET
+	hex
+	default 0x10
+
+config SB_HT_CHAIN_ON_BUS0
+	int
+	default 1
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "K8V-X SE"
+
+config HW_MEM_HOLE_SIZEK
+	hex
+	default 0
+
+config MAX_CPUS
+	int
+	default 2
+
+config MAX_PHYSICAL_CPUS
+	int
+	default 1
+
+config HEAP_SIZE
+	hex
+	default 0x40000
+
+config HT_CHAIN_END_UNITID_BASE
+	hex
+	default 0x20
+
+config HT_CHAIN_UNITID_BASE
+	hex
+	default 0x0
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+	hex
+	default 0x1043
+
+config IRQ_SLOT_COUNT
+	int
+	default 9
+
+endif # BOARD_ASUS_K8V_X_SE
Index: src/mainboard/asus/k8v-x_se/romstage.c
===================================================================
--- src/mainboard/asus/k8v-x_se/romstage.c	(revision 0)
+++ src/mainboard/asus/k8v-x_se/romstage.c	(revision 0)
@@ -0,0 +1,229 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 AMD
+ * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
+ * Copyright (C) 2006 MSI
+ * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+unsigned int get_sbdn(unsigned bus);
+
+#include <stdint.h>
+#include <string.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include <cpu/amd/model_fxx_rev.h>
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+#include "lib/delay.c"
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+#include "northbridge/amd/amdk8/early_ht.c"
+#include "superio/winbond/w83627ehg/early_serial.c"
+#include "southbridge/via/vt8237r/early_smbus.c"
+#include "northbridge/amd/amdk8/debug.c" /* After vt8237r_early_smbus.c! */
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "cpu/x86/bist.h"
+#include "northbridge/amd/amdk8/setup_resource_map.c"
+#include <spd.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
+#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V)
+#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
+
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+	return smbus_read_byte(device, address);
+}
+
+#include <reset.h>
+void soft_reset(void)
+{
+	uint8_t tmp;
+
+	set_bios_reset();
+	print_debug("soft reset \n");
+
+	/* PCI reset */
+	tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
+	tmp |= 0x01;
+	pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
+
+	while (1) {
+		/* daisy daisy ... */
+		hlt();
+	}
+}
+
+#include "southbridge/via/k8t890/early_car.c"
+#include "northbridge/amd/amdk8/amdk8.h"
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+#include "northbridge/amd/amdk8/raminit.c"
+#include "lib/generic_sdram.c"
+#include "cpu/amd/dualcore/dualcore.c"
+#include "cpu/amd/car/post_cache_as_ram.c"
+#include "cpu/amd/model_fxx/init_cpus.c"
+/* #include "cpu/amd/model_fxx/fidvid.c" */
+#include "northbridge/amd/amdk8/resourcemap.c"
+
+unsigned int get_sbdn(unsigned bus)
+{
+	device_t dev;
+
+	dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
+					PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
+	return (dev >> 15) & 0x1f;
+}
+
+static void sio_init(void)
+{
+	u8 reg;
+
+	pnp_enter_ext_func_mode(SERIAL_DEV);
+	/* We have 24MHz input. */
+	reg = pnp_read_config(SERIAL_DEV, 0x24);
+	pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40));
+	/* We have GPIO for KB/MS pin. */
+	reg = pnp_read_config(SERIAL_DEV, 0x2a);
+	pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1));
+	/* We have all RESTOUT and even some reserved bits, too. */
+	reg = pnp_read_config(SERIAL_DEV, 0x2c);
+	pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0));
+	pnp_exit_ext_func_mode(SERIAL_DEV);
+
+	pnp_enter_ext_func_mode(ACPI_DEV);
+	pnp_set_logical_device(ACPI_DEV);
+	/*
+	 * Set the delay rising time from PWROK_LP to PWROK_ST to
+	 * 300 - 600ms, and 0 to vice versa.
+	 */
+	reg = pnp_read_config(ACPI_DEV, 0xe6);
+	pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0));
+	/* 1 Use external suspend clock source 32.768KHz. Undocumented?? */
+	reg = pnp_read_config(ACPI_DEV, 0xe4);
+	pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10));
+	pnp_exit_ext_func_mode(ACPI_DEV);
+
+	/* TODO: Figure out which GPIO controls memory/chipset/CPU voltage, and set it here
+	 * Use A8V-E SE as inspiration
+	 */
+}
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+	static const uint16_t spd_addr[] = {
+		DIMM0, DIMM1, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+	};
+	unsigned bsp_apicid = 0;
+	int needs_reset = 0;
+	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+
+	sio_init();
+	w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	uart_init();
+	console_init();
+	enable_rom_decode();
+
+	print_info("now booting... fallback\n");
+
+	/* Is this a CPU only reset? Or is this a secondary CPU? */
+	if (!cpu_init_detectedx && boot_cpu()) {
+		/* Nothing special needs to be done to find bus 0. */
+		/* Allow the HT devices to be found. */
+		enumerate_ht_chain();
+	}
+
+	sio_init();
+	w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	uart_init();
+	console_init();
+	enable_rom_decode();
+
+	print_info("now booting... real_main\n");
+
+	if (bist == 0)
+		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
+
+	/* Halt if there was a built in self test failure. */
+	report_bist_failure(bist);
+
+	setup_default_resource_map();
+	setup_coherent_ht_domain();
+	wait_all_core0_started();
+
+	print_info("now booting... Core0 started\n");
+
+#if CONFIG_LOGICAL_CPUS==1
+	/* It is said that we should start core1 after all core0 launched. */
+	start_other_cores();
+	wait_all_other_cores_started(bsp_apicid);
+#endif
+	init_timer();
+	ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
+
+	needs_reset = optimize_link_coherent_ht();
+	needs_reset |= optimize_link_incoherent_ht(sysinfo);
+	needs_reset |= k8x8xx_early_setup_ht();
+
+	if (needs_reset) {
+		print_debug("ht reset -\n");
+		soft_reset();
+	}
+
+	/*
+	 * The following is another part from the A8V-E SE
+	 * It is commented out because manipulating the FIDVID MSRs (0xc0010041, and 0xc0010042)
+	 * will cause a General Protection Exception CPUs which do not support them.
+	 * See the AMD Fam 0Fh BIOS and Kernel Developer's Guide for more details
+	 * TODO: patch fidvid.c to check CPUID before using the FIDVID MSRs
+	 */
+	/* the HT settings needs to be OK, because link freq change may cause HT disconnect */
+	/*
+	enable_fid_change();
+	init_fidvid_bsp(bsp_apicid);
+	*/
+
+	/* Stop the APs so we can start them later in init. */
+	allow_all_aps_stop(bsp_apicid);
+
+	/* It's the time to set ctrl now. */
+	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+	
+	enable_smbus();
+	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
+	
+	print_debug("Starting RAM check... quick\n");
+	quick_ram_check();
+	print_debug(" Done\n");
+	post_cache_as_ram();
+}
Index: src/mainboard/asus/k8v-x_se/devicetree.cb
===================================================================
--- src/mainboard/asus/k8v-x_se/devicetree.cb	(revision 0)
+++ src/mainboard/asus/k8v-x_se/devicetree.cb	(revision 0)
@@ -0,0 +1,93 @@
+chip northbridge/amd/amdk8/root_complex		# Root complex
+  device lapic_cluster 0 on			# APIC cluster
+    chip cpu/amd/socket_754			# CPU
+      device lapic 0 on end			# APIC
+    end
+  end
+  device pci_domain 0 on			# PCI domain
+    chip northbridge/amd/amdk8			# mc0
+      device pci 18.0 on			# Northbridge
+        # Devices on link 0, link 0 == LDT 0
+        chip southbridge/via/vt8237r		# Southbridge
+          register "ide0_enable" = "1"		# Enable IDE channel 0
+          register "ide1_enable" = "1"		# Enable IDE channel 1
+          register "ide0_80pin_cable" = "1"	# 80pin cable on IDE channel 0
+          register "ide1_80pin_cable" = "0"	# 80pin cable on IDE channel 1
+          register "fn_ctrl_lo" = "0"		# Enable SB functions
+          register "fn_ctrl_hi" = "0xad"	# Enable SB functions
+          device pci 0.0 on end			# HT
+          device pci f.0 on end			# SATA
+          device pci f.1 on end			# IDE
+          device pci 11.0 on			# LPC
+            chip drivers/generic/generic	# DIMM 0-0-0
+              device i2c 50 on end
+            end
+            chip drivers/generic/generic	# DIMM 0-0-1
+              device i2c 51 on end
+            end
+            chip superio/winbond/w83627ehg	# Super I/O
+              device pnp 2e.0 on		# Floppy
+                io 0x60 = 0x3f0
+                irq 0x70 = 6
+                drq 0x74 = 2
+              end
+              device pnp 2e.1 on		# Parallel port
+                io 0x60 = 0x378
+                irq 0x70 = 7
+                drq 0x74 = 4
+              end
+              device pnp 2e.2 on		# Com1
+                io 0x60 = 0x3f8
+                irq 0x70 = 4
+              end
+              device pnp 2e.3 off		# Com2 (N/A on this board)
+                io 0x60 = 0x2f8
+                irq 0x70 = 3
+              end
+              device pnp 2e.5 on		# PS/2 keyboard & mouse
+                io 0x60 = 0x60
+                irq 0x70 = 1
+              end
+              device pnp 2e.106 off		# Serial flash interface (SFI)
+                io 0x60 = 0x100
+              end
+              device pnp 2e.007 off		# GPIO 1
+              end
+              device pnp 2e.107 off		# Game port
+                io 0x60 = 0x201
+              end
+              device pnp 2e.207 off		# MIDI
+                io 0x62 = 0x330
+                irq 0x70 = 9
+              end
+              device pnp 2e.307 off		# GPIO 6
+              end
+              device pnp 2e.8 off		# WDTO#, PLED
+              end
+              device pnp 2e.009 on		# GPIO 2
+              end
+              device pnp 2e.109 off		# GPIO 3
+              end
+              device pnp 2e.209 off		# GPIO 4
+              end
+              device pnp 2e.309 on		# GPIO 5
+              end
+              device pnp 2e.a off		# ACPI
+              end
+              device pnp 2e.b on		# Hardware monitor
+                io 0x60 = 0x290
+                irq 0x70 = 0
+              end
+            end
+          end
+          device pci 12.0 on end		# VIA LAN
+        end
+        chip southbridge/via/k8t800		# "Southbridge" K8T800
+        end
+      end
+      device pci 18.1 on end
+      device pci 18.2 on end
+      device pci 18.3 on end
+    end
+  end
+end
Index: src/mainboard/asus/k8v-x_se/mptable.c
===================================================================
--- src/mainboard/asus/k8v-x_se/mptable.c	(revision 0)
+++ src/mainboard/asus/k8v-x_se/mptable.c	(revision 0)
@@ -0,0 +1,127 @@
+/*
+ * This file is part of the coreboot project.
+ * 
+ * Copyright (C) 2011  Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* generated by MPTable, version 2.0.15
+ * as modified by RGM for coreboot 
+ * Heavily modified to meet coreboot quality standards
+ */
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+
+#include "southbridge/via/vt8237r/vt8237r.h"
+#include "southbridge/via/k8t890/k8x8xx.h"
+
+/*
+ * ---------------------- PCI IRQ routing schematic --------------------------
+ * 
+ *                 PCI          IRQ     IRQ      IRQ     IRQ
+ * Device/slot    device       INTA#   INTB#    INTC#   INTD#
+ * ---------------------------------------------------------------------------
+ *  ISA interrupts as usual
+ *  AGP            00.01        16      17       nc      nc
+ *  PCI slot 1     00.0b        16      17       18      19
+ *  PCI slot 2     00.0c        17      18       19      16
+ *  PCI slot 3     00.0d        18      19       16      17
+ *  PCI slot 4     00.0e        19      16       17      18
+ *  SATA / IDE     00.0f        20      20       20      20
+ *  USB            00.10        21      21       21      21
+ *  LPC bus        00.11
+ *    AC97         00.11.5      nc      nc       22      nc
+ *    modem        00.11.6      nc      nc       22      nc
+ *  LAN            00.12.0      23      23       23      23
+ */
+
+static void *smp_write_config_table(void *v)
+{
+	struct mp_config_table *mc;
+	int bus_isa;
+
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+	mptable_init(mc, LAPIC_ADDR);
+
+	smp_write_processors(mc);
+        
+	mptable_write_buses(mc, NULL, &bus_isa);
+
+	/*I/O APICs:    APIC ID Version State           Address*/
+	smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR);
+
+	mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);	
+	
+	/*I/O Ints:          Type    Trigger              Polarity            Bus ID      IRQ         APIC ID          PIN#
+	 */
+	/* PCI slot 1 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x0b << 2) | 0, VT8237R_APIC_ID, 0x10); /* INTA - IRQ16 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x0b << 2) | 1, VT8237R_APIC_ID, 0x11); /* INTB - IRQ17 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x0b << 2) | 2, VT8237R_APIC_ID, 0x12); /* INTC - IRQ18 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x0b << 2) | 3, VT8237R_APIC_ID, 0x13); /* INTD - IRQ19 */
+	/* PCI slot 2*/
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x0c << 2) | 0, VT8237R_APIC_ID, 0x11); /* INTA - IRQ17 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x0c << 2) | 1, VT8237R_APIC_ID, 0x12); /* INTB - IRQ18 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x0c << 2) | 2, VT8237R_APIC_ID, 0x13); /* INTC - IRQ19 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x0c << 2) | 3, VT8237R_APIC_ID, 0x10); /* INTD - IRQ16 */
+	/* PCI slot 3 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x0d << 2) | 0, VT8237R_APIC_ID, 0x12); /* INTA - IRQ18 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x0d << 2) | 1, VT8237R_APIC_ID, 0x13); /* INTB - IRQ19 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x0d << 2) | 2, VT8237R_APIC_ID, 0x10); /* INTC - IRQ16 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x0d << 2) | 3, VT8237R_APIC_ID, 0x11); /* INTD - IRQ17 */
+	/* PCI slot 4 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x0e << 2) | 0, VT8237R_APIC_ID, 0x13); /* INTA - IRQ19 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x0e << 2) | 1, VT8237R_APIC_ID, 0x10); /* INTB - IRQ16 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x0e << 2) | 2, VT8237R_APIC_ID, 0x11); /* INTC - IRQ17 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x0e << 2) | 3, VT8237R_APIC_ID, 0x12); /* INTD - IRQ18 */
+	/* SATA and IDE */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x0f << 2) | 0, VT8237R_APIC_ID, 0x14); /* SATA */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x0f << 2) | 1, VT8237R_APIC_ID, 0x14); /* IDE */
+	/* USB */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x10 << 2) | 0, VT8237R_APIC_ID, 0x15); /* UHCI */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x10 << 2) | 1, VT8237R_APIC_ID, 0x15); /* UHCI */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15); /* EHCI */
+	/* LPC */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x11 << 2) | 2, VT8237R_APIC_ID, 0x16);
+	/* LAN */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0,  (0x12 << 2) | 0, VT8237R_APIC_ID, 0x17); /* Rhine-II LAN */
+	
+	/* AGP slot */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1,  (0x00 << 2) | 0, VT8237R_APIC_ID, 0x10);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1,  (0x00 << 2) | 1, VT8237R_APIC_ID, 0x11);
+
+	/* Local Ints:        Type       Polarity               Trigger               Bus ID  IRQ  APIC ID      PIN#*/
+	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0);
+	smp_write_lintsrc(mc, mp_NMI,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1);
+	/* Compute the checksums. */
+	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+
+	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
+			mc, smp_next_mpe_entry(mc));
+	return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+        void *v;
+        v = smp_write_floating_table(addr);
+        return (unsigned long)smp_write_config_table(v);
+}
Index: src/mainboard/asus/k8v-x_se/irq_tables.c
===================================================================
--- src/mainboard/asus/k8v-x_se/irq_tables.c	(revision 0)
+++ src/mainboard/asus/k8v-x_se/irq_tables.c	(revision 0)
@@ -0,0 +1,101 @@
+/*
+ * This file is part of the coreboot project.
+ * 
+ * Copyright (C) 2011  Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA.
+ */
+
+
+#include <arch/pirq_routing.h>
+#include <device/pci_ids.h>
+
+#define LNKA 1
+#define LNKB 2
+#define LNKC 3
+#define LNKD 4
+/* TODO: Should we connect E-H to A-D ?
+ * Is this dependent on the IRQ router config?
+ */
+#define LNKE 1
+#define LNKF 2
+#define LNKG 3
+#define LNKH 4
+
+#define IRQMSK ( 1<<11 | 1<<10 | 1<<5 | 1<<3 | 1<<14 |1<<15)
+
+
+const struct irq_routing_table intel_irq_routing_table = {
+	.signature = PIRQ_SIGNATURE,    /* u32 signature */
+	.version = PIRQ_VERSION,        /* u16 version */
+	.size = 32 + 16 * 9, /* Max. number of devices on the bus */
+	.rtr_bus = 0x00,                /* Interrupt router bus */
+	.rtr_devfn = (0x11 << 3) | 0x0, /* Interrupt router dev */
+	.exclusive_irqs = 0,            /* IRQs devoted exclusively to PCI usage */
+	.rtr_vendor = 0x1106,           /* Vendor */
+	.rtr_device = 0x3227,           /* Device */
+	.miniport_data = 0,             /* Miniport */
+	.rfu = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	.checksum = 0xbe,               /* Checksum (has to be set to some value that
+					 * would give 0 after the sum of all bytes
+					 * for this structure (including checksum).
+					 */
+	.slots =
+	{
+		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+		/* AGP */
+		{0x00, (0x01 << 3) | 0x0, {{LNKA, IRQMSK}, {LNKB, IRQMSK}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+		/* LPC */
+		{0x00, (0x11 << 3) | 0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {LNKG, IRQMSK}, {0x00, 0x0000}}, 0x0, 0x0},
+		/* SATA and IDE */
+		{0x00, (0x0f << 3) | 0x0, {{LNKE, IRQMSK}, {LNKF, IRQMSK}, {LNKG, IRQMSK}, {LNKH, IRQMSK}}, 0x0, 0x0},
+		/* USB */
+		{0x00, (0x10 << 3) | 0x0, {{LNKE, IRQMSK}, {LNKF, IRQMSK}, {LNKG, IRQMSK}, {LNKH, IRQMSK}}, 0x0, 0x0},
+		/* PCI slots */
+		{0x00, (0x0b << 3) | 0x0, {{LNKA, IRQMSK}, {LNKB, IRQMSK}, {LNKC, IRQMSK}, {LNKD, IRQMSK}}, 0x1, 0x0},
+		{0x00, (0x0c << 3) | 0x0, {{LNKB, IRQMSK}, {LNKC, IRQMSK}, {LNKD, IRQMSK}, {LNKA, IRQMSK}}, 0x2, 0x0},
+		{0x00, (0x0d << 3) | 0x0, {{LNKC, IRQMSK}, {LNKD, IRQMSK}, {LNKA, IRQMSK}, {LNKB, IRQMSK}}, 0x3, 0x0},
+		{0x00, (0x0e << 3) | 0x0, {{LNKD, IRQMSK}, {LNKA, IRQMSK}, {LNKB, IRQMSK}, {LNKC, IRQMSK}}, 0x4, 0x0},
+		/* On-board LAN */
+		{0x00, (0x12 << 3) | 0x0, {{LNKE, IRQMSK}, {LNKF, IRQMSK}, {LNKG, IRQMSK}, {LNKH, IRQMSK}}, 0x0, 0x0},
+		/*
+		0x00, (0x01 << 3) | 0x0, {{0x01, 0xccb8}, {0x02, 0xccb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+		0x00, (0x11 << 3) | 0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x03, 0xccb8}, {0x00, 0x0000}}, 0x0, 0x0},
+		0x00, (0x0f << 3) | 0x0, {{0x01, 0xccb8}, {0x02, 0xccb8}, {0x03, 0xccb8}, {0x05, 0xccb8}}, 0x0, 0x0},
+		0x00, (0x10 << 3) | 0x0, {{0x01, 0xccb8}, {0x02, 0xccb8}, {0x03, 0xccb8}, {0x05, 0xccb8}}, 0x0, 0x0},
+		0x00, (0x0b << 3) | 0x0, {{0x01, 0xccb8}, {0x02, 0xccb8}, {0x03, 0xccb8}, {0x05, 0xccb8}}, 0x1, 0x0},
+		0x00, (0x0c << 3) | 0x0, {{0x02, 0xccb8}, {0x03, 0xccb8}, {0x05, 0xccb8}, {0x01, 0xccb8}}, 0x2, 0x0},
+		0x00, (0x0d << 3) | 0x0, {{0x03, 0xccb8}, {0x05, 0xccb8}, {0x01, 0xccb8}, {0x02, 0xccb8}}, 0x3, 0x0},
+		0x00, (0x0e << 3) | 0x0, {{0x05, 0xccb8}, {0x01, 0xccb8}, {0x02, 0xccb8}, {0x03, 0xccb8}}, 0x4, 0x0},
+		0x00, (0x12 << 3) | 0x0, {{0x01, 0xccb8}, {0x02, 0xccb8}, {0x03, 0xccb8}, {0x05, 0xccb8}}, 0x0, 0x0},
+		 * 
+		 */
+	}
+};
+
+#include <console/console.h>
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	int i;
+	u8 sum = 0;
+	
+	for( i = 0; i < sizeof(intel_irq_routing_table); i++ )
+		sum += ( (u8*)&intel_irq_routing_table )[i];
+	
+	sum = intel_irq_routing_table.checksum - sum;
+	printk(BIOS_DEBUG, " PIRQ table of size %u, correct checksum is %02x\n", sizeof(intel_irq_routing_table), sum);
+	
+	return copy_pirq_routing_table(addr);
+}
Index: src/mainboard/asus/k8v-x_se/acpi_tables.c
===================================================================
--- src/mainboard/asus/k8v-x_se/acpi_tables.c	(revision 0)
+++ src/mainboard/asus/k8v-x_se/acpi_tables.c	(revision 0)
@@ -0,0 +1,153 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Written by Stefan Reinauer <stepan@openbios.org>.
+ * ACPI FADT, FACS, and DSDT table support added by
+ *
+ * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org>
+ * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
+#include <device/device.h>
+#include <device/pci_ids.h>
+#include "northbridge/amd/amdk8/acpi.h"
+#include <cpu/amd/model_fxx_powernow.h>
+#include "southbridge/via/vt8237r/vt8237r.h"
+
+extern const unsigned char AmlCode[];
+
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+	return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
+{
+	k8acpi_write_vars();
+	amd_model_fxx_generate_powernow(0, 0, 0);
+	acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS");
+	return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* Create all subtables for processors. */
+	current = acpi_create_madt_lapics(current);
+
+	/* Write SB IOAPIC. */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				VT8237R_APIC_ID, IO_APIC_ADDR, 0);
+
+	/* IRQ9 ACPI active low. */
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
+
+	/* IRQ0 -> APIC IRQ2. */
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+						current, 0, 0, 2, 0x0);
+
+	/* Create all subtables for processors. */
+	current = acpi_create_madt_lapic_nmis(current,
+			MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
+
+	return current;
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+	unsigned long current;
+	acpi_rsdp_t *rsdp;
+	acpi_srat_t *srat;
+	acpi_rsdt_t *rsdt;
+	acpi_madt_t *madt;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+	acpi_header_t *ssdt;
+	acpi_header_t *dsdt;
+
+	/* Align ACPI tables to 16 byte. */
+	start = (start + 0x0f) & -0x10;
+	current = start;
+
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
+
+	/* We need at least an RSDP and an RSDT table. */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+
+	/* Clear all table memory. */
+	memset((void *) start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt, NULL);
+	acpi_write_rsdt(rsdt);
+
+	/* We explicitly add these tables later on: */
+	printk(BIOS_DEBUG, "ACPI:     * FACS\n");
+	facs = (acpi_facs_t *) current;
+	current += sizeof(acpi_facs_t);
+	acpi_create_facs(facs);
+
+	dsdt = (acpi_header_t *)current;
+	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+	current += dsdt->length;
+	memcpy(dsdt, &AmlCode, dsdt->length);
+	dsdt->checksum = 0;	/* Don't trust iasl to get this right. */
+	dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
+		     dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:     * FADT\n");
+
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdp, fadt);
+
+	/* If we want to use HPET timers Linux wants it in MADT. */
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	acpi_add_table(rsdp, madt);
+
+	printk(BIOS_DEBUG, "ACPI:    * SRAT\n");
+	srat = (acpi_srat_t *) current;
+	acpi_create_srat(srat);
+	current += srat->header.length;
+	acpi_add_table(rsdp, srat);
+	
+	/* SSDT */
+	printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
+	ssdt = (acpi_header_t *)current;
+
+	acpi_create_ssdt_generator(ssdt, "DYNADATA");
+	current += ssdt->length;
+	acpi_add_table(rsdp, ssdt);
+
+	printk(BIOS_INFO, "ACPI: done.\n");
+	return current;
+}
Index: src/mainboard/asus/k8v-x_se/chip.h
===================================================================
--- src/mainboard/asus/k8v-x_se/chip.h	(revision 0)
+++ src/mainboard/asus/k8v-x_se/chip.h	(revision 0)
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {};
Index: src/mainboard/asus/k8v-x_se/dsdt.asl
===================================================================
--- src/mainboard/asus/k8v-x_se/dsdt.asl	(revision 0)
+++ src/mainboard/asus/k8v-x_se/dsdt.asl	(revision 0)
@@ -0,0 +1,195 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+ * ISA portions taken from QEMU acpi-dsdt.dsl.
+ */
+
+DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
+{
+	#include "northbridge/amd/amdk8/util.asl"
+	/* Define the main processor.*/
+	Scope (\_PR)
+	{
+		Processor (\_PR.CPU0, 0x00, 0x000000, 0x00) {}
+	}
+
+	/* For now only define 2 power states:
+	 *  - S0 which is fully on
+	 *  - S5 which is soft off
+	 * Any others would involve declaring the wake up methods.
+	 */
+	Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
+	Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
+
+	/* Root of the bus hierarchy */
+	Scope (\_SB)
+	{
+		/* Top PCI device */
+		Device (PCI0)
+		{
+			Name (_HID, EisaId ("PNP0A03"))
+			Name (_ADR, 0x00)
+			Name (_UID, 0x00)
+			Name (_BBN, 0x00)
+
+			External (BUSN)
+			External (MMIO)
+			External (PCIO)
+			External (SBLK)
+			External (TOM1)
+			External (HCLK)
+			External (SBDN)
+			External (HCDN)
+
+			Method (_CRS, 0, NotSerialized)
+			{
+				Name (BUF0, ResourceTemplate ()
+				{
+					IO (Decode16,
+					0x0CF8,             /* Address Range Minimum */
+					0x0CF8,             /* Address Range Maximum */
+					0x01,               /* Address Alignment     */
+					0x08,               /* Address Length        */
+					)
+					WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+					0x0000,             /* Address Space Granularity  */
+					0x0000,             /* Address Range Minimum      */
+					0x0CF7,             /* Address Range Maximum      */
+					0x0000,             /* Address Translation Offset */
+					0x0CF8,             /* Address Length             */
+					,, , TypeStatic)
+				})
+				/* Methods bellow use SSDT to get actual MMIO regs
+				   The IO ports are from 0xd00, optionally an VGA,
+				   otherwise the info from MMIO is used.
+				*/
+				Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
+				Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
+				Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
+				Return (Local3)
+			}
+
+			/* PCI Routing Table */
+			/* aaa */
+			Name (_PRT, Package () {
+				/* AGP slot */
+				Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 },
+				Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 }, 
+				/* PCI slots */
+				Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* PCI Slot 1 */
+				Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 },
+				Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 },
+				Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 },
+				Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 }, /* PCI Slot 2 */
+				Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 },
+				Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 },
+				Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 },
+				Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 }, /* PCI Slot 3 */
+				Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 },
+				Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 },
+				Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 },
+				Package (0x04) { 0x000EFFFF, 0x00, 0x00, 0x13 }, /* PCI Slot 4 */
+				Package (0x04) { 0x000EFFFF, 0x01, 0x00, 0x10 },
+				Package (0x04) { 0x000EFFFF, 0x02, 0x00, 0x11 },
+				Package (0x04) { 0x000EFFFF, 0x03, 0x00, 0x12 },
+				/* SATA and IDE */
+				Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */
+				Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */
+				Package (0x04) { 0x000FFFFF, 0x02, 0x00, 0x14 },
+				Package (0x04) { 0x000FFFFF, 0x03, 0x00, 0x14 },
+				/* USB routing */
+				Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 },
+				Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 },
+				Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },
+				Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 },
+				/* VIA8237R LPC bus */
+				Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */
+				/* On-board LAN */
+				Package (0x04) { 0x0012FFFF, 0x00, 0x00, 0x17 },
+				Package (0x04) { 0x0012FFFF, 0x01, 0x00, 0x17 },
+				Package (0x04) { 0x0012FFFF, 0x02, 0x00, 0x17 },
+				Package (0x04) { 0x0012FFFF, 0x03, 0x00, 0x17 },
+			})
+
+			Device (ISA) {
+				Name (_ADR, 0x00110000)
+				
+				/* PS/2 keyboard (seems to be important for WinXP install) */
+				Device (KBD)
+				{
+					Name (_HID, EisaId ("PNP0303"))
+					Method (_STA, 0, NotSerialized)
+					{
+						Return (0x0f)
+					}
+					Method (_CRS, 0, NotSerialized)
+					{
+						Name (TMP, ResourceTemplate () {
+							IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
+							IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
+							IRQNoFlags () {1}
+						})
+						Return (TMP)
+					}
+				}
+
+				/* PS/2 mouse */
+				Device (MOU)
+				{
+					Name (_HID, EisaId ("PNP0F13"))
+					Method (_STA, 0, NotSerialized)
+					{
+						Return (0x0f)
+					}
+					Method (_CRS, 0, NotSerialized)
+					{
+						Name (TMP, ResourceTemplate () {
+						     IRQNoFlags () {12}
+						})
+						Return (TMP)
+					}
+				}
+
+				/* PS/2 floppy controller */
+				Device (FDC0)
+				{
+					Name (_HID, EisaId ("PNP0700"))
+					Method (_STA, 0, NotSerialized)
+					{
+						Return (0x0f)
+					}
+					Method (_CRS, 0, NotSerialized)
+					{
+						Name (BUF0, ResourceTemplate () {
+							IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
+							IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
+							IRQNoFlags () {6}
+							DMA (Compatibility, NotBusMaster, Transfer8) {2}
+						})
+						Return (BUF0)
+					}
+				}
+			}
+		}
+	}
+}
Index: src/mainboard/asus/k8v-x_se/cmos.layout
===================================================================
--- src/mainboard/asus/k8v-x_se/cmos.layout	(revision 0)
+++ src/mainboard/asus/k8v-x_se/cmos.layout	(revision 0)
@@ -0,0 +1,96 @@
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+395          1       e       1        hw_scrubber
+396          1       e       1        interleave_chip_selects
+397          2       e       8        max_mem_clock
+399         1       e       2        multi_core
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432         8       h       0        boot_countdown
+440          4       e       9        slow_cpu
+444          1       e       1        nmi
+445          1       e       1        iommu
+728        256       h       0        user_data
+984         16       h       0        check_sum
+# Reserve the extended AMD configuration registers
+1000        24       r       0        amd_reserved
+
+
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+8     0     DDR400
+8     1     DDR333
+8     2     DDR266
+8     3     DDR200
+9     0     off
+9     1     87.5%
+9     2     75.0%
+9     3     62.5%
+9     4     50.0%
+9     5     37.5%
+9     6     25.0%
+9     7     12.5%
+
+checksums
+
+checksum 392 983 984
Index: src/mainboard/asus/k8v-x_se/mainboard.c
===================================================================
--- src/mainboard/asus/k8v-x_se/mainboard.c	(revision 0)
+++ src/mainboard/asus/k8v-x_se/mainboard.c	(revision 0)
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "chip.h"
+
+struct chip_operations mainboard_ops = {
+	CHIP_NAME("ASUS K8V_X SE Mainboard")
+};

