msrtool 4966M
Detected system linux: Linux with /dev/cpu/*/msr
Detected target geodegx2: AMD Geode(tm) GX2
Detected target cs5536: AMD Geode(tm) CS5536


# geodegx2 MSRs:
# MC_CF07_DATA
# 63:60 D1_SZ DIMM1 Size
#    56 D1_MB DIMM1 Module Banks
#    52 D1_CB DIMM1 Component Banks
# 50:48 D1_PSZ DIMM1 Page Size
# 47:44 D0_SZ DIMM0 Size
#    40 D0_MB DIMM0 Module Banks
#    36 D0_CB DIMM0 Component Banks
# 34:32 D0_PSZ DIMM0 Page Size
# 29:28 EMR_BA Mode Register Set Bank Address
#    26 EMR_QFC Extended Mode Register FET Control
#    25 EMR_DRV Extended Mode Register Drive Strength Control
#    24 EMR_DLL Extended Mode Register DLL
#  23:8 REF_INT Refresh Interval
#   7:6 REF_STAG Refresh Staggering
#     3 REF_TST Test Refresh
#     1 SOFT_RST Software Reset
#     0 PROG_DRAM Program Mode Register in SDRAM
0x20000018 0x1007711300003400

# MC_CF8F_DATA
# 63:56 STALE_REQ GLIU Max Stale Request Count
# 52:51 XOR_BIT_SEL XOR Bit Select
#    50 XOR_MB0 XOR MB0 Enable
#    49 XOR_BA1 XOR BA1 Enable
#    48 XOR_BA0 XOR BA0 Enable
#    39 AP_B2B Autoprecharge Back-to-Back Command
#    38 AP_EN Autoprecharge
#    33 HOI_LOI High / Low Order Interleave Select
#    31 THZ_DLY tHZ Delay
# 30:28 CAS_LAT Read CAS Latency
# 27:24 REF2ACT ACT to ACT/REF Period. tRC
# 23:20 ACT2PRE ACT to PRE Period. tRAS
# 18:16 PRE2ACT PRE to ACT Period. tRP
# 14:12 ACT2CMD Delay Time from ACT to Read/Write. tRCD
#  11:8 ACT2ACT ACT(0) to ACT(1) Period. tRRD
#   7:6 DPLWR Data-in to PRE Period. tDPLW
#   5:4 DPLRD Data-in to PRE Period. tDPLR
#   2:0 DAL Data-in to ACT (REF) Period. tDAL
0x20000019 0x18000008296332a3

# MC_CF1017_DATA
#     8 PM1_UP_DLY PMode1 Up Delay
#   2:0 WR2DAT Write Command to Data Latency
0x2000001a 0x0000000000000101

# MC_CFPERF_CNT1
# 63:32 CNT0 Counter 0
#  31:0 CNT1 Counter 1
0x2000001b 0x0000000000000000

# MC_PERFCNT2
#    35 STOP_CNT1 Stop Counter 1
#    34 RST_CNT1 Reset Counter 1
#    33 STOP_CNT0 Stop Counter 0
#    32 RST_CNT0 Reset Counter 0
# 31:24 CNT1_MASK Counter 1 Mask
# 23:16 CNT1_DATA Counter 1 Data
#  15:8 CNT0_MASK Counter 0 Mask
#   7:0 CNT0_DATA Counter 0 Data
0x2000001c 0x0000000000ff00ff

# MC_CFCLK_DBUG
#    34 B2B_EN Back-to-Back Command Enable
#    32 MTEST_EN MTEST Enable
#     9 MASK_CKE[1:0] CKE Mask
#     8 MASK_CKE0 CKE0 Mask
#     7 CNTL_MSK1 Control Mask 1
#     6 CNTL_MSK0 Control Mask 0
#     5 ADRS_MSK Address Mask
0x2000001d 0x0000000000000000

# GLCP_DELAY_CONTROLS
#    63 EN Delay Settings Enable
# 60:56 GIO Delay Geode Companion Device
# 55:51 PCI_IN Delay PCI Inputs
# 50:46 PCI_OUT Delay PCI Outputs
# 40:36 DOTCLK Delay Dot Clock
# 35:31 DRGB Delay Digital RGBs
# 30:26 SDCLK_IN Delay SDRAM Clock Input
# 25:21 SDCLK_OUT Delay SDRAM Clock Output
# 20:16 MEM_CTL Delay Memory Controls
#     6 MEM_ODDOUT Delay Odd Memory Data Output Bits
#   3:2 DQS_CLK_IN Delay DQS Before Clocking Input
#   1:0 DQS_CLK_OUT Delay DQS Before Clocking Output
0x4c00000f 0x830d415f8ea0ad6f

# GLCP_SYS_RSTPLL
# 44:41 MDIV GLIU1 Divisor
# 40:38 VDIV CPU Core Divisor
# 37:32 FBDIV Feedback Devisor
# 31:26 SWFLAGS Software Flags
#    25 LOCK PLL Lock
#    24 LOCKWAIT Lock Wait
# 23:16 HOLD_COUNT Hold Count, divided by 16
#    15 BYPASS PLL Bypass
#    14 PD Power Down
#    13 RESETPLL PLL Reset
#    10 DDRMODE DDR Mode
#     9 VA_SEMI_SYNC_MODE Synchronous CPU Core and GLIU1
#     8 PCI_SEMI_SYNC_MODE Synchronous CPU Core and GLIU1
#     7 DSTALL Debug Stall
#   6:4 BOOTSTRAP_STAT Bootstrap Status
#     3 DOTPOSTDIV3 DOTPLL Post-Divide by 3
#     2 DOTPREMULT2 DOTPLL Pre-Multiply by 2
#     1 DOTPREDIV2 DOTPLL Pre-Divide by 2
#     0 CHIP_RESET Chip Reset
0x4c000014 0x0000022606de0070
# cs5536 MSRs:
# DIVIL_LBAR_IRQ
# 47:44 IO_MASK I/O Address Mask Value
#    32 LBAR_EN LBAR Enable
#  15:5 BASE_ADDR Base Address in I/O Space
0x51400008 0x0000f00100001000

# DIVIL_LBAR_KEL
# 63:44 MEM_MASK Memory Address Mask Value
#    32 LBAR_EN LBAR Enable
# 31:12 BASE_ADDR Base Address in Memory Space
0x51400009 0xfffff001efc00000

# DIVIL_LBAR_SMB
# 47:44 IO_MASK I/O Address Mask Value
#    32 LBAR_EN LBAR Enable
#  15:8 BASE_ADDR Base Address in I/O Space
0x5140000b 0x0000f00100006000

# DIVIL_LBAR_GPIO
# 47:44 IO_MASK I/O Address Mask Value
#    32 LBAR_EN LBAR Enable
#  15:8 BASE_ADDR Base Address in I/O Space
0x5140000c 0x0000f00100006100

# DIVIL_LBAR_MFGPT
# 47:44 IO_MASK I/O Address Mask Value
#    32 LBAR_EN LBAR Enable
#  15:8 BASE_ADDR Base Address in I/O Space
0x5140000d 0x0000f00100006200

# DIVIL_LBAR_ACPI
# 47:44 IO_MASK I/O Address Mask Value
#    32 LBAR_EN LBAR Enable
#  15:8 BASE_ADDR Base Address in I/O Space
0x5140000e 0x0000f00100009c00

# DIVIL_LBAR_PMS
# 47:44 IO_MASK I/O Address Mask Value
#    32 LBAR_EN LBAR Enable
#  15:7 BASE_ADDR Base Address in I/O Space
0x5140000f 0x0000f00100009d00

# DIVIL_BALL_OPTS
# 11:10 SEC_BOOT_LOC Secondary Boot Location
#   9:8 BOOT_OP_LATCHED Latched Value of Boot Option
#     6 PIN_OPT_LALL All LPC Pin Option Selection
#     5 PIN_OPT_LIRQ LPC_SERIRQ or GPIO21 Pin Option Selection
#     4 PIN_OPT_LDRQ LPC_DRQ# or GPIO20 Pin Option Selection
#   3:2 PRI_BOOT_LOC Primary Boot Location
#     0 PIN_OPT_IDE IDE or Flash Controller Pin Function Selection
0x51400015 0x0000000000000071

# PIC_YSEL_LOW
# 31:28 MAP_Y7 Map Unrestricted Y Input 7
# 27:24 MAP_Y6 Map Unrestricted Y Input 6
# 23:20 MAP_Y5 Map Unrestricted Y Input 5
# 19:16 MAP_Y4 Map Unrestricted Y Input 4
# 15:12 MAP_Y3 Map Unrestricted Y Input 3
#  11:8 MAP_Y2 Map Unrestricted Y Input 2
#   7:4 MAP_Y1 Map Unrestricted Y Input 1
#   3:0 MAP_Y0 Map Unrestricted Y Input 0
0x51400020 0x00000000bb050a00

# PIC_YSEL_HIGH
# 31:28 MAP_Y15 Map Unrestricted Y Input 15
# 27:24 MAP_Y14 Map Unrestricted Y Input 14
# 23:20 MAP_Y13 Map Unrestricted Y Input 13
# 19:16 MAP_Y12 Map Unrestricted Y Input 12
# 15:12 MAP_Y11 Map Unrestricted Y Input 11
#  11:8 MAP_Y10 Map Unrestricted Y Input 10
#   7:4 MAP_Y9 Map Unrestricted Y Input 9
#   3:0 MAP_Y8 Map Unrestricted Y Input 8
0x51400021 0x0000000004000000

# PIC_ZSEL_LOW
# 31:28 MAP_Z7 Map Unrestricted Z Input 7
# 27:24 MAP_Z6 Map Unrestricted Z Input 6
# 23:20 MAP_Z5 Map Unrestricted Z Input 5
# 19:16 MAP_Z4 Map Unrestricted Z Input 4
# 15:12 MAP_Z3 Map Unrestricted Z Input 3
#  11:8 MAP_Z2 Map Unrestricted Z Input 2
#   7:4 MAP_Z1 Map Unrestricted Z Input 1
#   3:0 MAP_Z0 Map Unrestricted Z Input 0
0x51400022 0x0000000000002222

# PIC_ZSEL_HIGH
# 31:28 MAP_Z15 Map Unrestricted Z Input 15
# 27:24 MAP_Z14 Map Unrestricted Z Input 14
# 23:20 MAP_Z13 Map Unrestricted Z Input 13
# 19:16 MAP_Z12 Map Unrestricted Z Input 12
# 15:12 MAP_Z11 Map Unrestricted Z Input 11
#  11:8 MAP_Z10 Map Unrestricted Z Input 10
#   7:4 MAP_Z9 Map Unrestricted Z Input 9
#   3:0 MAP_Z8 Map Unrestricted Z Input 8
0x51400023 0x00000000000aa5b2

# PIC_IRQM_PRIM
#    15 PRIM15_MSK Primary Input 15 Mask
#    14 PRIM14_MSK Primary Input 14 Mask
#    13 PRIM13_MSK Primary Input 13 Mask
#    12 PRIM12_MSK Primary Input 12 Mask
#    11 PRIM11_MSK Primary Input 11 Mask
#    10 PRIM10_MSK Primary Input 10 Mask
#     9 PRIM9_MSK Primary Input 9 Mask
#     8 PRIM8_MSK Primary Input 8 Mask
#     7 PRIM7_MSK Primary Input 7 Mask
#     6 PRIM6_MSK Primary Input 6 Mask
#     5 PRIM5_MSK Primary Input 5 Mask
#     4 PRIM4_MSK Primary Input 4 Mask
#     3 PRIM3_MSK Primary Input 3 Mask
#     1 PRIM1_MSK Primary Input 1 Mask
#     0 PRIM0_MSK Primary Input 0 Mask
0x51400024 0x000000000000ffff

# PIC_IRQM_LPC
#    15 LPC15_EN LPC Input 15 Enable
#    14 LPC14_EN LPC Input 14 Enable
#    13 LPC13_EN LPC Input 13 Enable
#    12 LPC12_EN LPC Input 12 Enable
#    11 LPC11_EN LPC Input 11 Enable
#    10 LPC10_EN LPC Input 10 Enable
#     9 LPC9_EN LPC Input 9 Enable
#     8 LPC8_EN LPC Input 8 Enable
#     7 LPC7_EN LPC Input 7 Enable
#     6 LPC6_EN LPC Input 6 Enable
#     5 LPC5_EN LPC Input 5 Enable
#     4 LPC4_EN LPC Input 4 Enable
#     3 LPC3_EN LPC Input 3 Enable
#     1 LPC1_EN LPC Input 1 Enable
#     0 LPC0_EN LPC Input 0 Enable
0x51400025 0x0000000000000000

# PIC_XIRR_STS_LOW
#    31 IG7_STS_Z Unrestricted Source Z Input 7
#    30 IG7_STS_Y Unrestricted Source Y Input 7
#    29 IG7_STS_LPC LPC Input 7
#    28 IG7_STS_PRIM Primary Input 7
#    27 IG6_STS_Z Unrestricted Source Z Input 6
#    26 IG6_STS_Y Unrestricted Source Y Input 6
#    25 IG6_STS_LPC LPC Input 6
#    24 IG6_STS_PRIM Primary Input 6
#    23 IG5_STS_Z Unrestricted Source Z Input 5
#    22 IG5_STS_Y Unrestricted Source Y Input 5
#    21 IG5_STS_LPC LPC Input 5
#    20 IG5_STS_PRIM Primary Input 5
#    19 IG4_STS_Z Unrestricted Source Z Input 4
#    18 IG4_STS_Y Unrestricted Source Y Input 4
#    17 IG4_STS_LPC LPC Input 4
#    16 IG4_STS_PRIM Primary Input 4
#    15 IG3_STS_Z Unrestricted Source Z Input 3
#    14 IG3_STS_Y Unrestricted Source Y Input 3
#    13 IG3_STS_LPC LPC Input 3
#    12 IG3_STS_PRIM Primary Input 3
#    11 IG2_STS_Z Unrestricted Source Z Input 2
#    10 IG2_STS_Y Unrestricted Source Y Input 2
#     7 IG1_STS_Z Unrestricted Source Z Input 1
#     6 IG1_STS_Y Unrestricted Source Y Input 1
#     5 IG1_STS_LPC LPC Input 1
#     4 IG1_STS_PRIM Primary Input 1
#     1 IG0_STS_LPC LPC Input 0
#     0 IG0_STS_PRIM Primary Input 0
0x51400026 0x0000000000000001

# PIC_XIRR_STS_HIGH
#    31 IG15_STS_Z Unrestricted Source Z Input 15
#    30 IG15_STS_Y Unrestricted Source Y Input 15
#    29 IG15_STS_LPC LPC Input 15
#    28 IG15_STS_PRIM Primary Input 15
#    27 IG14_STS_Z Unrestricted Source Z Input 14
#    26 IG14_STS_Y Unrestricted Source Y Input 14
#    25 IG14_STS_LPC LPC Input 14
#    24 IG14_STS_PRIM Primary Input 14
#    23 IG13_STS_Z Unrestricted Source Z Input 13
#    22 IG13_STS_Y Unrestricted Source Y Input 13
#    21 IG13_STS_LPC LPC Input 13
#    20 IG13_STS_PRIM Primary Input 13
#    19 IG12_STS_Z Unrestricted Source Z Input 12
#    18 IG12_STS_Y Unrestricted Source Y Input 12
#    17 IG12_STS_LPC LPC Input 12
#    16 IG12_STS_PRIM Primary Input 12
#    15 IG11_STS_Z Unrestricted Source Z Input 11
#    14 IG11_STS_Y Unrestricted Source Y Input 11
#    13 IG11_STS_LPC LPC Input 11
#    12 IG11_STS_PRIM Primary Input 11
#    11 IG10_STS_Z Unrestricted Source Z Input 10
#    10 IG10_STS_Y Unrestricted Source Y Input 10
#     9 IG10_STS_LPC LPC Input 10
#     8 IG10_STS_PRIM Primary Input 10
#     7 IG9_STS_Z Unrestricted Source Z Input 9
#     6 IG9_STS_Y Unrestricted Source Y Input 9
#     5 IG9_STS_LPC LPC Input 9
#     4 IG9_STS_PRIM Primary Input 9
#     3 IG8_STS_Z Unrestricted Source Z Input 8
#     2 IG8_STS_Y Unrestricted Source Y Input 8
#     1 IG8_STS_LPC LPC Input 8
#     0 IG8_STS_PRIM Primary Input 8
0x51400027 0x0000000000000000