> So looking at the specs for the display that comes with the ASUS Chromebook C201 I can see the following PIN structure [1] is required on the display end.
I'm confused... there's 30 pins there, but there should only be 20 on the connector. I guess you got this from the panel datasheet directly? If you bought your panel together with the cable, you still don't know how those map to what's on the connector. Looks like they're dropping 10 of them and rearranging the rest, because this looks nothing like the schematics I have. (For reference it starts with two VCC_LED, two VCC33_LCD, then HOTPLUG and two backlight-related pins.)
> Although even if they did have the lane exposes it looks like your helpful advice on the coreboot function would be a bit out of my depth.
It's pretty simple... try this patch (untested) which should implement what I suggested. I think there's a decent chance this might make your other panel work as well. (Note that this is *only* for the exact panel you originally posted log output for. Also: I think this should work, but there's a slim chance wrong pixel clocks may damage a panel, no warranty, yada yada.)
index 74151e85cb..4474ff81aa 100644
--- a/src/soc/rockchip/rk3288/clock.c
@@ -539,6 +539,11 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div, u32 *ext_div)
return -1;
}
+ div->no = 4;
+ div->nf = 91;
+ div->nr = 4;
+ return 0;
+
div->no = no;
best_diff_khz = vco_khz;