Re: [LinuxBIOS] [linuxbios-checkins] r2143 - trunk/LinuxBIOSv2/src/cpu/amd/car

[San Mehat]

Ahhh thanks yh, this will come in handy :)

-san

On 12/14/05, yhlu  wrote:
> San,
>
> this is for you. You can disassembly code with HDT at CAR stage now..
>
> YH
>
> ---------- Forwarded message ----------
> From: [e-mail] 
> Date: Dec 14, 2005 12:08 PM
> Subject: [linuxbios-checkins] r2143 - trunk/LinuxBIOSv2/src/cpu/amd/car
> To: [e-mail]
>
> Author: yhlu
> Date: 2005-12-14 21:08:23 +0100 (Wed, 14 Dec 2005)
> New Revision: 2143
>
> Modified:
>    trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc
> Log:
> support HDT disassembly when cache as ram auto stage
> Modified: trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc
>
> --- trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc  2005-12-14
> 02:39:33 UTC (rev 2142)
> +++ trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc  2005-12-14
> 20:08:23 UTC (rev 2143)
> @@ -1,5 +1,6 @@
> /* by yhlu 6.2005 */
> -/* We will use 4K bytes only */
> +/* yhlu 2005.12 make it support HDT Memory Debuggers with Disassmbly,
> please select the PCI Bus mem for Phys Type*/
> +/* We may need 4K bytes only */
> #define CacheSize DCACHE_RAM_SIZE
> #define CacheBase (0xd0000 - CacheSize)
>
> @@ -12,9 +13,9 @@
>         /*for normal part %ebx already contain cpu_init_detected from
> fallback call */
>
> cache_as_ram_setup:
>   /* hope we can skip the double set for normal part */
>
> #if USE_FALLBACK_IMAGE == 1
>   /* check if cpu_init_detected */
>   movl    $MTRRdefType_MSR, %ecx
>   rdmsr
>
> @@ -22,9 +23,6 @@
>         movl %eax, %ebx  /* We store the status */
>     /* Set MtrrFixDramModEn for clear fixed mtrr */
>   xorl    %eax, %eax
>   xorl    %edx, %edx
>
> enable_fixed_mtrr_dram_modify:
>         movl    $SYSCFG_MSR, %ecx
>         rdmsr
> @@ -32,13 +30,6 @@
>         orl     $SYSCFG_MSR_MtrrFixDramModEn, %eax
>         wrmsr
>    /* Set the default memory type and enable fixed and variable
>
> MTRRs */
>    movl    $MTRRdefType_MSR, %ecx
>    xorl    %edx, %edx
>    /* Enable Variable and Fixed MTRRs */
>    movl    $0x00000c00, %eax
>    wrmsr
>   /*Clear all MTRRs */
>
>   xorl    %edx, %edx
>
> @@ -55,12 +46,6 @@
>          jmp     clear_fixed_var_mtrr
> clear_fixed_var_mtrr_out:
>    /* Enable the MTRRs and IORRs in SYSCFG */
>    movl    $SYSCFG_MSR, %ecx
>    rdmsr
>    orl     $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn),
>
> %eax
>    wrmsr
>
> #if CacheSize == 0x10000
>          /* enable caching for 64K using fixed mtrr */
>          movl    $0x268, %ecx  /* fix4k_c0000*/
> @@ -69,31 +54,34 @@
>          wrmsr
>         movl    $0x269, %ecx
>         wrmsr
> -#endif
> +#else
>
> -#if CacheSize == 0x8000
> #if CacheSize == 0x8000
>       /* enable caching for 32K using fixed mtrr */
>       movl    $0x269, %ecx  /* fix4k_c8000*/
>       movl    $0x06060606, %eax /* WB IO type */
>      movl    %eax, %edx
>      wrmsr
>
> -#endif
>
> #else
>   /* enable caching for 16K/8K/4K using fixed mtrr */
>   movl    $0x269, %ecx  /* fix4k_cc000*/
>
> -#if CacheSize == 0x4000
> #if CacheSize == 0x4000
>     movl    $0x06060606, %edx /* WB IO type */
>
> -#endif
> -#if CacheSize == 0x2000
> #endif
> #if CacheSize == 0x2000
>     movl    $0x06060000, %edx /* WB IO type */
>
> -#endif
> -#if CacheSize == 0x1000
> #endif
> #if CacheSize == 0x1000
>     movl    $0x06000000, %edx /* WB IO type */
>
> -#endif
> #endif
>    xorl    %eax, %eax
>    wrmsr
> #endif
>    /* enable memory access for 0 - 1MB using top_mem */
>
> +#endif
>    /* enable memory access for first MBs using top_mem */
>    movl    $TOP_MEM, %ecx
>    xorl    %edx, %edx
>    movl    $(((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) &
>
> ~TOP_MEM_MASK) , %eax
> @@ -101,7 +89,6 @@
> #endif /*  USE_FALLBACK_IMAGE == 1*/
>
> #if USE_FALLBACK_IMAGE == 0
>    /* disable cache */
>    movl    %cr0, %eax
>    orl    $(0x1<<30),%eax
>
> @@ -119,11 +106,26 @@
>          wrmsr
>      movl    $0x203, %ecx
>    movl    $0x0000000f, %edx
>    movl    $0x0000000f, %edx  /* AMD 40 bit */
>    movl    $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
>    wrmsr
>
> #endif /* XIP_ROM_SIZE && XIP_ROM_BASE */
>
> +#if USE_FALLBACK_IMAGE == 1
>    /* Set the default memory type and enable fixed and variable
>
> MTRRs */
>    movl    $MTRRdefType_MSR, %ecx
>    xorl    %edx, %edx
>    /* Enable Variable and Fixed MTRRs */
>    movl    $0x00000c00, %eax
>    wrmsr
>    /* Enable the MTRRs and IORRs in SYSCFG */
>    movl    $SYSCFG_MSR, %ecx
>    rdmsr
>    orl     $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn),
>
> %eax
>    wrmsr
>
> +#endif
>    /* enable cache */
>    movl    %cr0, %eax
>    andl    $0x9fffffff,%eax
>
> @@ -132,23 +134,22 @@
> #if USE_FALLBACK_IMAGE == 1
>      /* Read the range with lodsl*/
>    movl    $(CacheBase+CacheSize-4), %esi
>    std
>   cld
>    movl    $CacheBase, %esi
>    movl    $(CacheSize>>2), %ecx
>    rep     lodsl
>    /* Clear the range */
>    movl    $(CacheBase+CacheSize-4), %edi
>    movl    $CacheBase, %edi
>    movl    $(CacheSize>>2), %ecx
>    xorl    %eax, %eax
>    rep     stosl
>
> #endif /*USE_FALLBACK_IMAGE == 1*/
>   /* set up the stack pointer */
>   movl    $(CacheBase+CacheSize-4), %eax
>   movl    %eax, %esp
>
>   /* Restore the BIST result */
>   movl    %ebp, %eax
>   /* We need to set ebp ? No need */