Rudolf Marek wrote:
- if (!devfun7)
return;- /*
* This init code is valid only for the VT8237A! For different* sounthbridges (e.g. VT8237S, VT8237R (without plus R)typo :) maybe was just copied? Did you get the values from orig bios? Or just copied? For what vlink mode it is 8x? I got some VIA recommended values but they are bit different 0xb5 is 0x88.
- /* FIXME: Intel needs more bit set for C2/C3. */
- /*
* Allow SLP# signal to assert LDTSTOP_L.* Will work for C3 and for FID/VID change. FIXME FIXME, pre rev A2.What is fixme fixme pre revA2?
*/- outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);
- dump_south(dev);
+}
- static void vt8237s_init(struct device *dev) { u32 tmp;
@@ -541,7 +584,7 @@ .read_resources = vt8237r_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources,
- .init = vt8237r_init,
- .init = vt8237a_init, .scan_bus = scan_static_bus, };
Otherwise fine.
Updated patch:
This adds VT8237A specific VLINK/LPC init functions in vt8237_ctrl.c, vt8237r_lpc.c and vt8237r_early_smbus.c I ran some tests and apparently both the
| /* So the chip knows we are on AMD. */ | pci_write_config8(devctl, 0x7c, 0x7f);
and
| /* | * Allow SLP# signal to assert LDTSTOP_L. | * Will work for C3 and for FID/VID change. | */ | outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);
in vt8237r_early_smbus.c are needed on VT8237A, otherwise I get a (non-fatal) fid/vid change error on boot.
While vt8237a_vlink_init() in vt8237_ctrl.c is a modified vt8237r_vlink_init(), vt8237a_init() in vt8237r_lpc.c is a modified vt8237s_init().
Signed-off-by: Tobias Diedrich ranma+coreboot@tdiedrich.de
---
Index: src/southbridge/via/vt8237r/vt8237_ctrl.c =================================================================== --- src/southbridge/via/vt8237r/vt8237_ctrl.c.orig 2010-11-03 15:23:19.000000000 +0100 +++ src/southbridge/via/vt8237r/vt8237_ctrl.c 2010-11-03 15:37:25.000000000 +0100 @@ -168,6 +168,75 @@
}
+static void vt8237a_vlink_init(struct device *dev) +{ + u8 reg; + device_t devfun7; + + devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8T890CE_7, 0); + if (!devfun7) + devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8M890CE_7, 0); + if (!devfun7) + devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8T890CF_7, 0); + /* No pairing NB was found. */ + if (!devfun7) + return; + + /* + * This init code is valid only for the VT8237A! For different + * sounthbridges (e.g. VT8237S, VT8237R and VT8251) a different + * init code is required. + * + * FIXME: This is based on vt8237r_vlink_init() in + * k8t890/k8t890_ctrl.c and modified to fit what the AMI + * BIOS on my M2V wrote to these registers (by looking + * at lspci -nxxx output). + * Works for me. + */ + + /* disable auto disconnect */ + reg = pci_read_config8(devfun7, 0x42); + reg &= ~0x4; + pci_write_config8(devfun7, 0x42, reg); + + /* NB part setup */ + pci_write_config8(devfun7, 0xb5, 0x88); + pci_write_config8(devfun7, 0xb6, 0x88); + pci_write_config8(devfun7, 0xb7, 0x61); + + reg = pci_read_config8(devfun7, 0xb4); + reg |= 0x11; + pci_write_config8(devfun7, 0xb4, reg); + + pci_write_config8(devfun7, 0xb0, 0x6); + pci_write_config8(devfun7, 0xb1, 0x1); + + /* SB part setup */ + pci_write_config8(dev, 0xb7, 0x50); + pci_write_config8(dev, 0xb9, 0x88); + pci_write_config8(dev, 0xba, 0x8a); + pci_write_config8(dev, 0xbb, 0x88); + + reg = pci_read_config8(dev, 0xbd); + reg |= 0x3; + reg &= ~0x4; + pci_write_config8(dev, 0xbd, reg); + + reg = pci_read_config8(dev, 0xbc); + reg &= ~0x7; + pci_write_config8(dev, 0xbc, reg); + + pci_write_config8(dev, 0x48, 0x23); + + /* enable auto disconnect, for STPGNT and HALT */ + reg = pci_read_config8(devfun7, 0x42); + reg |= 0x7; + pci_write_config8(devfun7, 0x42, reg); +} + static void ctrl_enable(struct device *dev) { /* Enable the 0:13 and 0:13.1. */ @@ -193,6 +262,12 @@ vt8237s_vlink_init(dev); }
+ devsb = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237A_LPC, 0); + if (devsb) { + vt8237a_vlink_init(dev); + } + /* Configure PCI1 and copy mirror registers from D0F3. */ vt8237_cfg(dev); dump_south(dev); Index: src/southbridge/via/vt8237r/vt8237r_lpc.c =================================================================== --- src/southbridge/via/vt8237r/vt8237r_lpc.c.orig 2010-11-03 15:23:19.000000000 +0100 +++ src/southbridge/via/vt8237r/vt8237r_lpc.c 2010-11-03 15:50:51.000000000 +0100 @@ -319,6 +319,55 @@ printk(BIOS_SPEW, "Leaving %s.\n", __func__); }
+static void vt8237a_init(struct device *dev) +{ + /* + * FIXME: This is based on vt8237s_init() and the values the AMI + * BIOS on my M2V wrote to these registers (by loking + * at lspci -nxxx output). + * Works for me. + */ + u32 tmp; + + /* Set bit 3 of 0x4f (use INIT# as CPU reset). */ + tmp = pci_read_config8(dev, 0x4f); + tmp |= 0x08; + pci_write_config8(dev, 0x4f, tmp); + + /* + * bit2: REQ5 as PCI request input - should be together with INTE-INTH. + * bit5: usb power control lines as gpio + */ + pci_write_config8(dev, 0xe4, 0x24); + /* + * Enable APIC wakeup from INTH + * Enable SATA LED, disable special CPU Frequency Change - + * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs. + */ + pci_write_config8(dev, 0xe5, 0x69); + + /* Reduce further the STPCLK/LDTSTP signal to 5us. */ + pci_write_config8(dev, 0xec, 0x4); + + /* Host Bus Power Management Control, maybe not needed */ + pci_write_config8(dev, 0x8c, 0x5); + + /* Enable HPET at VT8237R_HPET_ADDR. */ + pci_write_config32(dev, 0x68, (VT8237R_HPET_ADDR | 0x80)); + + southbridge_init_common(dev); + + /* FIXME: Intel needs more bit set for C2/C3. */ + + /* + * Allow SLP# signal to assert LDTSTOP_L. + * Will work for C3 and for FID/VID change. + */ + outb(0x1, VT8237R_ACPI_IO_BASE + 0x11); + + dump_south(dev); +} + static void vt8237s_init(struct device *dev) { u32 tmp; @@ -537,6 +586,14 @@ .scan_bus = scan_static_bus, };
+static const struct device_operations vt8237r_lpc_ops_a = { + .read_resources = vt8237r_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = vt8237a_init, + .scan_bus = scan_static_bus, +}; + static const struct pci_driver lpc_driver_r __pci_driver = { .ops = &vt8237r_lpc_ops_r, .vendor = PCI_VENDOR_ID_VIA, @@ -544,7 +601,7 @@ };
static const struct pci_driver lpc_driver_a __pci_driver = { - .ops = &vt8237r_lpc_ops_r, + .ops = &vt8237r_lpc_ops_a, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_VT8237A_LPC, }; Index: src/southbridge/via/vt8237r/vt8237r_early_smbus.c =================================================================== --- src/southbridge/via/vt8237r/vt8237r_early_smbus.c.orig 2010-11-03 15:23:19.000000000 +0100 +++ src/southbridge/via/vt8237r/vt8237r_early_smbus.c 2010-11-03 15:23:22.000000000 +0100 @@ -257,19 +257,30 @@ return;
devid = pci_read_config16(dev, PCI_DEVICE_ID); - if (devid == PCI_DEVICE_ID_VIA_VT8237S_LPC) { - devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237_VLINK), 0);
- if (devctl == PCI_DEV_INVALID) - return; + /* generic setup */ + + /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */ + pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1); + + /* Enable ACPI accessm RTC signal gated with PSON. */ + pci_write_config8(dev, 0x81, 0x84); + + /* chipset-specific parts */
- /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */ - pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1); + /* VLINK: FIXME: can we drop the devid check and just look for the VLINK device? */ + if (devid == PCI_DEVICE_ID_VIA_VT8237S_LPC || + devid == PCI_DEVICE_ID_VIA_VT8237A_LPC) { + devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237_VLINK), 0);
- /* Enable ACPI accessm RTC signal gated with PSON. */ - pci_write_config8(dev, 0x81, 0x84); + if (devctl != PCI_DEV_INVALID) { + /* So the chip knows we are on AMD. */ + pci_write_config8(devctl, 0x7c, 0x7f); + } + }
+ if (devid == PCI_DEVICE_ID_VIA_VT8237S_LPC) { /* * Allow SLP# signal to assert LDTSTOP_L. * Will work for C3 and for FID/VID change. @@ -280,17 +291,10 @@ /* Reduce further the STPCLK/LDTSTP signal to 5us. */ pci_write_config8(dev, 0xec, 0x4);
- /* So the chip knows we are on AMD. */ - pci_write_config8(devctl, 0x7c, 0x7f); - return; }
- /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */ - pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1); - - /* Enable ACPI accessm RTC signal gated with PSON. */ - pci_write_config8(dev, 0x81, 0x84); + /* VT8237R and VT8237A */
/* * Allow SLP# signal to assert LDTSTOP_L.