-------- Original Message --------
Subject: Re: [coreboot] Coreboot on X230 and Dualboot / How to make it work
Local Time: 26 September 2017 12:49 PM
UTC Time: 26 September 2017 10:49
From: one7two99@protonmail.com

Next step is to clean the flashregion_2_intel_me.bin (me.bin) with me_cleaner which is describe well.

It seems that ME_cleaner is now included in Coreboot looking at the options in menuconfig. As such I asssume I don't need to manually clean flashregion_2_intel_me.bin (me.bin)

The extracted Blobs are located at ./3rdparty/blobs/mainboard/lenovo/x230 and have been proper renamed and I have enabled the options under "Chipset":

*** Intel Firmware ***
[*] Add Intel descriptor.bin file
[ ]   Configure IFD for EM100 usage
[*]   Add Intel ME/TXE firmware
[*]     Verify the integrity of the supplied ME/TXE firmware                                          │
[*]     Strip down the Intel ME/TXE firmware
[*]   Add gigabit ethernet firmware

I have enlarged the CBFS under coreboot nconfig in "Mainboard"

ROM chip size (12288 KB (12 MB))
(0x100000) Size of CBFS filesystem in ROM    

0x100000 wasn't enough, so I tried 0x200000 which was enough to add corinfo as secondary payload. Adding also nvramcui would need a bigger CBFS.
The later works if I increase the size of CBFS to 0x400000, as such I've proceed with this CBFS size.

I've read https://www.coreboot.org/CBFS but honestly, this information is currently more than I can understand (not a hardware hacker :-).
When I look at the picture from me_cleaner...
... the pictures explains to me that the Chips consists of several "areas":
Descriptor / GbE Blob / ME Firmware Blob / BIOS

Is the CBFS something like a "container" within the BIOS, which would mean that if I want to increase the size of the CBFS over a ceratin point I need to shrink ME Firmware (which is covered by the documentation from me_cleaner).
What would be the maximum CBFS size I can use without further modifications to the ME Firmware or will Coreboot reduce the size of the ME Firmware area to gain additional space automatically?

Now the obvious last step is to split the 12 MB coreboot.rom into two parts to flash the upper 4 MB chip and the 8 MB chip (which should include the "cleaned" version of Intel ME, as I have enabled "Strip down the Intel ME/TXE firmware" in the coreboot config).

Getting the last 4 MB of the coreboot.rom is covered by the coreboot wiki:
# to flash the upper 4 MB part of the BIOS:
dd of=x230-4mb.rom bs=1M if=build/coreboot.rom skip=8

to flash the 8 mb chip I'll try:
dd of=x230-8mb.tom bs=1M if=build/coreboot.rom count=8

Is the above approach correct? I tried so already once but it didn't work (short flashing of Power-On-button -> nothing more)