coreboot-4.0-4566-g56ea9c4 Mon Jul 29 15:26:27 BST 2013 starting...
Setting up static southbridge registers... done.
Disabling Watchdog reboot... done.
Setting up static northbridge registers... done.
Initializing Graphics...
Back from sandybridge_early_initialization()
POST: 0x38
SMBus controller enabled.
Memory Straps:
 - memory capacity 2GB
 - die revision 1
 - vendor Samsung
CBFS: CBFS_HEADER_ROM_ADDRESS: 0xfffff9c0/0x800000
CBFS: CBFS location: 0x700000~0x7ff9e0, align: 64
CBFS: Looking for 'spd.bin' starting from 0x700000.
CBFS:  - load entry 0x700000 file name (16 bytes)...
CBFS:  (unmatched file @0x700000: cmos_layout.bin)
CBFS:  - load entry 0x7004c0 file name (32 bytes)...
CBFS:  (unmatched file @0x7004c0: pci8086,0106.rom)
CBFS:  - load entry 0x710500 file name (72 bytes)...
CBFS:  (unmatched file @0x710500: cpu_microcode_blob.bin)
CBFS:  - load entry 0x7155c0 file name (32 bytes)...
CBFS:  (unmatched file @0x7155c0: fallback/romstage)
CBFS:  - load entry 0x71e980 file name (32 bytes)...
CBFS:  (unmatched file @0x71e980: fallback/coreboot_ram)
CBFS:  - load entry 0x7682c0 file name (16 bytes)...
CBFS:  (unmatched file @0x7682c0: )
CBFS:  - load entry 0x77ffc0 file name (40 bytes)...
CBFS:  (unmatched file @0x77ffc0: mrc.cache)
CBFS:  - load entry 0x780000 file name (32 bytes)...
CBFS:  (unmatched file @0x780000: fallback/payload)
CBFS:  - load entry 0x79a100 file name (16 bytes)...
CBFS:  (unmatched file @0x79a100: )
CBFS:  - load entry 0x7dbfc0 file name (40 bytes)...
CBFS: Found file (offset=0x7dc000, len=1536).
POST: 0x39
CPU id(206a7): Intel(R) Celeron(R) CPU 867 @ 1.30GHz
AES NOT supported, TXT NOT supported, VT supported
PCH type: Unknown, device id: 1c49, rev id 5
Intel ME early init
Intel ME firmware is ready
ME: Requested 8MB UMA
Starting UEFI PEI System Agent
CBFS: CBFS_HEADER_ROM_ADDRESS: 0xfffff9c0/0x800000
CBFS: CBFS location: 0x700000~0x7ff9e0, align: 64
CBFS: Looking for 'mrc.bin' starting from 0x700000.
CBFS:  - load entry 0x700000 file name (16 bytes)...
CBFS:  (unmatched file @0x700000: cmos_layout.bin)
CBFS:  - load entry 0x7004c0 file name (32 bytes)...
CBFS:  (unmatched file @0x7004c0: pci8086,0106.rom)
CBFS:  - load entry 0x710500 file name (72 bytes)...
CBFS:  (unmatched file @0x710500: cpu_microcode_blob.bin)
CBFS:  - load entry 0x7155c0 file name (32 bytes)...
CBFS:  (unmatched file @0x7155c0: fallback/romstage)
CBFS:  - load entry 0x71e980 file name (32 bytes)...
CBFS:  (unmatched file @0x71e980: fallback/coreboot_ram)
CBFS:  - load entry 0x7682c0 file name (16 bytes)...
CBFS:  (unmatched file @0x7682c0: )
CBFS:  - load entry 0x77ffc0 file name (40 bytes)...
CBFS:  (unmatched file @0x77ffc0: mrc.cache)
CBFS:  - load entry 0x780000 file name (32 bytes)...
CBFS:  (unmatched file @0x780000: fallback/payload)
CBFS:  - load entry 0x79a100 file name (16 bytes)...
CBFS:  (unmatched file @0x79a100: )
CBFS:  - load entry 0x7dbfc0 file name (40 bytes)...
CBFS:  (unmatched file @0x7dbfc0: spd.bin)
CBFS:  - load ent

*** Log truncated, 1673 characters dropped. ***

Loading image.
CBFS: CBFS_HEADER_ROM_ADDRESS: 0xfffff9c0/0x800000
CBFS: CBFS location: 0x700000~0x7ff9e0, align: 64
CBFS: Looking for 'fallback/coreboot_ram' starting from 0x700000.
CBFS:  - load entry 0x700000 file name (16 bytes)...
CBFS:  (unmatched file @0x700000: cmos_layout.bin)
CBFS:  - load entry 0x7004c0 file name (32 bytes)...
CBFS:  (unmatched file @0x7004c0: pci8086,0106.rom)
CBFS:  - load entry 0x710500 file name (72 bytes)...
CBFS:  (unmatched file @0x710500: cpu_microcode_blob.bin)
CBFS:  - load entry 0x7155c0 file name (32 bytes)...
CBFS:  (unmatched file @0x7155c0: fallback/romstage)
CBFS:  - load entry 0x71e980 file name (32 bytes)...
CBFS: Found file (offset=0x71e9b8, len=301288).
CBFS: loading stage fallback/coreboot_ram @ 0x100000 (409680 bytes), entry @ 0x100000
CBFS: stage loaded.
Jumping to image.
POST: 0x39
coreboot-4.0-4566-g56ea9c4 Mon Jul 29 15:26:27 BST 2013 booting...
POST: 0x40
Enumerating buses...
Show all devs...Before device enumeration.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
APIC: acac: enabled 0
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:16.0: enabled 1
PCI: 00:16.1: enabled 0
PCI: 00:16.2: enabled 0
PCI: 00:16.3: enabled 0
PCI: 00:19.0: enabled 0
PCI: 00:1a.0: enabled 1
PCI: 00:1b.0: enabled 1
PCI: 00:1c.0: enabled 1
PCI: 00:1c.1: enabled 0
PCI: 00:1c.2: enabled 0
PCI: 00:1c.3: enabled 1
PCI: 00:1c.4: enabled 0
PCI: 00:1c.5: enabled 0
PCI: 00:1c.6: enabled 0
PCI: 00:1c.7: enabled 0
PCI: 00:1d.0: enabled 1
PCI: 00:1e.0: enabled 0
PCI: 00:1f.0: enabled 1
PNP: 002e.1: enabled 1
PNP: 002e.2: enabled 0
PNP: 002e.3: enabled 0
PNP: 002e.4: enabled 0
PNP: 002e.7: enabled 1
PNP: 002e.8: enabled 1
PNP: 002e.9: enabled 1
PNP: 00ff.1: enabled 0
IOAPIC: 04: enabled 1
PCI: 00:1f.2: enabled 1
PCI: 00:1f.3: enabled 1
PCI: 00:1f.5: enabled 0
PCI: 00:1f.6: enabled 1
Compare with tree...
Root Device: enabled 1
 CPU_CLUSTER: 0: enabled 1
  APIC: 00: enabled 1
  APIC: acac: enabled 0
 DOMAIN: 0000: enabled 1
  PCI: 00:00.0: enabled 1
  PCI: 00:02.0: enabled 1
  PCI: 00:16.0: enabled 1
  PCI: 00:16.1: enabled 0
  PCI: 00:16.2: enabled 0
  PCI: 00:16.3: enabled 0
  PCI: 00:19.0: enabled 0
  PCI: 00:1a.0: enabled 1
  PCI: 00:1b.0: enabled 1
  PCI: 00:1c.0: enabled 1
  PCI: 00:1c.1: enabled 0
  PCI: 00:1c.2: enabled 0
  PCI: 00:1c.3: enabled 1
  PCI: 00:1c.4: enabled 0
  PCI: 00:1c.5: enabled 0
  PCI: 00:1c.6: enabled 0
  PCI: 00:1c.7: enabled 0
  PCI: 00:1d.0: enabled 1
  PCI: 00:1e.0: enabled 0
  PCI: 00:1f.0: enabled 1
   PNP: 002e.1: enabled 1
   PNP: 002e.2: enabled 0
   PNP: 002e.3: enabled 0
   PNP: 002e.4: enabled 0
   PNP: 002e.7: enabled 1
   PNP: 002e.8: enabled 1
   PNP: 002e.9: enabled 1
   PNP: 00ff.1: enabled 0
   IOAPIC: 04: enabled 1
  PCI: 00:1f.2: enabled 1
  PCI: 00:1f.3: enabled 1
  PCI: 00:1f.5: enabled 0
  PCI: 00:1f.6: enabled 1
scan_static_bus for Root Device
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 enabled
DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
POST: 0x24
PCI: 00:00.0 [8086/0104] ops
Normal boot.
PCI: 00:00.0 [8086/0104] enabled
PCI: 00:02.0 [8086/0000] ops
PCI: 00:02.0 [8086/0106] enabled
PCI: 00:16.0 [8086/1c3a] bus ops
PCI: 00:16.0 [8086/1c3a] enabled
PCI: 00:16.1: Disabling device
PCI: 00:16.1 [8086/1c3b] disabled No operations
PCI: 00:16.2: Disabling device
PCI: 00:16.2 [8086/1c3c] disabled No operations
PCI: 00:16.3: Disabling device
PCI: 00:16.3 [8086/1c3d] disabled No operations
PCI: 00:19.0: Disabling device
PCI: 00:1a.0 [8086/0000] ops
PCI: 00:1a.0 [8086/1c2d] enabled
PCI: 00:1b.0 [8086/0000] ops
PCI: 00:1b.0 [8086/1c20] enabled
PCI: 00:1c.0 [8086/0000] bus ops
PCI: 00:1c.0 [8086/1c10] enabled
PCI: 00:1c.1: Disabling device
PCI: 00:1c.2: Disabling device
PCI: 00:1c.3 [8086/0000] bus ops
PCI: 00:1c.3 [8086/1c16] enabled
PCI: 00:1c.4: Disabling device
PCI: 00:1c.4: check set enabled
PCI: 00:1c.5: Disabling device
PCI: 00:1c.6: Disabling device
PCI: 00:1c.7: Disabling device
PCH: RPFN 0x76543210 -> 0xfedc3a90
PCI: 00:1d.0 [8086/0000] ops
PCI: 00:1d.0 [8086/1c26] enabled
PCI: 00:1e.0: Disabling device
PCI: 00:1e.0 [8086/2448] bus ops
PCI: 00:1e.0 [8086/2448] disabled
PCI: 00:1f.0 [8086/0000] bus ops
PCI: 00:1f.0 [8086/1c49] enabled
PCI: 00:1f.2 [8086/0000] ops
PCI: 00:1f.2 [8086/1c03] enabled
PCI: 00:1f.3 [8086/0000] bus ops
PCI: 00:1f.3 [8086/1c22] enabled
PCI: 00:1f.5: Disabling device
PCI: 00:1f.6 [8086/1c24] enabled
POST: 0x25
scan_static_bus for PCI: 00:16.0
scan_static_bus for PCI: 00:16.0 done
do_pci_scan_bridge for PCI: 00:1c.0
memalign Enter, boundary 8, size 24, free_mem_ptr 00160050
memalign 00160050
PCI: pci_scan_bus for bus 01
POST: 0x24
memalign Enter, boundary 8, size 152, free_mem_ptr 00160068
memalign 00160068
PCI: 01:00.0 [168c/0030] enabled
POST: 0x25
PCI: pci_scan_bus returning with max=001
POST: 0x55
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x50
Capability: type 0x10 @ 0x70
Capability: type 0x10 @ 0x40
Enabling Common Clock Configuration
ASPM: Enabled L0s and L1
do_pci_scan_bridge returns max 1
do_pci_scan_bridge for PCI: 00:1c.3
memalign Enter, boundary 8, size 24, free_mem_ptr 00160100
memalign 00160100
PCI: pci_scan_bus for bus 02
POST: 0x24
memalign Enter, boundary 8, size 152, free_mem_ptr 00160118
memalign 00160118
PCI: 02:00.0 [10ec/8168] ops
PCI: 02:00.0 [10ec/8168] enabled
POST: 0x25
PCI: pci_scan_bus returning with max=002
POST: 0x55
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x50
Capability: type 0x10 @ 0x70
Capability: type 0x10 @ 0x40
Enabling Common Clock Configuration
ASPM: Enabled L1
do_pci_scan_bridge returns max 2
scan_static_bus for PCI: 00:1f.0
memalign Enter, boundary 8, size 2560, free_mem_ptr 001601b0
memalign 001601b0
PNP: 002e.1 enabled
PNP: 002e.2 disabled
PNP: 002e.3 disabled
PNP: 002e.4 disabled
PNP: 002e.7 enabled
PNP: 002e.8 enabled
PNP: 002e.9 enabled
PNP: 00ff.1 disabled
IOAPIC: 04 enabled
scan_static_bus for PCI: 00:1f.0 done
scan_static_bus for PCI: 00:1f.3
scan_static_bus for PCI: 00:1f.3 done
PCI: pci_scan_bus returning with max=002
POST: 0x55
scan_static_bus for Root Device done
done
POST: 0x66
found VGA at PCI: 00:02.0
Setting up VGA for PCI: 00:02.0
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0
APIC: 00 missing read_resources
CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
DOMAIN: 0000 read_resources bus 0 link: 0
Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.
PCI: 00:1c.0 read_resources bus 1 link: 0
PCI: 00:1c.0 read_resources bus 1 link: 0 done
PCI: 00:1c.3 read_resources bus 2 link: 0
PCI: 00:1c.3 read_resources bus 2 link: 0 done
PCI: 00:1f.0 read_resources bus 0 link: 0
PCI: 00:1f.0 read_resources bus 0 link: 0 done
DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
 Root Device child on link 0 CPU_CLUSTER: 0
  CPU_CLUSTER: 0 child on link 0 APIC: 00
   APIC: 00
   APIC: acac
  DOMAIN: 0000 child on link 0 PCI: 00:00.0
  DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
  DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
   PCI: 00:00.0
   PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf
   PCI: 00:02.0
   PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10
   PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 101201 index 18
   PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
   PCI: 00:16.0
   PCI: 00:16.0 resource base 0 size 10 align 4 gran 4 limit ffffffffffffffff flags 201 index 10
   PCI: 00:16.1
   PCI: 00:16.2
   PCI: 00:16.3
   PCI: 00:19.0
   PCI: 00:1a.0
   PCI: 00:1a.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10
   PCI: 00:1b.0
   PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
   PCI: 00:1c.0 child on link 0 PCI: 01:00.0
   PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
    PCI: 01:00.0
    PCI: 01:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
    PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30
   PCI: 00:1c.1
   PCI: 00:1c.2
   PCI: 00:1c.3 child on link 0 PCI: 02:00.0
   PCI: 00:1c.3 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
    PCI: 02:00.0
    PCI: 02:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
    PCI: 02:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 1201 index 18
    PCI: 02:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20
   PCI: 00:1c.4
   PCI: 00:1c.5
   PCI: 00:1c.6
   PCI: 00:1c.7
   PCI: 00:1d.0
   PCI: 00:1d.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10
   PCI: 00:1e.0
   PCI: 00:1f.0 child on link 0 PNP: 002e.1
   PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
   PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
   PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
    PNP: 002e.1
    PNP: 002e.1 resource base b00 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
    PNP: 002e.2
    PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60
    PNP: 002e.3
    PNP: 002e.3 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60
    PNP: 002e.4
    PNP: 002e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
    PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PNP: 002e.7
    PNP: 002e.7 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 002e.8
    PNP: 002e.8 resource base 62 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
    PNP: 002e.9
    PNP: 002e.9 resource base a00 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
    PNP: 00ff.1
    IOAPIC: 04
    IOAPIC: 04 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 0
   PCI: 00:1f.2
   PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
   PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
   PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
   PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
   PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
   PCI: 00:1f.2 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 24
   PCI: 00:1f.3
   PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
   PCI: 00:1f.3 resource base 0 size 100 align 8 gran 8 limit ffffffffffffffff flags 201 index 10
   PCI: 00:1f.5
   PCI: 00:1f.6
   PCI: 00:1f.6 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 02:00.0 10 *  [0x0 - 0xff] io
PCI: 00:1c.3 compute_resources_io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:1c.3 1c *  [0x0 - 0xfff] io
PCI: 00:02.0 20 *  [0x1000 - 0x103f] io
PCI: 00:1f.2 20 *  [0x1040 - 0x105f] io
PCI: 00:1f.2 10 *  [0x1060 - 0x1067] io
PCI: 00:1f.2 18 *  [0x1068 - 0x106f] io
PCI: 00:1f.2 14 *  [0x1070 - 0x1073] io
PCI: 00:1f.2 1c *  [0x1074 - 0x1077] io
DOMAIN: 0000 compute_resources_io: base: 1078 size: 1078 align: 12 gran: 0 limit: ffff done
DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 01:00.0 10 *  [0x0 - 0x1ffff] mem
PCI: 01:00.0 30 *  [0x20000 - 0x2ffff] mem
PCI: 00:1c.0 compute_resources_mem: base: 30000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 02:00.0 20 *  [0x0 - 0x3fff] prefmem
PCI: 02:00.0 18 *  [0x4000 - 0x4fff] prefmem
PCI: 00:1c.3 compute_resources_prefmem: base: 5000 size: 100000 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:02.0 18 *  [0x0 - 0xfffffff] prefmem
PCI: 00:02.0 10 *  [0x10000000 - 0x103fffff] mem
PCI: 00:1c.0 20 *  [0x10400000 - 0x104fffff] mem
PCI: 00:1c.3 24 *  [0x10500000 - 0x105fffff] prefmem
PCI: 00:1b.0 10 *  [0x10600000 - 0x10603fff] mem
PCI: 00:1f.6 10 *  [0x10604000 - 0x10604fff] mem
PCI: 00:1f.2 24 *  [0x10605000 - 0x106057ff] mem
PCI: 00:1a.0 10 *  [0x10605800 - 0x10605bff] mem
PCI: 00:1d.0 10 *  [0x10605c00 - 0x10605fff] mem
PCI: 00:1f.3 10 *  [0x10606000 - 0x106060ff] mem
PCI: 00:16.0 10 *  [0x10606100 - 0x1060610f] mem
DOMAIN: 0000 compute_resources_mem: base: 10606110 size: 10606110 align: 28 gran: 0 limit: ffffffff done
avoid_fixed_resources: DOMAIN: 0000
avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: DOMAIN: 0000
constrain_resources: PCI: 00:00.0
constrain_resources: PCI: 00:02.0
constrain_resources: PCI: 00:16.0
constrain_resources: PCI: 00:1a.0
constrain_resources: PCI: 00:1b.0
constrain_resources: PCI: 00:1c.0
constrain_resources: PCI: 01:00.0
constrain_resources: PCI: 00:1c.3
constrain_resources: PCI: 02:00.0
constrain_resources: PCI: 00:1d.0
constrain_resources: PCI: 00:1f.0
constrain_resources: PNP: 002e.1
constrain_resources: PNP: 002e.7
constrain_resources: PNP: 002e.8
constrain_resources: PNP: 002e.9
constrain_resources: IOAPIC: 04
constrain_resources: PCI: 00:1f.2
constrain_resources: PCI: 00:1f.3
constrain_resources: PCI: 00:1f.6
avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff
	lim->base 00001000 lim->limit 0000ffff
avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff
	lim->base 00000000 lim->limit efffffff
Setting resources...
DOMAIN: 0000 allocate_resources_io: base:1000 size:1078 align:12 gran:0 limit:ffff
Assigned: PCI: 00:1c.3 1c *  [0x1000 - 0x1fff] io
Assigned: PCI: 00:02.0 20 *  [0x2000 - 0x203f] io
Assigned: PCI: 00:1f.2 20 *  [0x2040 - 0x205f] io
Assigned: PCI: 00:1f.2 10 *  [0x2060 - 0x2067] io
Assigned: PCI: 00:1f.2 18 *  [0x2068 - 0x206f] io
Assigned: PCI: 00:1f.2 14 *  [0x2070 - 0x2073] io
Assigned: PCI: 00:1f.2 1c *  [0x2074 - 0x2077] io
DOMAIN: 0000 allocate_resources_io: next_base: 2078 size: 1078 align: 12 gran: 0 done
PCI: 00:1c.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:1c.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:1c.3 allocate_resources_io: base:1000 size:1000 align:12 gran:12 limit:ffff
Assigned: PCI: 02:00.0 10 *  [0x1000 - 0x10ff] io
PCI: 00:1c.3 allocate_resources_io: next_base: 1100 size: 1000 align: 12 gran: 12 done
DOMAIN: 0000 allocate_resources_mem: base:d0000000 size:10606110 align:28 gran:0 limit:efffffff
Assigned: PCI: 00:02.0 18 *  [0xd0000000 - 0xdfffffff] prefmem
Assigned: PCI: 00:02.0 10 *  [0xe0000000 - 0xe03fffff] mem
Assigned: PCI: 00:1c.0 20 *  [0xe0400000 - 0xe04fffff] mem
Assigned: PCI: 00:1c.3 24 *  [0xe0500000 - 0xe05fffff] prefmem
Assigned: PCI: 00:1b.0 10 *  [0xe0600000 - 0xe0603fff] mem
Assigned: PCI: 00:1f.6 10 *  [0xe0604000 - 0xe0604fff] mem
Assigned: PCI: 00:1f.2 24 *  [0xe0605000 - 0xe06057ff] mem
Assigned: PCI: 00:1a.0 10 *  [0xe0605800 - 0xe0605bff] mem
Assigned: PCI: 00:1d.0 10 *  [0xe0605c00 - 0xe0605fff] mem
Assigned: PCI: 00:1f.3 10 *  [0xe0606000 - 0xe06060ff] mem
Assigned: PCI: 00:16.0 10 *  [0xe0606100 - 0xe060610f] mem
DOMAIN: 0000 allocate_resources_mem: next_base: e0606110 size: 10606110 align: 28 gran: 0 done
PCI: 00:1c.0 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
PCI: 00:1c.0 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.0 allocate_resources_mem: base:e0400000 size:100000 align:20 gran:20 limit:efffffff
Assigned: PCI: 01:00.0 10 *  [0xe0400000 - 0xe041ffff] mem
Assigned: PCI: 01:00.0 30 *  [0xe0420000 - 0xe042ffff] mem
PCI: 00:1c.0 allocate_resources_mem: next_base: e0430000 size: 100000 align: 20 gran: 20 done
PCI: 00:1c.3 allocate_resources_prefmem: base:e0500000 size:100000 align:20 gran:20 limit:efffffff
Assigned: PCI: 02:00.0 20 *  [0xe0500000 - 0xe0503fff] prefmem
Assigned: PCI: 02:00.0 18 *  [0xe0504000 - 0xe0504fff] prefmem
PCI: 00:1c.3 allocate_resources_prefmem: next_base: e0505000 size: 100000 align: 20 gran: 20 done
PCI: 00:1c.3 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff
PCI: 00:1c.3 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done
Root Device assign_resources, bus 0 link: 0
TOUUD 0x100600000 TOLUD 0x7f200000 TOM 0x80000000
MEBASE 0x7f800000
IGD decoded, subtracting 32M UMA and 2M GTT
TSEG base 0x7c800000 size 8M
Available memory below 4GB: 1992M
Available memory above 4GB: 6M
Adding PCIe config bar base=0xf0000000 size=0x4000000
DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:00.0 cf <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x00 mem<mmconfig>
PCI: 00:02.0 10 <- [0x00e0000000 - 0x00e03fffff] size 0x00400000 gran 0x16 mem64
PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem64
PCI: 00:02.0 20 <- [0x0000002000 - 0x000000203f] size 0x00000040 gran 0x06 io
PCI: 00:16.0 10 <- [0x00e0606100 - 0x00e060610f] size 0x00000010 gran 0x04 mem64
PCI: 00:1a.0 10 <- [0x00e0605800 - 0x00e0605bff] size 0x00000400 gran 0x0a mem
PCI: 00:1b.0 10 <- [0x00e0600000 - 0x00e0603fff] size 0x00004000 gran 0x0e mem64
PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem
PCI: 00:1c.0 20 <- [0x00e0400000 - 0x00e04fffff] size 0x00100000 gran 0x14 bus 01 mem
PCI: 00:1c.0 assign_resources, bus 1 link: 0
PCI: 01:00.0 10 <- [0x00e0400000 - 0x00e041ffff] size 0x00020000 gran 0x11 mem64
PCI: 01:00.0 30 <- [0x00e0420000 - 0x00e042ffff] size 0x00010000 gran 0x10 romem
PCI: 00:1c.0 assign_resources, bus 1 link: 0
PCI: 00:1c.3 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 02 io
PCI: 00:1c.3 24 <- [0x00e0500000 - 0x00e05fffff] size 0x00100000 gran 0x14 bus 02 prefmem
PCI: 00:1c.3 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 mem
PCI: 00:1c.3 assign_resources, bus 2 link: 0
PCI: 02:00.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io
PCI: 02:00.0 18 <- [0x00e0504000 - 0x00e0504fff] size 0x00001000 gran 0x0c prefmem64
PCI: 02:00.0 20 <- [0x00e0500000 - 0x00e0503fff] size 0x00004000 gran 0x0e prefmem64
PCI: 00:1c.3 assign_resources, bus 2 link: 0
PCI: 00:1d.0 10 <- [0x00e0605c00 - 0x00e0605fff] size 0x00000400 gran 0x0a mem
PCI: 00:1f.0 assign_resources, bus 0 link: 0
PNP: 002e.1 60 <- [0x0000000b00 - 0x0000000b00] size 0x00000001 gran 0x00 io
PNP: 002e.7 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
PNP: 002e.8 60 <- [0x0000000062 - 0x0000000062] size 0x00000001 gran 0x00 io
PNP: 002e.9 60 <- [0x0000000a00 - 0x0000000a00] size 0x00000001 gran 0x00 io
PCI: 00:1f.0 assign_resources, bus 0 link: 0
PCI: 00:1f.2 10 <- [0x0000002060 - 0x0000002067] size 0x00000008 gran 0x03 io
PCI: 00:1f.2 14 <- [0x0000002070 - 0x0000002073] size 0x00000004 gran 0x02 io
PCI: 00:1f.2 18 <- [0x0000002068 - 0x000000206f] size 0x00000008 gran 0x03 io
PCI: 00:1f.2 1c <- [0x0000002074 - 0x0000002077] size 0x00000004 gran 0x02 io
PCI: 00:1f.2 20 <- [0x0000002040 - 0x000000205f] size 0x00000020 gran 0x05 io
PCI: 00:1f.2 24 <- [0x00e0605000 - 0x00e06057ff] size 0x00000800 gran 0x0b mem
PCI: 00:1f.3 10 <- [0x00e0606000 - 0x00e06060ff] size 0x00000100 gran 0x08 mem64
PCI: 00:1f.6 10 <- [0x00e0604000 - 0x00e0604fff] size 0x00001000 gran 0x0c mem64
DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
 Root Device child on link 0 CPU_CLUSTER: 0
  CPU_CLUSTER: 0 child on link 0 APIC: 00
   APIC: 00
   APIC: acac
  DOMAIN: 0000 child on link 0 PCI: 00:00.0
  DOMAIN: 0000 resource base 1000 size 1078 align 12 gran 0 limit ffff flags 40040100 index 10000000
  DOMAIN: 0000 resource base d0000000 size 10606110 align 28 gran 0 limit efffffff flags 40040200 index 10000100
  DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3
  DOMAIN: 0000 resource base 100000 size 7c700000 align 0 gran 0 limit 0 flags e0004200 index 4
  DOMAIN: 0000 resource base 100000000 size 600000 align 0 gran 0 limit 0 flags e0004200 index 5
  DOMAIN: 0000 resource base 7c800000 size 2a00000 align 0 gran 0 limit 0 flags f0000200 index 6
  DOMAIN: 0000 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 7
  DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 8
  DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 9
  DOMAIN: 0000 resource base 20000000 size 200000 align 0 gran 0 limit 0 flags f0004200 index a
  DOMAIN: 0000 resource base 40000000 size 200000 align 0 gran 0 limit 0 flags f0004200 index b
   PCI: 00:00.0
   PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf
   PCI: 00:02.0
   PCI: 00:02.0 resource base e0000000 size 400000 align 22 gran 22 limit efffffff flags 60000201 index 10
   PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit efffffff flags 60101201 index 18
   PCI: 00:02.0 resource base 2000 size 40 align 6 gran 6 limit ffff flags 60000100 index 20
   PCI: 00:16.0
   PCI: 00:16.0 resource base e0606100 size 10 align 4 gran 4 limit efffffff flags 60000201 index 10
   PCI: 00:16.1
   PCI: 00:16.2
   PCI: 00:16.3
   PCI: 00:19.0
   PCI: 00:1a.0
   PCI: 00:1a.0 resource base e0605800 size 400 align 10 gran 10 limit efffffff flags 60000200 index 10
   PCI: 00:1b.0
   PCI: 00:1b.0 resource base e0600000 size 4000 align 14 gran 14 limit efffffff flags 60000201 index 10
   PCI: 00:1c.0 child on link 0 PCI: 01:00.0
   PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
   PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
   PCI: 00:1c.0 resource base e0400000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20
    PCI: 01:00.0
    PCI: 01:00.0 resource base e0400000 size 20000 align 17 gran 17 limit efffffff flags 60000201 index 10
    PCI: 01:00.0 resource base e0420000 size 10000 align 16 gran 16 limit efffffff flags 60002200 index 30
   PCI: 00:1c.1
   PCI: 00:1c.2
   PCI: 00:1c.3 child on link 0 PCI: 02:00.0
   PCI: 00:1c.3 resource base 1000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c
   PCI: 00:1c.3 resource base e0500000 size 100000 align 20 gran 20 limit efffffff flags 60081202 index 24
   PCI: 00:1c.3 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20
    PCI: 02:00.0
    PCI: 02:00.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags 60000100 index 10
    PCI: 02:00.0 resource base e0504000 size 1000 align 12 gran 12 limit efffffff flags 60001201 index 18
    PCI: 02:00.0 resource base e0500000 size 4000 align 14 gran 14 limit efffffff flags 60001201 index 20
   PCI: 00:1c.4
   PCI: 00:1c.5
   PCI: 00:1c.6
   PCI: 00:1c.7
   PCI: 00:1d.0
   PCI: 00:1d.0 resource base e0605c00 size 400 align 10 gran 10 limit efffffff flags 60000200 index 10
   PCI: 00:1e.0
   PCI: 00:1f.0 child on link 0 PNP: 002e.1
   PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
   PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
   PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
    PNP: 002e.1
    PNP: 002e.1 resource base b00 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60
    PNP: 002e.2
    PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60
    PNP: 002e.3
    PNP: 002e.3 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60
    PNP: 002e.4
    PNP: 002e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
    PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PNP: 002e.7
    PNP: 002e.7 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
    PNP: 002e.8
    PNP: 002e.8 resource base 62 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60
    PNP: 002e.9
    PNP: 002e.9 resource base a00 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60
    PNP: 00ff.1
    IOAPIC: 04
    IOAPIC: 04 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 0
   PCI: 00:1f.2
   PCI: 00:1f.2 resource base 2060 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
   PCI: 00:1f.2 resource base 2070 size 4 align 2 gran 2 limit ffff flags 60000100 index 14
   PCI: 00:1f.2 resource base 2068 size 8 align 3 gran 3 limit ffff flags 60000100 index 18
   PCI: 00:1f.2 resource base 2074 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c
   PCI: 00:1f.2 resource base 2040 size 20 align 5 gran 5 limit ffff flags 60000100 index 20
   PCI: 00:1f.2 resource base e0605000 size 800 align 11 gran 11 limit efffffff flags 60000200 index 24
   PCI: 00:1f.3
   PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
   PCI: 00:1f.3 resource base e0606000 size 100 align 8 gran 8 limit efffffff flags 60000201 index 10
   PCI: 00:1f.5
   PCI: 00:1f.6
   PCI: 00:1f.6 resource base e0604000 size 1000 align 12 gran 12 limit efffffff flags 60000201 index 10
Done allocating resources.
POST: 0x88
Enabling resources...
PCI: 00:00.0 subsystem <- 1ae0/c000
PCI: 00:00.0 cmd <- 06
PCI: 00:02.0 subsystem <- 1ae0/c000
PCI: 00:02.0 cmd <- 03
PCI: 00:16.0 subsystem <- 1ae0/c000
PCI: 00:16.0 cmd <- 02
PCI: 00:1a.0 subsystem <- 1ae0/c000
PCI: 00:1a.0 cmd <- 102
PCI: 00:1b.0 subsystem <- 1ae0/c000
PCI: 00:1b.0 cmd <- 102
PCI: 00:1c.0 bridge ctrl <- 0003
PCI: 00:1c.0 subsystem <- 1ae0/c000
PCI: 00:1c.0 cmd <- 106
PCI: 00:1c.3 bridge ctrl <- 0003
PCI: 00:1c.3 subsystem <- 1ae0/c000
PCI: 00:1c.3 cmd <- 107
PCI: 00:1d.0 subsystem <- 1ae0/c000
PCI: 00:1d.0 cmd <- 102
pch_decode_init
PCI: 00:1f.0 subsystem <- 1ae0/c000
PCI: 00:1f.0 cmd <- 107
PCI: 00:1f.2 subsystem <- 1ae0/c000
PCI: 00:1f.2 cmd <- 03
PCI: 00:1f.3 subsystem <- 1ae0/c000
PCI: 00:1f.3 cmd <- 103
PCI: 00:1f.6 subsystem <- 1ae0/c000
PCI: 00:1f.6 cmd <- 02
PCI: 01:00.0 cmd <- 02
PCI: 02:00.0 cmd <- 03
done.
POST: 0x89
Initializing devices...
Root Device init
lumpy_ec_init
.CPU_CLUSTER: 0 init
memalign Enter, boundary 8, size 49, free_mem_ptr 00160bb0
memalign 00160bb0
start_eip=0x00001000, code_size=0x00000031
Installing SMM handler to 0x7c800000
Installing IED header to 0x7cc00000
Initializing SMM handler... ... pmbase = 0x0500

SMI_STS: PM1 
PM1_STS: WAK BM 
GPE0_STS: GPIO15 GPIO14 GPIO13 GPIO11 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 SMB_WAK 
ALT_GP_SMI_STS: GPI15 GPI14 GPI13 GPI11 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 
TCO_STS: 
  ... raise SMI#
Initializing CPU #0
CPU: vendor Intel device 206a7
CPU: family 06, model 2a, stepping 07
POST: 0x60
Enabling cache
CBFS: CBFS_HEADER_ROM_ADDRESS: 0xfffff9c0/0x800000
CBFS: CBFS location: 0x700000~0x7ff9e0, align: 64
CBFS: Looking for 'cpu_microcode_blob.bin' starting from 0x700000.
CBFS:  - load entry 0x700000 file name (16 bytes)...
CBFS:  (unmatched file @0x700000: cmos_layout.bin)
CBFS:  - load entry 0x7004c0 file name (32 bytes)...
CBFS:  (unmatched file @0x7004c0: pci8086,0106.rom)
CBFS:  - load entry 0x710500 file name (72 bytes)...
CBFS: Found file (offset=0x710560, len=20544).
microcode: sig=0x206a7 pf=0x10 revision=0x28
CPU: Intel(R) Celeron(R) CPU 867 @ 1.30GHz.
memalign Enter, boundary 8, size 24, free_mem_ptr 00160be1
memalign 00160be8
memalign Enter, boundary 8, size 24, free_mem_ptr 00160c00
memalign 00160c00
memalign Enter, boundary 8, size 24, free_mem_ptr 00160c18
memalign 00160c18
memalign Enter, boundary 8, size 24, free_mem_ptr 00160c30
memalign 00160c30
memalign Enter, boundary 8, size 24, free_mem_ptr 00160c48
memalign 00160c48
memalign Enter, boundary 8, size 24, free_mem_ptr 00160c60
memalign 00160c60
memalign Enter, boundary 8, size 24, free_mem_ptr 00160c78
memalign 00160c78
memalign Enter, boundary 8, size 24, free_mem_ptr 00160c90
memalign 00160c90
memalign Enter, boundary 8, size 24, free_mem_ptr 00160ca8
memalign 00160ca8
memalign Enter, boundary 8, size 24, free_mem_ptr 00160cc0
memalign 00160cc0
memalign Enter, boundary 8, size 24, free_mem_ptr 00160cd8
memalign 00160cd8
memalign Enter, boundary 8, size 24, free_mem_ptr 00160cf0
memalign 00160cf0
memalign Enter, boundary 8, size 24, free_mem_ptr 00160d08
memalign 00160d08
memalign Enter, boundary 8, size 24, free_mem_ptr 00160d20
memalign 00160d20
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x000000007c800000 size 0x7c740000 type 6
0x000000007c800000 - 0x00000000d0000000 size 0x53800000 type 0
0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
0x00000000e0000000 - 0x00000000ff800000 size 0x1f800000 type 0
0x00000000ff800000 - 0x0000000100000000 size 0x00800000 type 5
0x0000000100000000 - 0x0000000100600000 size 0x00600000 type 6
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
MTRR: default type WB/UC MTRR counts: 13/7.
MTRR: UC selected as default type.
MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6
MTRR: 1 base 0x000000007c800000 mask 0x0000000fff800000 type 0
MTRR: 2 base 0x000000007d000000 mask 0x0000000fff000000 type 0
MTRR: 3 base 0x000000007e000000 mask 0x0000000ffe000000 type 0
MTRR: 4 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
MTRR: 5 base 0x00000000ff800000 mask 0x0000000fff800000 type 0
MTRR: 6 base 0x0000000100000000 mask 0x0000000f00000000 type 6

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

POST: 0x93
Setting up local apic... apic_id: 0x00 done.
POST: 0x9b
Enabling VMX
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 1300
Turbo is unavailable
CPU: 0 has 2 cores, 1 threads per core
memalign Enter, boundary 8, size 152, free_mem_ptr 00160d38
memalign 00160d38
CPU: 0 has core 2
CPU1: stack_base 0015e000, stack_end 0015eff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 2.
After apic_write.
Initializing CPU #1
Startup point 1.
Waiting for send to finish...
+CPU: vendor Intel device 206a7
Sending STARTUP #2 to 2.
After apic_write.
CPU: family 06, model 2a, stepping 07
Startup point 1.
Waiting for send to finish...
+POST: 0x60After Startup.
CPU #0 initialized
Waiting for 1 CPUS to stop

Enabling cache
CBFS: CBFS_HEADER_ROM_ADDRESS: 0xfffff9c0/0x800000
CBFS: CBFS location: 0x700000~0x7ff9e0, align: 64
CBFS: Looking for 'cpu_microcode_blob.bin' starting from 0x700000.
CBFS:  - load entry 0x700000 file name (16 bytes)...
CBFS:  (unmatched file @0x700000: cmos_layout.bin)
CBFS:  - load entry 0x7004c0 file name (32 bytes)...
CBFS:  (unmatched file @0x7004c0: pci8086,0106.rom)
CBFS:  - load entry 0x710500 file name (72 bytes)...
CBFS: Found file (offset=0x710560, len=20544).
microcode: sig=0x206a7 pf=0x10 revision=0x0
microcode: updated to revision 0x28 date=2012-04-24
CPU: Intel(R) Celeron(R) CPU 867 @ 1.30GHz.
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6
MTRR: 1 base 0x000000007c800000 mask 0x0000000fff800000 type 0
MTRR: 2 base 0x000000007d000000 mask 0x0000000fff000000 type 0
MTRR: 3 base 0x000000007e000000 mask 0x0000000ffe000000 type 0
MTRR: 4 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
MTRR: 5 base 0x00000000ff800000 mask 0x0000000fff800000 type 0
MTRR: 6 base 0x0000000100000000 mask 0x0000000f00000000 type 6

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

POST: 0x93
Setting up local apic... apic_id: 0x02 done.
POST: 0x9b
Enabling VMX
model_x06ax: energy policy set to 6
model_x06ax: frequency set to 1300
CPU #1 initialized
All AP CPUs stopped (5244 loops)
CPU1: stack: 0015e000 - 0015f000, lowest used address 0015ec6c, stack used: 916 bytes
PCI: 00:00.0 init
Set BIOS_RESET_CPL
CPU TDP: 17 Watts
PCI: 00:02.0 init
GT Power Management Init
SNB GT1 Power Meter Weights
GT Power Management Init (post VBIOS)
PCI: 00:16.0 init
PCI READ [40] : 0x00000040
PCI READ [48] : 0x00000048
ME: FW Partition Table      : OK
ME: Bringup Loader Failure  : NO
ME: Firmware Init Complete  : NO
ME: Manufacturing Mode      : YES
ME: Boot Options Present    : NO
ME: Update In Progress      : NO
ME: Current Working State   : Normal
ME: Current Operation State : M0 with UMA
ME: Current Operation Mode  : Normal
ME: Error Code              : No Error
ME: Progress Phase          : Host Communication
ME: Power Management Event  : Clean Moff->Mx wake
ME: Progress Phase State    : Host communication established
ME: BIOS path: Normal
PCI READ [bc] : 0x000000bc
ME: Extend SHA-256: 5f466e1c69b5fe232b5bb547939edd493c81c66fa0394befb8b672426018f72a
READ     [04] : cbd=128 cbrp=00 cbwp=00 ready=0 reset=0 ig=0 is=1 ie=0
WRITE    [04] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=1 is=1 ie=0
READ     [04] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
WRITE    [00] : CB: 0x80040007
WRITE    [00] : CB: 0x000002ff
READ     [04] : cbd=128 cbrp=00 cbwp=02 ready=1 reset=0 ig=0 is=0 ie=0
WRITE    [04] : cbd=128 cbrp=00 cbwp=02 ready=1 reset=0 ig=1 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=1
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=128 cbrp=00 cbwp=00 ready=1 reset=0 ig=0 is=0 ie=0
READ     [0c] : cbd=

*** Log truncated, 28841 characters dropped. ***

POST: 0x8a
Updating MRC cache data.
No FMAP found at ffe70000.
FMAP: area RW_MRC_CACHE not found
find_current_mrc_cache_local: No valid MRC cache found.
read 6000 from 07e4
read 00000000 from 0880
wrote 00000000 to 0880
memalign Enter, boundary 8, size 12, free_mem_ptr 00160dd0
memalign 00160dd0
read 00c0 from 0870
wrote 000c to 0870
wrote 9f to 0878
read 0000 from 0876
wrote 0000 to 0876
read 0000 from 0874
wrote 00000000 to 07e8
wrote 4402 to 0871
read 00c4 from 0870
wrote 0004 to 0870
read 001740ef from 07f0
read 00 from 07f4
wrote 0000 to 0874
SF: Got idcodes
memalign Enter, boundary 8, size 32, free_mem_ptr 00160ddc
memalign 00160de0
SF: Detected W25Q64 with page size 1000, total 800000
Need to erase the MRC cache region of -1 bytes at 00117f49
SF: Erase offset/length not multiple of erase size
Finally: write MRC cache update to flash at 00117f49
PP: 0x7c6c0200 => cmd = { 0x02 0x917f49 } chunk_len = 55
read 00c0 from 0870
wrote 000c to 0870
wrote 06 to 0878
read 0000 from 0876
wrote 0001 to 0876
wrote 0006 to 0874
read 00c0 from 0870
wrote 000c to 0870
wrote 02 to 0878
read 0001 from 0876
wrote 0003 to 0876
read 0006 from 0874
wrote 00917f49 to 07e8
wrote 4443524d to 07f0
wrote 00000b50 to 07f4
wrote 0000912b to 07f8
wrote 00000000 to 07fc
wrote 00187999 to 0800
wrote 0a145454 to 0804
wrote 0a023220 to 0808
wrote 00005690 to 080c
wrote 00000000 to 0810
wrote 00000000 to 0814
wrote 00100005 to 0818
wrote 20202020 to 081c
wrote 000e0000 to 0820
wrote 00 to 0824
wrote 00 to 0825
wrote 00 to 0826
wrote 7606 to 0871
read 04cc from 0870
wrote 000c to 0870
ICH SPI: Data transaction error
SF: Failed to send write command (55 bytes): -1
SF: Winbond Page Program failed
High Tables Base is 7c6c0000.
POST: 0x9b
Writing ISA IRQs
automatic IRQ entry for PCI: 00:00.0: INTA# -> IOAPIC 4 PIN 16
automatic IRQ entry for PCI: 00:02.0: INTA# -> IOAPIC 4 PIN 16
automatic IRQ entry for PCI: 00:16.0: INTA# -> IOAPIC 4 PIN 16
fixed IRQ entry for: PCI: 00:1a.0: INTA# -> IOAPIC 4 PIN 17
fixed IRQ entry for: PCI: 00:1b.0: INTA# -> IOAPIC 4 PIN 22
automatic IRQ entry for PCI: 00:1c.0: INTA# -> IOAPIC 4 PIN 16
automatic IRQ entry for PCI: 00:1c.3: INTD# -> IOAPIC 4 PIN 18
fixed IRQ entry for: PCI: 00:1d.0: INTA# -> IOAPIC 4 PIN 19
fixed IRQ entry for: PCI: 00:1f.0: INTA# -> IOAPIC 4 PIN 16
fixed IRQ entry for: PCI: 00:1f.2: INTA# -> IOAPIC 4 PIN 16
fixed IRQ entry for: PCI: 00:1f.3: INTC# -> IOAPIC 4 PIN 23
automatic IRQ entry for PCI: 00:1f.6: INTC# -> IOAPIC 4 PIN 18
automatic IRQ entry for PCI: 01:00.0: INTA# -> IOAPIC 4 PIN 16
automatic IRQ entry for PCI: 02:00.0: INTA# -> IOAPIC 4 PIN 19
Wrote the mp table end at: 000f0010 - 000f0184
MPTABLE len: 388
Adding CBMEM entry as no. 4
Writing ISA IRQs
automatic IRQ entry for PCI: 00:00.0: INTA# -> IOAPIC 4 PIN 16
automatic IRQ entry for PCI: 00:02.0: INTA# -> IOAPIC 4 PIN 16
automatic IRQ entry for PCI: 00:16.0: INTA# -> IOAPIC 4 PIN 16
fixed IRQ entry for: PCI: 00:1a.0: INTA# -> IOAPIC 4 PIN 17
fixed IRQ entry for: PCI: 00:1b.0: INTA# -> IOAPIC 4 PIN 22
automatic IRQ entry for PCI: 00:1c.0: INTA# -> IOAPIC 4 PIN 16
automatic IRQ entry for PCI: 00:1c.3: INTD# -> IOAPIC 4 PIN 18
fixed IRQ entry for: PCI: 00:1d.0: INTA# -> IOAPIC 4 PIN 19
fixed IRQ entry for: PCI: 00:1f.0: INTA# -> IOAPIC 4 PIN 16
fixed IRQ entry for: PCI: 00:1f.2: INTA# -> IOAPIC 4 PIN 16
fixed IRQ entry for: PCI: 00:1f.3: INTC# -> IOAPIC 4 PIN 23
automatic IRQ entry for PCI: 00:1f.6: INTC# -> IOAPIC 4 PIN 18
automatic IRQ entry for PCI: 01:00.0: INTA# -> IOAPIC 4 PIN 16
automatic IRQ entry for PCI: 02:00.0: INTA# -> IOAPIC 4 PIN 19
Wrote the mp table end at: 7c6d1010 - 7c6d1184
MPTABLE len: 388
MP table: 388 bytes.
POST: 0x9c
Adding CBMEM entry as no. 5
ACPI: Writing ACPI tables at 7c6d2000.
ACPI:    * FACS
ACPI:    * DSDT
ACPI:    * FADT
ACPI: added table 1/32, length now 40
ACPI:    * HPET
ACPI: added table 2/32, length now 44
ACPI:    * MADT
ACPI: added table 3/32, length now 48
ACPI:    * MCFG
ACPI: added table 4/32, length now 52
ACPI: Patching up global NVS in DSDT at offset 0x0158 -> 0x7c6d5ae0
Adding CBMEM entry as no. 6
.ACPI:     * DSDT @ 7c6d2250 Length 36af
ACPI:     * SSDT
Found 1 CPU(s) with 2 core(s) each.
PSS: 1300MHz power 17000 control 0xd00 status 0xd00
PSS: 1000MHz power 12628 control 0xa00 status 0xa00
PSS: 800MHz power 9859 control 0x800 status 0x800
PSS: 1300MHz power 17000 control 0xd00 status 0xd00
PSS: 1000MHz power 12628 control 0xa00 status 0xa00
PSS: 800MHz power 9859 control 0x800 status 0x800
ACPI: added table 5/32, length now 56
current = 7c6d7200
ACPI: done.
ACPI tables: 20992 bytes.
Adding CBMEM entry as no. 7
smbios_write_tables: 7c6dd600
CBFS: CBFS_HEADER_ROM_ADDRESS: 0xfffff9c0/0x800000
Root Device (SAMSUNG Lumpy)
CPU_CLUSTER: 0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge)
APIC: 00 (Socket rPGA989 CPU)
APIC: acac (Intel SandyBridge/IvyBridge CPU)
DOMAIN: 0000 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge)
PCI: 00:00.0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge)
PCI: 00:02.0 (Intel i7 (SandyBridge/IvyBridge) integrated Northbridge)
PCI: 00:16.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:16.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:16.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:16.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:19.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1a.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1b.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.4 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.6 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1c.7 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1d.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1e.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1f.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PNP: 002e.1 (SMSC MEC1308 EC SuperIO Interface)
PNP: 002e.2 (SMSC MEC1308 EC SuperIO Interface)
PNP: 002e.3 (SMSC MEC1308 EC SuperIO Interface)
PNP: 002e.4 (SMSC MEC1308 EC SuperIO Interface)
PNP: 002e.7 (SMSC MEC1308 EC SuperIO Interface)
PNP: 002e.8 (SMSC MEC1308 EC SuperIO Interface)
PNP: 002e.9 (SMSC MEC1308 EC SuperIO Interface)
PNP: 00ff.1 (SMSC MEC1308 EC Mailbox Interface)
IOAPIC: 04 (IOAPIC)
PCI: 00:1f.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1f.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1f.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 00:1f.6 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
PCI: 01:00.0 (unknown)
PCI: 02:00.0 (unknown)
APIC: 02 (unknown)
SMBIOS tables: 398 bytes.
POST: 0x9e
Adding CBMEM entry as no. 8
POST: 0x9d
Adding CBMEM entry as no. 9
Writing table forward entry at 0x00000500
Wrote coreboot table at: 00000500, 0x10 bytes, checksum a560
Table forward entry ends at 0x00000528.
... aligned to 0x00001000
Writing coreboot table at 0x7c7dde00
rom_table_end = 0x7c7dde00
... aligned to 0x7c7e0000
memalign Enter, boundary 8, size 24, free_mem_ptr 00160e00
memalign 00160e00
memalign Enter, boundary 8, size 24, free_mem_ptr 00160e18
memalign 00160e18
memalign Enter, boundary 8, size 24, free_mem_ptr 00160e30
memalign 00160e30
memalign Enter, boundary 8, size 24, free_mem_ptr 00160e48
memalign 00160e48
memalign Enter, boundary 8, size 24, free_mem_ptr 00160e60
memalign 00160e60
memalign Enter, boundary 8, size 24, free_mem_ptr 00160e78
memalign 00160e78
 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
 1. 0000000000001000-000000000009ffff: RAM
 2. 00000000000a0000-00000000000fffff: RESERVED
 3. 0000000000100000-000000001fffffff: RAM
 4. 0000000020000000-00000000201fffff: RESERVED
 5. 0000000020200000-000000003fffffff: RAM
 6. 0000000040000000-00000000401fffff: RESERVED
 7. 0000000040200000-000000007c6bffff: RAM
 8. 000000007c6c0000-000000007c7fffff: CONFIGURATION TABLES
 9. 000000007c800000-000000007f1fffff: RESERVED
10. 00000000f0000000-00000000f3ffffff: RESERVED
11. 0000000100000000-00000001005fffff: RAM
.Wrote coreboot table at: 7c7dde00, 0x350 bytes, checksum 4b2a
coreboot table: 872 bytes.
POST: 0x9d
Multiboot Information structure has been written.
FREE SPACE  0. 7c7e5e00 0001a200
MRC DATA    1. 7c6c0200 00000c00
CONSOLE     2. 7c6c0e00 00010000
GDT         3. 7c6d0e00 00000200
SMP TABLE   4. 7c6d1000 00001000
ACPI        5. 7c6d2000 0000b400
GNVS PTR    6. 7c6dd400 00000200
SMBIOS      7. 7c6dd600 00000800
ACPI RESUME 8. 7c6dde00 00100000
COREBOOT    9. 7c7dde00 00008000
CBFS: CBFS_HEADER_ROM_ADDRESS: 0xfffff9c0/0x800000
CBFS: CBFS location: 0x700000~0x7ff9e0, align: 64
CBFS: Looking for 'fallback/payload' starting from 0x700000.
CBFS:  - load entry 0x700000 file name (16 bytes)...
CBFS:  (unmatched file @0x700000: cmos_layout.bin)
CBFS:  - load entry 0x7004c0 file name (32 bytes)...
CBFS:  (unmatched file @0x7004c0: pci8086,0106.rom)
CBFS:  - load entry 0x710500 file name (72 bytes)...
CBFS:  (unmatched file @0x710500: cpu_microcode_blob.bin)
CBFS:  - load entry 0x7155c0 file name (32 bytes)...
CBFS:  (unmatched file @0x7155c0: fallback/romstage)
CBFS:  - load entry 0x71e980 file name (32 bytes)...
CBFS:  (unmatched file @0x71e980: fallback/coreboot_ram)
CBFS:  - load entry 0x7682c0 file name (16 bytes)...
CBFS:  (unmatched file @0x7682c0: )
CBFS:  - load entry 0x77ffc0 file name (40 bytes)...
CBFS:  (unmatched file @0x77ffc0: mrc.cache)
CBFS:  - load entry 0x780000 file name (32 bytes)...
CBFS: Found file (offset=0x780038, len=106668).
Loading segment from rom address 0xfff80038
  code (compression=0)
memalign Enter, boundary 8, size 28, free_mem_ptr 00160e90
memalign 00160e90
  New segment dstaddr 0xe5f8c memsize 0x1a074 srcaddr 0xfff80070 filesize 0x1a074
  (cleaned up) New segment addr 0xe5f8c size 0x1a074 offset 0xfff80070 filesize 0x1a074
Loading segment from rom address 0xfff80054
  Entry Point 0x000fd505
Payload (probably SeaBIOS) loaded into a reserved area in the lower 1MB
Loading Segment: addr: 0x00000000000e5f8c memsz: 0x000000000001a074 filesz: 0x000000000001a074
lb: [0x0000000000100000, 0x0000000000164050)
Post relocation: addr: 0x00000000000e5f8c memsz: 0x000000000001a074 filesz: 0x000000000001a074
it's not compressed!
[ 0x000e5f8c, 00100000, 0x00100000) <- fff80070
dest 000e5f8c, end 00100000, bouncebuffer 7c5f7f60
Loaded segments
PCH watchdog disabled
Jumping to boot code at 000fd505
POST: 0xf8
CPU0: stack: 0015f000 - 00160000, lowest used address 0015fa38, stack used: 1480 bytes
entry    = 0x000fd505
lb_start = 0x00100000
lb_size  = 0x00064050
buffer   = 0x7c5f7f60
----- [ seabios log starts here ] -----
Found coreboot cbmem console @ 7c6c0e00
Found mainboard SAMSUNG Lumpy
Relocating init from 0x000e7051 to 0x7c6a5a10 (size 42184)
Found CBFS header at 0xfffff9c0
CPU Mhz=1297
Found 14 PCI devices (max PCI bus is 02)
Copying MPTABLE from 0x7c6d1000/7c6d1010 to 0x000f1390
Copying ACPI RSDP from 0x7c6d2000 to 0x000f1360
Copying SMBIOS entry point from 0x7c6dd600 to 0x000f1340
Using pmtimer, ioport 0x508
Scan for VGA option rom
Running option rom at c000:0003
Changing serial settings was ff/ff now 3/0
Turning on vga text mode console
SeaBIOS (version rel-1.7.3-18-g7093aa5-dirty-20130729_152740-john-samsung-550-chromebook)
EHCI init on dev 00:1a.0 (regs=0xe0605820)
EHCI init on dev 00:1d.0 (regs=0xe0605c20)
Found 0 lpt ports
Found 0 serial ports
AHCI controller at 1f.2, iobase e0605000, irq 10
Searching bootorder for: /pci@i0cf8/*@1f,2/drive@0/disk@0
AHCI/0: registering: "AHCI/0: SanDisk SSD U100 16GB ATA-9 Hard-Disk (15272 MiBytes)"
PS2 keyboard initialized
Initialized USB HUB (0 ports used)
Initialized USB HUB (0 ports used)
All threads complete.
Scan for option roms

Press ESC for boot menu.

Searching bootorder for: HALT
drive 0x000f12d0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=31277232
Space available for UMB: cf000-ee000, f0000-f12d0
Returned 65536 bytes of ZoneHigh
e820 map has 11 items:
  0: 0000000000000000 - 000000000009fc00 = 1 RAM
  1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
  2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
  3: 0000000000100000 - 0000000020000000 = 1 RAM
  4: 0000000020000000 - 0000000020200000 = 2 RESERVED
  5: 0000000020200000 - 0000000040000000 = 1 RAM
  6: 0000000040000000 - 0000000040200000 = 2 RESERVED
  7: 0000000040200000 - 000000007c6c0000 = 1 RAM
  8: 000000007c6c0000 - 000000007f200000 = 2 RESERVED
  9: 00000000f0000000 - 00000000f4000000 = 2 RESERVED
  10: 0000000100000000 - 0000000100600000 = 1 RAM
Changing serial settings was ff/ff now 3/0
enter handle_19:
  NULL
Booting from Hard Disk...
Booting from 0000:7c00